arm64: dts: rockchip: add u2phy1_otg node for rk3399

RK3399 SoC USB2 PHY1 comprises with one host-port and
one otg-port, now we support PHY1 otg-port.

Change-Id: I8e7fd53ce6f1552172044ad2adc3f19e923d1bcd
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 2d88cf00c4c44b8fbfabf950a76b3a03cb76fee3..ee2b83effbafb2746fe3203c8d8a82c4f5682b80 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1222,6 +1222,16 @@
                        clock-output-names = "clk_usbphy1_480m";
                        status = "disabled";
 
+                       u2phy1_otg: otg-port {
+                               #phy-cells = <0>;
+                               interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "otg-bvalid", "otg-id",
+                                                 "linestate";
+                               status = "disabled";
+                       };
+
                        u2phy1_host: host-port {
                                #phy-cells = <0>;
                                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;