help
Support for TI's DaVinci platform.
-config ARCH_OMAP
- bool "TI OMAP"
+config ARCH_OMAP1
+ bool "TI OMAP1"
depends on MMU
select ARCH_HAS_CPUFREQ
select ARCH_HAS_HOLES_MEMORYMODEL
- select ARCH_REQUIRE_GPIOLIB
- select CLKSRC_MMIO
- select GENERIC_CLOCKEVENTS
- select HAVE_CLK
- help
- Support for TI's OMAP platform (OMAP1/2/3/4).
-
-config ARCH_VT8500_SINGLE
- bool "VIA/WonderMedia 85xx"
- select ARCH_HAS_CPUFREQ
+ select ARCH_OMAP
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
- select COMMON_CLK
- select CPU_ARM926T
+ select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
select HAVE_CLK
- select MULTI_IRQ_HANDLER
- select SPARSE_IRQ
- select USE_OF
+ select HAVE_IDE
+ select IRQ_DOMAIN
+ select NEED_MACH_IO_H if PCCARD
+ select NEED_MACH_MEMORY_H
help
- Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
+ Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
endchoice
Say Y here if you want kernel low-level debugging support
on MVEBU based platforms.
+ config DEBUG_OMAP2PLUS_UART
+ bool "Kernel low-level debugging messages via OMAP2PLUS UART"
+ depends on ARCH_OMAP2PLUS
+ help
+ Say Y here if you want kernel low-level debugging support
+ on OMAP2PLUS based platforms.
+
config DEBUG_PICOXCELL_UART
depends on ARCH_PICOXCELL
bool "Use PicoXcell UART for low-level debug"
of the tiles using the RS1 memory map, including all new A-class
core tiles, FPGA-based SMMs and software models.
+ config DEBUG_VT8500_UART0
+ bool "Use UART0 on VIA/Wondermedia SoCs"
+ depends on ARCH_VT8500
+ help
+ This option selects UART0 on VIA/Wondermedia System-on-a-chip
+ devices, including VT8500, WM8505, WM8650 and WM8850.
+
config DEBUG_LL_UART_NONE
bool "No low-level debugging UART"
depends on !ARCH_MULTIPLATFORM
Choose UART port on which kernel low-level debug messages
should be output.
+choice
+ prompt "Low-level debug console UART"
+ depends on DEBUG_OMAP2PLUS_UART
+
+ config DEBUG_OMAP2UART1
+ bool "OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards)"
+ help
+ This covers at least h4, 2430sdp, 3430sdp, 3630sdp,
+ omap3 torpedo and 3530 lv som.
+
+ config DEBUG_OMAP2UART2
+ bool "OMAP2/3/4 UART2"
+
+ config DEBUG_OMAP2UART3
+ bool "OMAP2 UART3 (n8x0)"
+
+ config DEBUG_OMAP3UART3
+ bool "OMAP3 UART3 (most omap3 boards)"
+ help
+ This covers at least cm_t3x, beagle, crane, devkit8000,
+ igep00x0, ldp, n900, n9(50), pandora, overo, touchbook,
+ and 3517evm.
+
+ config DEBUG_OMAP4UART3
+ bool "OMAP4/5 UART3 (omap4 blaze, panda, omap5 sevm)"
+
+ config DEBUG_OMAP3UART4
+ bool "OMAP36XX UART4"
+
+ config DEBUG_OMAP4UART4
+ bool "OMAP4/5 UART4"
+
+ config DEBUG_TI81XXUART1
+ bool "TI81XX UART1 (ti8148evm)"
+
+ config DEBUG_TI81XXUART2
+ bool "TI81XX UART2"
+
+ config DEBUG_TI81XXUART3
+ bool "TI81XX UART3 (ti8168evm)"
+
+ config DEBUG_AM33XXUART1
+ bool "AM33XX UART1"
+
+ config DEBUG_ZOOM_UART
+ bool "Zoom2/3 UART"
+endchoice
+
choice
prompt "Low-level debug console UART"
depends on DEBUG_LL && DEBUG_TEGRA_UART
DEBUG_IMX6Q_UART
default "debug/highbank.S" if DEBUG_HIGHBANK_UART
default "debug/mvebu.S" if DEBUG_MVEBU_UART
+ default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+ default "debug/vt8500.S" if DEBUG_VT8500_UART0
default "debug/tegra.S" if DEBUG_TEGRA_UART
default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
default "mach/debug-macro.S"
CONFIG_ARCH_SOCFPGA=y
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
+CONFIG_ARCH_ZYNQ=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_SMP=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
-CONFIG_GPIOLIB=y
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP2PLUS=y
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_ARCH_VEXPRESS_CA9X4=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
CONFIG_NO_HZ=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C_CHARDEV=y
CONFIG_SPI=y
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_SDIO_UART=y
+CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
CONFIG_RTC_CLASS=y
--- /dev/null
+/*
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/serial_reg.h>
+
+/* OMAP2 serial ports */
+#define OMAP2_UART1_BASE 0x4806a000
+#define OMAP2_UART2_BASE 0x4806c000
+#define OMAP2_UART3_BASE 0x4806e000
+
+/* OMAP3 serial ports */
+#define OMAP3_UART1_BASE OMAP2_UART1_BASE
+#define OMAP3_UART2_BASE OMAP2_UART2_BASE
+#define OMAP3_UART3_BASE 0x49020000
+#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
+#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
+
+/* OMAP4 serial ports */
+#define OMAP4_UART1_BASE OMAP2_UART1_BASE
+#define OMAP4_UART2_BASE OMAP2_UART2_BASE
+#define OMAP4_UART3_BASE 0x48020000
+#define OMAP4_UART4_BASE 0x4806e000
+
+/* TI81XX serial ports */
+#define TI81XX_UART1_BASE 0x48020000
+#define TI81XX_UART2_BASE 0x48022000
+#define TI81XX_UART3_BASE 0x48024000
+
+/* AM3505/3517 UART4 */
+#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
+
+/* AM33XX serial port */
+#define AM33XX_UART1_BASE 0x44E09000
+
+/* OMAP5 serial ports */
+#define OMAP5_UART1_BASE OMAP2_UART1_BASE
+#define OMAP5_UART2_BASE OMAP2_UART2_BASE
+#define OMAP5_UART3_BASE OMAP4_UART3_BASE
+#define OMAP5_UART4_BASE OMAP4_UART4_BASE
+#define OMAP5_UART5_BASE 0x48066000
+#define OMAP5_UART6_BASE 0x48068000
+
+/* External port on Zoom2/3 */
+#define ZOOM_UART_BASE 0x10000000
+#define ZOOM_UART_VIRT 0xfa400000
+
+#define OMAP_PORT_SHIFT 2
+#define ZOOM_PORT_SHIFT 1
+
+#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
+
+ .pushsection .data
+omap_uart_phys: .word 0
+omap_uart_virt: .word 0
+omap_uart_lsr: .word 0
+ .popsection
+
+ .macro addruart, rp, rv, tmp
+
+ /* Use omap_uart_phys/virt if already configured */
+10: adr \rp, 99f @ get effective addr of 99f
+ ldr \rv, [\rp] @ get absolute addr of 99f
+ sub \rv, \rv, \rp @ offset between the two
+ ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
+ sub \tmp, \rp, \rv @ make it effective
+ ldr \rp, [\tmp, #0] @ omap_uart_phys
+ ldr \rv, [\tmp, #4] @ omap_uart_virt
+ cmp \rp, #0 @ is port configured?
+ cmpne \rv, #0
+ bne 100f @ already configured
+
+ /* Configure the UART offset from the phys/virt base */
+#ifdef CONFIG_DEBUG_OMAP2UART1
+ mov \rp, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_OMAP2UART2
+ mov \rp, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_OMAP2UART3
+ mov \rp, #UART_OFFSET(OMAP2_UART3_BASE)
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_OMAP3UART3
+ mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+ add \rp, \rp, #0x00fb0000
+ add \rp, \rp, #0x00006000 @ OMAP3_UART3_BASE
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_OMAP4UART3
+ mov \rp, #UART_OFFSET(OMAP4_UART3_BASE)
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_OMAP3UART4
+ mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+ add \rp, \rp, #0x00fb0000
+ add \rp, \rp, #0x00028000 @ OMAP3_UART4_BASE
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_OMAP4UART4
+ mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_TI81XXUART1
+ mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_TI81XXUART2
+ mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_TI81XXUART3
+ mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
+ b 98f
+#endif
+#ifdef CONFIG_DEBUG_AM33XXUART1
+ ldr \rp, =AM33XX_UART1_BASE
+ and \rp, \rp, #0x00ffffff
+ b 97f
+#endif
+#ifdef CONFIG_DEBUG_ZOOM_UART
+ ldr \rp, =ZOOM_UART_BASE
+ str \rp, [\tmp, #0] @ omap_uart_phys
+ ldr \rp, =ZOOM_UART_VIRT
+ str \rp, [\tmp, #4] @ omap_uart_virt
+ mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
+ str \rp, [\tmp, #8] @ omap_uart_lsr
+#endif
+ b 10b
+
+ /* AM33XX: Store both phys and virt address for the uart */
+97: add \rp, \rp, #0x44000000 @ phys base
+ str \rp, [\tmp, #0] @ omap_uart_phys
+ sub \rp, \rp, #0x44000000 @ phys base
+ add \rp, \rp, #0xf9000000 @ virt base
+ str \rp, [\tmp, #4] @ omap_uart_virt
+ mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
+ str \rp, [\tmp, #8] @ omap_uart_lsr
+
+ b 10b
+
+ /* Store both phys and virt address for the uart */
+98: add \rp, \rp, #0x48000000 @ phys base
+ str \rp, [\tmp, #0] @ omap_uart_phys
+ sub \rp, \rp, #0x48000000 @ phys base
+ add \rp, \rp, #0xfa000000 @ virt base
+ str \rp, [\tmp, #4] @ omap_uart_virt
+ mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
+ str \rp, [\tmp, #8] @ omap_uart_lsr
+
+ b 10b
+
+ .align
+99: .word .
+ .word omap_uart_phys
+ .ltorg
+
+100: /* Pass the UART_LSR reg address */
+ ldr \tmp, [\tmp, #8] @ omap_uart_lsr
+ add \rp, \rp, \tmp
+ add \rv, \rv, \tmp
+ .endm
+
+ .macro senduart,rd,rx
+ orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
+ bic \rx, \rx, #0xff @ get base (THR) reg address
+ strb \rd, [\rx] @ send lower byte of rd
+ orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
+ bic \rd, \rd, #(0xff << 24) @ restore original rd
+ .endm
+
+ .macro busyuart,rd,rx
+1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
+ and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
+ teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
+ bne 1001b
+ .endm
+
+ .macro waituart,rd,rx
+ .endm
--- /dev/null
+/*
+ * Debugging macro include header
+ *
+ * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
+ * Moved from arch/arm/mach-vt8500/include/mach/debug-macro.S
+ * Minor changes for readability.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define DEBUG_LL_PHYS_BASE 0xD8000000
+#define DEBUG_LL_VIRT_BASE 0xF8000000
+#define DEBUG_LL_UART_OFFSET 0x00200000
+
+#if defined(CONFIG_DEBUG_VT8500_UART0)
+ .macro addruart, rp, rv, tmp
+ mov \rp, #DEBUG_LL_UART_OFFSET
+ orr \rv, \rp, #DEBUG_LL_VIRT_BASE
+ orr \rp, \rp, #DEBUG_LL_PHYS_BASE
+ .endm
+
+ .macro senduart,rd,rx
+ strb \rd, [\rx, #0]
+ .endm
+
+ .macro busyuart,rd,rx
+1001: ldr \rd, [\rx, #0x1c]
+ ands \rd, \rd, #0x2
+ bne 1001b
+ .endm
+
+ .macro waituart,rd,rx
+ .endm
+
+#endif
#include <linux/init.h>
#include <linux/device.h>
#include <linux/io.h>
-
+#include <linux/dma-mapping.h>
#include <linux/omap-dma.h>
#include <mach/tc.h>
return errata;
}
+static const struct platform_device_info omap_dma_dev_info = {
+ .name = "omap-dma-engine",
+ .id = -1,
+ .dma_mask = DMA_BIT_MASK(32),
+};
+
static int __init omap1_system_dma_init(void)
{
struct omap_system_dma_plat_info *p;
struct omap_dma_dev_attr *d;
- struct platform_device *pdev;
+ struct platform_device *pdev, *dma_pdev;
int ret;
pdev = platform_device_alloc("omap_dma_system", 0);
dma_common_ch_start = CPC;
dma_common_ch_end = COLOR;
+ dma_pdev = platform_device_register_full(&omap_dma_dev_info);
+ if (IS_ERR(dma_pdev)) {
+ ret = PTR_ERR(dma_pdev);
+ goto exit_release_pdev;
+ }
+
return ret;
+exit_release_pdev:
+ platform_device_del(pdev);
exit_release_chan:
kfree(d->chan);
exit_release_d:
return platform_device_register(pdev);
}
+
+static int __init omap_i2c_cmdline(void)
+{
+ return omap_register_i2c_bus_cmdline();
+}
+subsys_initcall(omap_i2c_cmdline);
+config ARCH_OMAP
+ bool
+
+config ARCH_OMAP2PLUS
+ bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
+ select ARCH_HAS_CPUFREQ
+ select ARCH_HAS_HOLES_MEMORYMODEL
+ select ARCH_OMAP
+ select ARCH_REQUIRE_GPIOLIB
+ select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
+ select HAVE_CLK
+ select OMAP_DM_TIMER
+ select PINCTRL
+ select PROC_DEVICETREE if PROC_FS
+ select SPARSE_IRQ
+ select USE_OF
+ help
+ Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
+
+
if ARCH_OMAP2PLUS
menu "TI OMAP2/3/4 Specific Features"
config OMAP4_ERRATA_I688
bool "OMAP4 errata: Async Bridge Corruption"
- depends on ARCH_OMAP4
+ depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM
select ARCH_HAS_BARRIERS
help
If a data is stalled inside asynchronous bridge because of back
# Makefile for the linux kernel.
#
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+ -I$(srctree)/arch/arm/plat-omap/include
+
# Common support
obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
}
return 0;
}
-device_initcall(beagle_opp_init);
+omap_device_initcall(beagle_opp_init);
static void __init omap3_beagle_init(void)
{
#include <video/omapdss.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
+#include "soc.h"
#include "board-rx51.h"
#include "mux.h"
return 0;
}
-subsys_initcall(rx51_video_init);
+omap_subsys_initcall(rx51_video_init);
#endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */
return ret;
}
-arch_initcall(omap2xxx_clk_arch_init);
+omap_arch_initcall(omap2xxx_clk_arch_init);
return ret;
}
-arch_initcall(omap3xxx_clk_arch_init);
+omap_arch_initcall(omap3xxx_clk_arch_init);
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
}
-postcore_initcall(omap3_l3_init);
+omap_postcore_initcall(omap3_l3_init);
static int __init omap4_l3_init(void)
{
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
}
-postcore_initcall(omap4_l3_init);
+omap_postcore_initcall(omap4_l3_init);
#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
return 0;
}
-arch_initcall(omap2_init_devices);
+omap_arch_initcall(omap2_init_devices);
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
-
+#include <linux/dma-mapping.h>
#include <linux/omap-dma.h>
#include "soc.h"
return 0;
}
+static const struct platform_device_info omap_dma_dev_info = {
+ .name = "omap-dma-engine",
+ .id = -1,
+ .dma_mask = DMA_BIT_MASK(32),
+};
+
static int __init omap2_system_dma_init(void)
{
- return omap_hwmod_for_each_by_class("dma",
+ struct platform_device *pdev;
+ int res;
+
+ res = omap_hwmod_for_each_by_class("dma",
omap2_system_dma_init_dev, NULL);
+ if (res)
+ return res;
+
+ pdev = platform_device_register_full(&omap_dma_dev_info);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return res;
}
-arch_initcall(omap2_system_dma_init);
+omap_arch_initcall(omap2_system_dma_init);
}
-arch_initcall(omap_init_drm);
+omap_arch_initcall(omap_init_drm);
#endif
return 0;
}
-subsys_initcall(emu_init);
+omap_subsys_initcall(emu_init);
return 0;
}
-arch_initcall(omap_init_vrfb);
+omap_arch_initcall(omap_init_vrfb);
#endif
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
return platform_device_register(&omap_fb_device);
}
-arch_initcall(omap_init_fb);
+omap_arch_initcall(omap_init_fb);
#endif
#include <linux/of.h>
#include <linux/platform_data/gpio-omap.h>
+#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"
#include "omap-pm.h"
/*
* gpio_init needs to be done before
* machine_init functions access gpio APIs.
- * Hence gpio_init is a postcore_initcall.
+ * Hence gpio_init is a omap_postcore_initcall.
*/
static int __init omap2_gpio_init(void)
{
return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, NULL);
}
-postcore_initcall(omap2_gpio_init);
+omap_postcore_initcall(omap2_gpio_init);
}
-postcore_initcall(gpmc_init);
+omap_postcore_initcall(gpmc_init);
module_exit(gpmc_exit);
static int __init omap_gpmc_init(void)
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
}
-postcore_initcall(omap_gpmc_init);
+omap_postcore_initcall(omap_gpmc_init);
static irqreturn_t gpmc_handle_irq(int irq, void *dev)
{
#include <linux/err.h>
#include <linux/platform_device.h>
+#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"
#include "hdq1w.h"
return 0;
}
-arch_initcall(omap_init_hdq);
+omap_arch_initcall(omap_init_hdq);
#include <linux/err.h>
#include <linux/hwspinlock.h>
+#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"
return retval;
}
/* early board code might need to reserve specific hwspinlock instances */
-postcore_initcall(hwspinlocks_init);
+omap_postcore_initcall(hwspinlocks_init);
return PTR_RET(pdev);
}
+static int __init omap_i2c_cmdline(void)
+{
+ return omap_register_i2c_bus_cmdline();
+}
+omap_subsys_initcall(omap_i2c_cmdline);
+++ /dev/null
-/* arch/arm/mach-omap2/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <linux/serial_reg.h>
-
-#include <mach/serial.h>
-
-#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
-
- .pushsection .data
-omap_uart_phys: .word 0
-omap_uart_virt: .word 0
-omap_uart_lsr: .word 0
- .popsection
-
- /*
- * Note that this code won't work if the bootloader passes
- * a wrong machine ID number in r1. To debug, just hardcode
- * the desired UART phys and virt addresses temporarily into
- * the omap_uart_phys and omap_uart_virt above.
- */
- .macro addruart, rp, rv, tmp
-
- /* Use omap_uart_phys/virt if already configured */
-10: adr \rp, 99f @ get effective addr of 99f
- ldr \rv, [\rp] @ get absolute addr of 99f
- sub \rv, \rv, \rp @ offset between the two
- ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
- sub \tmp, \rp, \rv @ make it effective
- ldr \rp, [\tmp, #0] @ omap_uart_phys
- ldr \rv, [\tmp, #4] @ omap_uart_virt
- cmp \rp, #0 @ is port configured?
- cmpne \rv, #0
- bne 100f @ already configured
-
- /* Check the debug UART configuration set in uncompress.h */
- mov \rp, pc
- ldr \rv, =OMAP_UART_INFO_OFS
- and \rp, \rp, #0xff000000
- ldr \rp, [\rp, \rv]
-
- /* Select the UART to use based on the UART1 scratchpad value */
- cmp \rp, #0 @ no port configured?
- beq 21f @ if none, try to use UART1
- cmp \rp, #OMAP2UART1 @ OMAP2/3/4UART1
- beq 21f @ configure OMAP2/3/4UART1
- cmp \rp, #OMAP2UART2 @ OMAP2/3/4UART2
- beq 22f @ configure OMAP2/3/4UART2
- cmp \rp, #OMAP2UART3 @ only on 24xx
- beq 23f @ configure OMAP2UART3
- cmp \rp, #OMAP3UART3 @ only on 34xx
- beq 33f @ configure OMAP3UART3
- cmp \rp, #OMAP4UART3 @ only on 44xx/54xx
- beq 43f @ configure OMAP4/5UART3
- cmp \rp, #OMAP3UART4 @ only on 36xx
- beq 34f @ configure OMAP3UART4
- cmp \rp, #OMAP4UART4 @ only on 44xx/54xx
- beq 44f @ configure OMAP4/5UART4
- cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
- beq 81f @ configure UART1
- cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
- beq 82f @ configure UART2
- cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
- beq 83f @ configure UART3
- cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different
- beq 84f @ configure UART1
- cmp \rp, #ZOOM_UART @ only on zoom2/3
- beq 95f @ configure ZOOM_UART
-
- /* Configure the UART offset from the phys/virt base */
-21: mov \rp, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4
- b 98f
-22: mov \rp, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4
- b 98f
-23: mov \rp, #UART_OFFSET(OMAP2_UART3_BASE)
- b 98f
-33: mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
- add \rp, \rp, #0x00fb0000
- add \rp, \rp, #0x00006000 @ OMAP3_UART3_BASE
- b 98f
-34: mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
- add \rp, \rp, #0x00fb0000
- add \rp, \rp, #0x00028000 @ OMAP3_UART4_BASE
- b 98f
-43: mov \rp, #UART_OFFSET(OMAP4_UART3_BASE)
- b 98f
-44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
- b 98f
-81: mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
- b 98f
-82: mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
- b 98f
-83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
- b 98f
-84: ldr \rp, =AM33XX_UART1_BASE
- and \rp, \rp, #0x00ffffff
- b 97f
-95: ldr \rp, =ZOOM_UART_BASE
- str \rp, [\tmp, #0] @ omap_uart_phys
- ldr \rp, =ZOOM_UART_VIRT
- str \rp, [\tmp, #4] @ omap_uart_virt
- mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
- str \rp, [\tmp, #8] @ omap_uart_lsr
- b 10b
-
- /* AM33XX: Store both phys and virt address for the uart */
-97: add \rp, \rp, #0x44000000 @ phys base
- str \rp, [\tmp, #0] @ omap_uart_phys
- sub \rp, \rp, #0x44000000 @ phys base
- add \rp, \rp, #0xf9000000 @ virt base
- str \rp, [\tmp, #4] @ omap_uart_virt
- mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
- str \rp, [\tmp, #8] @ omap_uart_lsr
-
- b 10b
-
- /* Store both phys and virt address for the uart */
-98: add \rp, \rp, #0x48000000 @ phys base
- str \rp, [\tmp, #0] @ omap_uart_phys
- sub \rp, \rp, #0x48000000 @ phys base
- add \rp, \rp, #0xfa000000 @ virt base
- str \rp, [\tmp, #4] @ omap_uart_virt
- mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
- str \rp, [\tmp, #8] @ omap_uart_lsr
-
- b 10b
-
- .align
-99: .word .
- .word omap_uart_phys
- .ltorg
-
-100: /* Pass the UART_LSR reg address */
- ldr \tmp, [\tmp, #8] @ omap_uart_lsr
- add \rp, \rp, \tmp
- add \rv, \rv, \tmp
- .endm
-
- .macro senduart,rd,rx
- orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
- bic \rx, \rx, #0xff @ get base (THR) reg address
- strb \rd, [\rx] @ send lower byte of rd
- orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
- bic \rd, \rd, #(0xff << 24) @ restore original rd
- .endm
-
- .macro busyuart,rd,rx
-1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
- and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
- teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
- bne 1001b
- .endm
-
- .macro waituart,rd,rx
- .endm
* GNU General Public License for more details.
*/
-/*
- * Memory entry used for the DEBUG_LL UART configuration, relative to
- * start of RAM. See also uncompress.h and debug-macro.S.
- *
- * Note that using a memory location for storing the UART configuration
- * has at least two limitations:
- *
- * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
- * uncompress code could then partially overwrite itself
- * 2. We assume printascii is called at least once before paging_init,
- * and addruart has a chance to read OMAP_UART_INFO
- */
-#define OMAP_UART_INFO_OFS 0x3ffc
-
/* OMAP2 serial ports */
#define OMAP2_UART1_BASE 0x4806a000
#define OMAP2_UART2_BASE 0x4806c000
#define OMAP24XX_BASE_BAUD (48000000/16)
-/*
- * DEBUG_LL port encoding stored into the UART1 scratchpad register by
- * decomp_setup in uncompress.h
- */
-#define OMAP2UART1 21
-#define OMAP2UART2 22
-#define OMAP2UART3 23
-#define OMAP3UART1 OMAP2UART1
-#define OMAP3UART2 OMAP2UART2
-#define OMAP3UART3 33
-#define OMAP3UART4 34 /* Only on 36xx */
-#define OMAP4UART1 OMAP2UART1
-#define OMAP4UART2 OMAP2UART2
-#define OMAP4UART3 43
-#define OMAP4UART4 44
-#define TI81XXUART1 81
-#define TI81XXUART2 82
-#define TI81XXUART3 83
-#define AM33XXUART1 84
-#define OMAP5UART3 OMAP4UART3
-#define OMAP5UART4 OMAP4UART4
-#define ZOOM_UART 95 /* Only on zoom2/3 */
-
#ifndef __ASSEMBLER__
struct omap_board_data;
+++ /dev/null
-/*
- * arch/arm/plat-omap/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-
-#include <mach/serial.h>
-
-#define MDR1_MODE_MASK 0x07
-
-volatile u8 *uart_base;
-int uart_shift;
-
-/*
- * Store the DEBUG_LL uart number into memory.
- * See also debug-macro.S, and serial.c for related code.
- */
-static void set_omap_uart_info(unsigned char port)
-{
- /*
- * Get address of some.bss variable and round it down
- * a la CONFIG_AUTO_ZRELADDR.
- */
- u32 ram_start = (u32)&uart_shift & 0xf8000000;
- u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
- *uart_info = port;
-}
-
-static void putc(int c)
-{
- if (!uart_base)
- return;
-
- /* Check for UART 16x mode */
- if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
- return;
-
- while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
- barrier();
- uart_base[UART_TX << uart_shift] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * Macros to configure UART1 and debug UART
- */
-#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \
- if (machine_is_##mach()) { \
- uart_base = (volatile u8 *)(dbg_uart); \
- uart_shift = (dbg_shft); \
- port = (dbg_id); \
- set_omap_uart_info(port); \
- break; \
- }
-
-#define DEBUG_LL_OMAP2(p, mach) \
- _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \
- OMAP2UART##p)
-
-#define DEBUG_LL_OMAP3(p, mach) \
- _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \
- OMAP3UART##p)
-
-#define DEBUG_LL_OMAP4(p, mach) \
- _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
- OMAP4UART##p)
-
-#define DEBUG_LL_OMAP5(p, mach) \
- _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \
- OMAP5UART##p)
-/* Zoom2/3 shift is different for UART1 and external port */
-#define DEBUG_LL_ZOOM(mach) \
- _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
-
-#define DEBUG_LL_TI81XX(p, mach) \
- _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
- TI81XXUART##p)
-
-#define DEBUG_LL_AM33XX(p, mach) \
- _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
- AM33XXUART##p)
-
-static inline void arch_decomp_setup(void)
-{
- int port = 0;
-
- /*
- * Initialize the port based on the machine ID from the bootloader.
- * Note that we're using macros here instead of switch statement
- * as machine_is functions are optimized out for the boards that
- * are not selected.
- */
- do {
- /* omap2 based boards using UART1 */
- DEBUG_LL_OMAP2(1, omap_2430sdp);
- DEBUG_LL_OMAP2(1, omap_apollon);
- DEBUG_LL_OMAP2(1, omap_h4);
-
- /* omap2 based boards using UART3 */
- DEBUG_LL_OMAP2(3, nokia_n800);
- DEBUG_LL_OMAP2(3, nokia_n810);
- DEBUG_LL_OMAP2(3, nokia_n810_wimax);
-
- /* omap3 based boards using UART1 */
- DEBUG_LL_OMAP2(1, omap3evm);
- DEBUG_LL_OMAP3(1, omap_3430sdp);
- DEBUG_LL_OMAP3(1, omap_3630sdp);
- DEBUG_LL_OMAP3(1, omap3530_lv_som);
- DEBUG_LL_OMAP3(1, omap3_torpedo);
-
- /* omap3 based boards using UART3 */
- DEBUG_LL_OMAP3(3, cm_t35);
- DEBUG_LL_OMAP3(3, cm_t3517);
- DEBUG_LL_OMAP3(3, cm_t3730);
- DEBUG_LL_OMAP3(3, craneboard);
- DEBUG_LL_OMAP3(3, devkit8000);
- DEBUG_LL_OMAP3(3, igep0020);
- DEBUG_LL_OMAP3(3, igep0030);
- DEBUG_LL_OMAP3(3, nokia_rm680);
- DEBUG_LL_OMAP3(3, nokia_rm696);
- DEBUG_LL_OMAP3(3, nokia_rx51);
- DEBUG_LL_OMAP3(3, omap3517evm);
- DEBUG_LL_OMAP3(3, omap3_beagle);
- DEBUG_LL_OMAP3(3, omap3_pandora);
- DEBUG_LL_OMAP3(3, omap_ldp);
- DEBUG_LL_OMAP3(3, overo);
- DEBUG_LL_OMAP3(3, touchbook);
-
- /* omap4 based boards using UART3 */
- DEBUG_LL_OMAP4(3, omap_4430sdp);
- DEBUG_LL_OMAP4(3, omap4_panda);
-
- /* omap5 based boards using UART3 */
- DEBUG_LL_OMAP5(3, omap5_sevm);
-
- /* zoom2/3 external uart */
- DEBUG_LL_ZOOM(omap_zoom2);
- DEBUG_LL_ZOOM(omap_zoom3);
-
- /* TI8168 base boards using UART3 */
- DEBUG_LL_TI81XX(3, ti8168evm);
-
- /* TI8148 base boards using UART1 */
- DEBUG_LL_TI81XX(1, ti8148evm);
-
- /* AM33XX base boards using UART1 */
- DEBUG_LL_AM33XX(1, am335xevm);
- } while (0);
-}
#include <linux/omap-dma.h>
+#include "soc.h"
#include "omap_device.h"
/*
return 0;
}
-arch_initcall(omap2_mcbsp_init);
+omap_arch_initcall(omap2_mcbsp_init);
#include <linux/slab.h>
#include <linux/platform_data/iommu-omap.h>
+#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"
return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL);
}
/* must be ready before omap3isp is probed */
-subsys_initcall(omap_iommu_init);
+omap_subsys_initcall(omap_iommu_init);
static void __exit omap_iommu_exit(void)
{
#include <linux/clk.h>
#include <linux/io.h>
+#include "soc.h"
#include "common.h"
#include "prm2xxx.h"
return 0;
}
-core_initcall(omap2xxx_common_look_up_clks_for_reset);
+omap_core_initcall(omap2xxx_common_look_up_clks_for_reset);
return 0;
}
-early_initcall(omap_l2_cache_init);
+omap_early_initcall(omap_l2_cache_init);
#endif
void __iomem *omap4_get_sar_ram_base(void)
return 0;
}
-early_initcall(omap4_sar_ram_init);
+omap_early_initcall(omap4_sar_ram_init);
void __init omap_gic_of_init(void)
{
#include <linux/of.h>
#include <linux/notifier.h>
+#include "soc.h"
#include "omap_device.h"
#include "omap_hwmod.h"
bus_register_notifier(&platform_bus_type, &platform_nb);
return 0;
}
-core_initcall(omap_device_init);
+omap_core_initcall(omap_device_init);
/**
* omap_device_late_idle - idle devices without drivers
bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
return 0;
}
-late_initcall(omap_device_late_init);
+omap_late_initcall(omap_device_late_init);
return 0;
}
-core_initcall(omap_hwmod_setup_all);
+omap_core_initcall(omap_hwmod_setup_all);
/**
* omap_hwmod_enable - enable an omap_hwmod
return 0;
}
-early_initcall(omap4430_phy_power_down);
+omap_early_initcall(omap4430_phy_power_down);
void am35x_musb_reset(void)
{
return r;
}
-device_initcall(omap3_opp_init);
+omap_device_initcall(omap3_opp_init);
ARRAY_SIZE(omap446x_opp_def_list));
return r;
}
-device_initcall(omap4_opp_init);
+omap_device_initcall(omap4_opp_init);
return 0;
}
-arch_initcall(pm_dbg_init);
+omap_arch_initcall(pm_dbg_init);
#endif
return 0;
}
-postcore_initcall(omap2_common_pm_init);
+omap_postcore_initcall(omap2_common_pm_init);
int __init omap2_common_pm_late_init(void)
{
return omap2_init_pmu(oh_num, oh_names);
}
-subsys_initcall(omap_init_pmu);
+omap_subsys_initcall(omap_init_pmu);
return ret;
}
-subsys_initcall(omap3xxx_prm_late_init);
+omap_subsys_initcall(omap3xxx_prm_late_init);
static void __exit omap3xxx_prm_exit(void)
{
return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
}
-subsys_initcall(omap44xx_prm_late_init);
+omap_subsys_initcall(omap44xx_prm_late_init);
static void __exit omap44xx_prm_exit(void)
{
return 0;
}
-core_initcall(omap_serial_early_init);
+omap_core_initcall(omap_serial_early_init);
/**
* omap_serial_init_port() - initialize single serial port
*/
#include <linux/power/smartreflex.h>
+#include "soc.h"
#include "voltage.h"
static int sr_class3_enable(struct omap_sr *sr)
pr_info("SmartReflex Class3 initialized\n");
return sr_register_class(&class3_data);
}
-late_initcall(sr_class3_init);
+omap_late_initcall(sr_class3_init);
#undef MULTI_OMAP2
#undef OMAP_NAME
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+#define MULTI_OMAP2
+#endif
#ifdef CONFIG_SOC_OMAP2420
# ifdef OMAP_NAME
# undef MULTI_OMAP2
*/
unsigned int omap_rev(void);
+static inline int soc_is_omap(void)
+{
+ return omap_rev() != 0;
+}
+
/*
* Get the CPU revision for OMAP devices
*/
OMAP4_HAS_FEATURE(perf_silicon, PERF_SILICON)
+/*
+ * We need to make sure omap initcalls don't run when
+ * multiplatform kernels are booted on other SoCs.
+ */
+#define omap_initcall(level, fn) \
+static int __init __used __##fn(void) \
+{ \
+ if (!soc_is_omap()) \
+ return 0; \
+ return fn(); \
+} \
+level(__##fn);
+
+#define omap_early_initcall(fn) omap_initcall(early_initcall, fn)
+#define omap_core_initcall(fn) omap_initcall(core_initcall, fn)
+#define omap_postcore_initcall(fn) omap_initcall(postcore_initcall, fn)
+#define omap_arch_initcall(fn) omap_initcall(arch_initcall, fn)
+#define omap_subsys_initcall(fn) omap_initcall(subsys_initcall, fn)
+#define omap_device_initcall(fn) omap_initcall(device_initcall, fn)
+#define omap_late_initcall(fn) omap_initcall(late_initcall, fn)
+
#endif /* __ASSEMBLY__ */
return 0;
}
-arch_initcall(omap2_dm_timer_init);
+omap_arch_initcall(omap2_dm_timer_init);
/**
* omap2_override_clocksource - clocksource override with user configuration
dev_name, oh->name);
return 0;
}
-subsys_initcall(omap_init_wdt);
+omap_subsys_initcall(omap_init_wdt);
config ARCH_VT8500
- bool "VIA/WonderMedia 85xx" if ARCH_MULTI_V5
- default ARCH_VT8500_SINGLE
+ bool
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_OF
- select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select VT8500_TIMER
help
Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
+
+config ARCH_WM8505
+ bool "VIA/Wondermedia 85xx and WM8650"
+ depends on ARCH_MULTI_V5
+ select ARCH_VT8500
+ select CPU_ARM926T
+ help
+++ /dev/null
-/*
- * arch/arm/mach-vt8500/include/mach/debug-macro.S
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * Debugging macro include header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
- .macro addruart, rp, rv, tmp
- mov \rp, #0x00200000
- orr \rv, \rp, #0xf8000000
- orr \rp, \rp, #0xd8000000
- .endm
-
- .macro senduart,rd,rx
- strb \rd, [\rx, #0]
- .endm
-
- .macro busyuart,rd,rx
-1001: ldr \rd, [\rx, #0x1c]
- ands \rd, \rd, #0x2
- bne 1001b
- .endm
-
- .macro waituart,rd,rx
- .endm
+++ /dev/null
-/*
- * arch/arm/mach-vt8500/include/mach/timex.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef MACH_TIMEX_H
-#define MACH_TIMEX_H
-
-#define CLOCK_TICK_RATE (3000000)
-
-#endif /* MACH_TIMEX_H */
+++ /dev/null
-/* arch/arm/mach-vt8500/include/mach/uncompress.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * Based on arch/arm/mach-dove/include/mach/uncompress.h
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#define UART0_PHYS 0xd8200000
-#define UART0_ADDR(x) *(volatile unsigned char *)(UART0_PHYS + x)
-
-static void putc(const char c)
-{
- while (UART0_ADDR(0x1c) & 0x2)
- /* Tx busy, wait and poll */;
-
- UART0_ADDR(0) = c;
-}
-
-static void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
config ARCH_OMAP_OTG
bool
-choice
- prompt "OMAP System Type"
- default ARCH_OMAP2PLUS
-
-config ARCH_OMAP1
- bool "TI OMAP1"
- select CLKDEV_LOOKUP
- select CLKSRC_MMIO
- select GENERIC_IRQ_CHIP
- select HAVE_IDE
- select IRQ_DOMAIN
- select NEED_MACH_IO_H if PCCARD
- select NEED_MACH_MEMORY_H
- help
- "Systems based on omap7xx, omap15xx or omap16xx"
-
-config ARCH_OMAP2PLUS
- bool "TI OMAP2/3/4"
- select CLKDEV_LOOKUP
- select GENERIC_IRQ_CHIP
- select OMAP_DM_TIMER
- select PINCTRL
- select PROC_DEVICETREE if PROC_FS
- select SPARSE_IRQ
- select USE_OF
- help
- "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
-
-endchoice
-
comment "OMAP Feature Selections"
config OMAP_DEBUG_DEVICES
config OMAP_MBOX_FWK
tristate "Mailbox framework support"
- depends on ARCH_OMAP
+ depends on ARCH_OMAP && !ARCH_MULTIPLATFORM
help
Say Y here if you want to use OMAP Mailbox framework support for
DSP, IVA1.0 and IVA2 in OMAP1/2/3.
# Makefile for the linux kernel.
#
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-omap/include
+
# Common support
obj-y := sram.o dma.o counter_32k.o
obj-m :=
* Register busses defined in command line but that are not registered with
* omap_register_i2c_bus from board initialization code.
*/
-static int __init omap_register_i2c_bus_cmdline(void)
+int __init omap_register_i2c_bus_cmdline(void)
{
int i, err = 0;
out:
return err;
}
-subsys_initcall(omap_register_i2c_bus_cmdline);
/**
* omap_register_i2c_bus - register I2C bus with device descriptors
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len);
+extern int omap_register_i2c_bus_cmdline(void);
#else
static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
{
return 0;
}
+
+static inline int omap_register_i2c_bus_cmdline(void)
+{
+ return 0;
+}
#endif
struct omap_hwmod;
#include <crypto/internal/hash.h>
#include <linux/omap-dma.h>
+
+#ifdef CONFIG_ARCH_OMAP1
#include <mach/irqs.h>
+#endif
#define SHA_REG_DIGEST(x) (0x00 + ((x) * 0x04))
#define SHA_REG_DIN(x) (0x1C + ((x) * 0x04))
}
EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
-static struct platform_device *pdev;
-
-static const struct platform_device_info omap_dma_dev_info = {
- .name = "omap-dma-engine",
- .id = -1,
- .dma_mask = DMA_BIT_MASK(32),
-};
-
static int omap_dma_init(void)
{
- int rc = platform_driver_register(&omap_dma_driver);
-
- if (rc == 0) {
- pdev = platform_device_register_full(&omap_dma_dev_info);
- if (IS_ERR(pdev)) {
- platform_driver_unregister(&omap_dma_driver);
- rc = PTR_ERR(pdev);
- }
- }
- return rc;
+ return platform_driver_register(&omap_dma_driver);
}
subsys_initcall(omap_dma_init);
static void __exit omap_dma_exit(void)
{
- platform_device_unregister(pdev);
platform_driver_unregister(&omap_dma_driver);
}
module_exit(omap_dma_exit);
#include <linux/spinlock.h>
#include <linux/compiler.h>
#include <linux/io.h>
-#include <mach/hardware.h>
#include <media/davinci/vpss.h>
MODULE_LICENSE("GPL");
config IR_RX51
tristate "Nokia N900 IR transmitter diode"
- depends on OMAP_DM_TIMER && LIRC
+ depends on OMAP_DM_TIMER && LIRC && !ARCH_MULTIPLATFORM
---help---
Say Y or M here if you want to enable support for the IR
transmitter diode built in the Nokia N900 (RX51) device.
spin_unlock_irqrestore(&ctlr->lock, flags);
return 0;
}
+EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl);
void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value)
{
dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value);
}
+EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi);
struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
cpdma_handler_fn handler)
spin_unlock_irqrestore(&ctlr->lock, flags);
return ret;
}
+EXPORT_SYMBOL_GPL(cpdma_control_set);
depends on HAS_DMA
depends on ARCH_OMAP4
depends on OMAP_IOMMU
+ depends on OMAP_MBOX_FWK
select REMOTEPROC
- select OMAP_MBOX_FWK
select RPMSG
help
Say y here to support OMAP's remote processors (dual M3
menuconfig TIDSPBRIDGE
tristate "DSP Bridge driver"
- depends on ARCH_OMAP3
+ depends on ARCH_OMAP3 && !ARCH_MULTIPLATFORM
select OMAP_MBOX_FWK
help
DSP/BIOS Bridge is designed for platforms that contain a GPP and
projects / firefly-linux-kernel-4.4.55.git / commitdiff