Fix the opcodes used by X86FastISel for shifts and conditional moves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55855 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 44fd9eaff1253d89ccc9027b3ee7aa6b7c8daca1..a9003e83691f26d73da7beb9fe1a032b8d5339f5 100644 (file)
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -468,36 +468,36 @@ bool X86FastISel::X86SelectShift(Instruction *I) {
     CReg = X86::CL;
     RC = &X86::GR8RegClass;
     switch (I->getOpcode()) {
-    case Instruction::LShr: Opc = X86::SHL8rCL; break;
+    case Instruction::LShr: Opc = X86::SHR8rCL; break;
     case Instruction::AShr: Opc = X86::SAR8rCL; break;
-    case Instruction::Shl:  Opc = X86::SHR8rCL; break;
+    case Instruction::Shl:  Opc = X86::SHL8rCL; break;
     default: return false;
     }
   } else if (I->getType() == Type::Int16Ty) {
     CReg = X86::CX;
     RC = &X86::GR16RegClass;
     switch (I->getOpcode()) {
-    case Instruction::LShr: Opc = X86::SHL16rCL; break;
+    case Instruction::LShr: Opc = X86::SHR16rCL; break;
     case Instruction::AShr: Opc = X86::SAR16rCL; break;
-    case Instruction::Shl:  Opc = X86::SHR16rCL; break;
+    case Instruction::Shl:  Opc = X86::SHL16rCL; break;
     default: return false;
     }
   } else if (I->getType() == Type::Int32Ty) {
     CReg = X86::ECX;
     RC = &X86::GR32RegClass;
     switch (I->getOpcode()) {
-    case Instruction::LShr: Opc = X86::SHL32rCL; break;
+    case Instruction::LShr: Opc = X86::SHR32rCL; break;
     case Instruction::AShr: Opc = X86::SAR32rCL; break;
-    case Instruction::Shl:  Opc = X86::SHR32rCL; break;
+    case Instruction::Shl:  Opc = X86::SHL32rCL; break;
     default: return false;
     }
   } else if (I->getType() == Type::Int64Ty) {
     CReg = X86::RCX;
     RC = &X86::GR64RegClass;
     switch (I->getOpcode()) {
-    case Instruction::LShr: Opc = X86::SHL64rCL; break;
+    case Instruction::LShr: Opc = X86::SHR64rCL; break;
     case Instruction::AShr: Opc = X86::SAR64rCL; break;
-    case Instruction::Shl:  Opc = X86::SHR64rCL; break;
+    case Instruction::Shl:  Opc = X86::SHL64rCL; break;
     default: return false;
     }
   } else {
@@ -523,13 +523,13 @@ bool X86FastISel::X86SelectSelect(Instruction *I) {
   unsigned Opc = 0;
   const TargetRegisterClass *RC = NULL;
   if (Ty == Type::Int16Ty) {
-    Opc = X86::CMOVNE16rr;
+    Opc = X86::CMOVE16rr;
     RC = &X86::GR16RegClass;
   } else if (Ty == Type::Int32Ty) {
-    Opc = X86::CMOVNE32rr;
+    Opc = X86::CMOVE32rr;
     RC = &X86::GR32RegClass;
   } else if (Ty == Type::Int64Ty) {
-    Opc = X86::CMOVNE64rr;
+    Opc = X86::CMOVE64rr;
     RC = &X86::GR64RegClass;
   } else {
     return false;