PowerPC instruction definitions use LittleEndian-style encoding [0..31]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16977 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC32.td b/lib/Target/PowerPC/PPC32.td
index bd6afd9dc876d009d61f54ed48e1c7f2aad905af..fb115f43129557a2f4ef33d566d1b4ceb8d50ef9 100644 (file)
--- a/lib/Target/PowerPC/PPC32.td
+++ b/lib/Target/PowerPC/PPC32.td
@@ -27,6 +27,8 @@ def PowerPCInstrInfo : InstrInfo {
   let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", 
                        "Arg3Type", "Arg4Type", "VMX", "PPC64"];
   let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
+
+  let isLittleEndianEncoding = 1;
 }
 
 def PPC32 : Target {

diff --git a/lib/Target/PowerPC/PPC64.td b/lib/Target/PowerPC/PPC64.td
index 264a261f368fde157d8f025c311d731cba6d0467..06067ed1f41b296ca140f487943b4d10bf977dd9 100644 (file)
--- a/lib/Target/PowerPC/PPC64.td
+++ b/lib/Target/PowerPC/PPC64.td
@@ -27,6 +27,8 @@ def PowerPCInstrInfo : InstrInfo {
   let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", 
                        "Arg3Type", "Arg4Type", "VMX", "PPC64"];
   let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
+
+  let isLittleEndianEncoding = 1;
 }
 
 def PPC64 : Target {

diff --git a/lib/Target/PowerPC/PowerPC.td b/lib/Target/PowerPC/PowerPC.td
index f556aeeae77b418bca64524f62cb23ebe4897084..b7d5bf116f888e8831b30b99bf0f70ac88a6651f 100644 (file)
--- a/lib/Target/PowerPC/PowerPC.td
+++ b/lib/Target/PowerPC/PowerPC.td
@@ -27,6 +27,8 @@ def PowerPCInstrInfo : InstrInfo {
   let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", 
                        "Arg3Type", "Arg4Type", "VMX", "PPC64"];
   let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
+
+  let isLittleEndianEncoding = 1;
 }
 
 def PowerPC : Target {