#define SPI_GPIO_TEST 0\r
#define HIGH_SPI_TEST 1\r
\r
-spinlock_t gpio_lock;\r
-spinlock_t gpio_state_lock;\r
-spinlock_t gpio_irq_lock;\r
+static DEFINE_SPINLOCK(gpio_state_lock);\r
+//static DEFINE_SPINLOCK(gpio_irq_lock);\r
static unsigned short int gGpio0State = 0; \r
#define SPI_GPIO_IRQ_NUM 16\r
static SPI_GPIO_PDATA g_spiGpioVectorTable[SPI_GPIO_IRQ_NUM] = \\r
int spi_free_gpio_irq(eSpiGpioPinNum_t PinNum)\r
{ \r
spi_gpio_disable_int(PinNum);\r
- spin_lock(&gpio_irq_lock);\r
+// spin_lock(&gpio_irq_lock);\r
g_spiGpioVectorTable[PinNum].gpio_vector = NULL;\r
g_spiGpioVectorTable[PinNum].gpio_devid= NULL;\r
- spin_unlock(&gpio_irq_lock);\r
+// spin_unlock(&gpio_irq_lock);\r
\r
return 0;\r
}\r
}\r
\r
\r
-volatile int TestGpioPinLevel = 0;\r
+static volatile int TestGpioPinLevel = 0;\r
void spi_gpio_work_handler(struct work_struct *work)\r
{\r
//struct spi_fpga_port *port =\r
\r
}\r
\r
-void spi_gpio_irq_work_handler(struct work_struct *work);\r
+static void spi_gpio_irq_work_handler(struct work_struct *work);\r
\r
int spi_gpio_register(struct spi_fpga_port *port)\r
{\r
\r
#endif \r
\r
- spin_lock_init(&gpio_lock);\r
- spin_lock_init(&gpio_state_lock);\r
- spin_lock_init(&gpio_irq_lock);\r
-\r
+ INIT_LIST_HEAD(&port->gpio.msg_queue);\r
port->gpio.spi_gpio_irq_workqueue = create_freezeable_workqueue("spi_gpio_irq_workqueue");\r
if (!port->gpio.spi_gpio_irq_workqueue) {\r
printk("cannot create spi_gpio_irq workqueue\n");\r
return -EBUSY;\r
}\r
INIT_WORK(&port->gpio.spi_gpio_irq_work, spi_gpio_irq_work_handler);\r
- INIT_LIST_HEAD(&port->gpio.msg_queue);\r
\r
DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
return 0;\r
return 0;\r
}\r
\r
-void spi_gpio_irq_work_handler(struct work_struct *work)\r
+static void spi_gpio_irq_work_handler(struct work_struct *work)\r
{\r
- unsigned int irq;\r
- unsigned int type;\r
- unsigned int state;\r
- unsigned int id;\r
struct spi_fpga_port *port =\r
container_of(work, struct spi_fpga_port, gpio.spi_gpio_irq_work);\r
\r
- while (!list_empty(&port->gpio.msg_queue)) \r
- {\r
- struct spi_gpio_irq_transfer *t = NULL;\r
- list_for_each_entry(t, &port->gpio.msg_queue, queue)\r
- {\r
- irq = t->irq;\r
- type = t->type;\r
- state = t->state;\r
- id = t->id;\r
- if ((irq == 0) || (id == 0)) \r
- break; \r
- printk("%s:irq=%d,type=%d,state=%d,id=%d\n",__FUNCTION__,irq,type,state,id);\r
- switch(id)\r
- {\r
- case ID_SPI_GPIO_IRQ_ENABLE:\r
- _spi_gpio_irq_enable(irq);\r
- break;\r
- case ID_SPI_GPIO_IRQ_DISABLE:\r
- _spi_gpio_irq_disable(irq);\r
- break;\r
- case ID_SPI_GPIO_IRQ_SET_TYPE:\r
- _spi_gpio_irq_set_type(irq,type);\r
- break;\r
- case ID_SPI_GPIO_IRQ_SET_WAKE:\r
- _spi_gpio_irq_set_wake(irq,state);\r
- break;\r
- default:\r
- break;\r
- \r
- }\r
- kfree(t);\r
+ while (1) {\r
+ struct spi_gpio_irq_transfer *t = NULL;\r
+ unsigned long flags;\r
+ unsigned int irq;\r
+ unsigned int type;\r
+ unsigned int state;\r
+ unsigned int id;\r
+\r
+ spin_lock_irqsave(&port->work_lock, flags);\r
+ if (!list_empty(&port->gpio.msg_queue)) {\r
+ t = list_first_entry(&port->gpio.msg_queue, struct spi_gpio_irq_transfer, queue);\r
+ list_del(&t->queue);\r
+ }\r
+ spin_unlock_irqrestore(&port->work_lock, flags);\r
+\r
+ if (!t) // msg_queue empty\r
+ break;\r
+\r
+ irq = t->irq;\r
+ type = t->type;\r
+ state = t->state;\r
+ id = t->id;\r
+ kfree(t);\r
+\r
+ if ((irq == 0) || (id == 0))\r
+ continue;\r
+ printk("%s:irq=%d,type=%d,state=%d,id=%d\n",__FUNCTION__,irq,type,state,id);\r
+ switch (id) {\r
+ case ID_SPI_GPIO_IRQ_ENABLE:\r
+ _spi_gpio_irq_enable(irq);\r
+ break;\r
+ case ID_SPI_GPIO_IRQ_DISABLE:\r
+ _spi_gpio_irq_disable(irq);\r
+ break;\r
+ case ID_SPI_GPIO_IRQ_SET_TYPE:\r
+ _spi_gpio_irq_set_type(irq, type);\r
+ break;\r
+ case ID_SPI_GPIO_IRQ_SET_WAKE:\r
+ _spi_gpio_irq_set_wake(irq, state);\r
+ break;\r
+ default:\r
+ break;\r
}\r
- list_del_init(&port->gpio.msg_queue);\r
}\r
}\r
\r
struct spi_fpga_port *port = pFpgaPort;\r
struct spi_gpio_irq_transfer *t;\r
unsigned long flags;\r
- t = kzalloc(sizeof(struct spi_gpio_irq_transfer), GFP_KERNEL);\r
+ t = kzalloc(sizeof(struct spi_gpio_irq_transfer), GFP_ATOMIC);\r
if (!t)\r
{\r
printk("err:%s:ENOMEM\n",__FUNCTION__);\r
\r
spin_lock_irqsave(&port->work_lock, flags);\r
list_add_tail(&t->queue, &port->gpio.msg_queue);\r
- queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
spin_unlock_irqrestore(&port->work_lock, flags);\r
+\r
+ queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
}\r
\r
static void spi_gpio_irq_disable(unsigned irq)\r
struct spi_fpga_port *port = pFpgaPort;\r
struct spi_gpio_irq_transfer *t;\r
unsigned long flags;\r
- t = kzalloc(sizeof(struct spi_gpio_irq_transfer), GFP_KERNEL);\r
+ t = kzalloc(sizeof(struct spi_gpio_irq_transfer), GFP_ATOMIC);\r
if (!t)\r
{\r
printk("err:%s:ENOMEM\n",__FUNCTION__);\r
\r
spin_lock_irqsave(&port->work_lock, flags);\r
list_add_tail(&t->queue, &port->gpio.msg_queue);\r
- queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
spin_unlock_irqrestore(&port->work_lock, flags);\r
\r
-\r
+ queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
}\r
\r
static void spi_gpio_irq_mask(unsigned int irq)\r
\r
spin_lock_irqsave(&port->work_lock, flags);\r
list_add_tail(&t->queue, &port->gpio.msg_queue);\r
- queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
spin_unlock_irqrestore(&port->work_lock, flags);\r
+\r
+ queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
+\r
return 0;\r
}\r
\r
\r
spin_lock_irqsave(&port->work_lock, flags);\r
list_add_tail(&t->queue, &port->gpio.msg_queue);\r
- queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
spin_unlock_irqrestore(&port->work_lock, flags);\r
+\r
+ queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work);\r
+\r
return 0;\r
}\r
\r
\r
}\r
\r
-int spi_gpio_banks;\r
+static int spi_gpio_banks;\r
static struct lock_class_key gpio_lock_class;\r
\r
/*\r