Add test for pinsrd and pinsrb instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76840 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/vec_insert-4.ll b/test/CodeGen/X86/vec_insert-4.ll
new file mode 100644 (file)
index 0000000..29c3040
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert-4.ll
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pinsrd | count 1
+; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pinsrb | count 1
+
+define <4 x i32> @t1(i32 %s, <4 x i32> %tmp) nounwind {
+        %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
+        ret <4 x i32> %tmp1
+}
+
+define <16 x i8> @t2(i8 %s, <16 x i8> %tmp) nounwind {
+        %tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
+        ret <16 x i8> %tmp1
+}