correct the (currently unused) pattern for lwzu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31535 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index e072e7e024e41749fda8f6b31a9e29ee95e226dc..cfe103de87851ac960bb61eb7dbd11930747b75f 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -197,6 +197,9 @@ class isDOT   {
   bit RC  = 1;
 }
 
+class RegConstraint<string C> {
+  string Constraints = C;
+}
 
 
 //===----------------------------------------------------------------------===//
@@ -418,10 +421,13 @@ def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
                   "lwz $rD, $src", LdStGeneral,
                   [(set GPRC:$rD, (load iaddr:$src))]>;
-def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
+
+def LWZU : DForm_1<33, (ops GPRC:$rD, GPRC:$rA_result, i32imm:$disp, GPRC:$rA),
                    "lwzu $rD, $disp($rA)", LdStGeneral,
-                   []>;
+                   []>, RegConstraint<"$rA = $rA_result">;
 }
+
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 def ADDI   : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
                      "addi $rD, $rA, $imm", IntGeneral,