Add dummy 'm' inline asm constraint handler for Sparc. I'm not sure, whether it is...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57345 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 691f283b154b6592599d6b1697b2038b28acb4e7..66e143de3fed54f3ee2d1419fc1663a617989a51 100644 (file)
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -45,6 +45,12 @@ public:
   bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
                     SDValue &Offset);
 
+  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+  /// inline asm expressions.
+  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                            char ConstraintCode,
+                                            std::vector<SDValue> &OutOps);
+
   /// InstructionSelect - This callback is invoked by
   /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
   virtual void InstructionSelect();
@@ -184,6 +190,26 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
 }
 
 
+/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+/// inline asm expressions.
+bool
+SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                                char ConstraintCode,
+                                                std::vector<SDValue> &OutOps) {
+  SDValue Op0, Op1;
+  switch (ConstraintCode) {
+  default: return true;
+  case 'm':   // memory
+   if (!SelectADDRrr(Op, Op, Op0, Op1))
+     SelectADDRri(Op, Op, Op0, Op1);
+   break;
+  }
+
+  OutOps.push_back(Op0);
+  OutOps.push_back(Op1);
+  return false;
+}
+
 /// createSparcISelDag - This pass converts a legalized DAG into a
 /// SPARC-specific DAG, ready for instruction scheduling.
 ///