Add support for avx vector fextend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137105 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 986e428b9eebf9c1cd3218f2a9b379f230f2cbbb..79d455a326c4c30cc39cf0a72211e696612cefd0 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -1093,12 +1093,17 @@ def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
           (VCVTTPS2DQYrm addr:$src)>;
 
-// Match fround for 128/256-bit conversions
+// Match fround and fextend for 128/256-bit conversions
 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
           (VCVTPD2PSYrr VR256:$src)>;
 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
           (VCVTPD2PSYrm addr:$src)>;
 
+def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
+          (VCVTPS2PDYrr VR128:$src)>;
+def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
+          (VCVTPS2PDYrm addr:$src)>;
+
 //===----------------------------------------------------------------------===//
 // SSE 1 & 2 - Compare Instructions
 //===----------------------------------------------------------------------===//

diff --git a/test/CodeGen/X86/avx-cvt.ll b/test/CodeGen/X86/avx-cvt.ll
index 6da47af5ab517bf7e2550be2ad15f415c8c12823..e45010c903edab99e887ea7a12342b038fabe6ca 100644 (file)
--- a/test/CodeGen/X86/avx-cvt.ll
+++ b/test/CodeGen/X86/avx-cvt.ll
@@ -20,6 +20,12 @@ define <8 x float> @fptrunc00(<8 x double> %b) nounwind {
   ret <8 x float> %a
 }
 
+; CHECK: vcvtps2pd %xmm
+define <4 x double> @fpext00(<4 x float> %b) nounwind {
+  %a = fpext <4 x float> %b to <4 x double>
+  ret <4 x double> %a
+}
+
 ; CHECK: vcvtsi2sdq (%
 define double @funcA(i64* nocapture %e) nounwind uwtable readonly ssp {
 entry: