R600/SI: Fix hardcoded and wrong operand numbers.
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 24 Sep 2014 02:17:09 +0000 (02:17 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 24 Sep 2014 02:17:09 +0000 (02:17 +0000)
Also fix leftover debug printing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218359 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/R600/SIInstrInfo.cpp

index e53db58123ba22325a164a9c6841d9537a73751e..41e6d37e01430cfdc98bcd8c1a8185ce68cfc0cc 100644 (file)
@@ -1069,11 +1069,9 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
   // Verify misc. restrictions on specific instructions.
   if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
       Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
-    MI->dump();
-
-    const MachineOperand &Src0 = MI->getOperand(2);
-    const MachineOperand &Src1 = MI->getOperand(3);
-    const MachineOperand &Src2 = MI->getOperand(4);
+    const MachineOperand &Src0 = MI->getOperand(Src0Idx);
+    const MachineOperand &Src1 = MI->getOperand(Src1Idx);
+    const MachineOperand &Src2 = MI->getOperand(Src2Idx);
     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
       if (!compareMachineOp(Src0, Src1) &&
           !compareMachineOp(Src0, Src2)) {