MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register
authorChandrakala Chavva <cchavva@caviumnetworks.com>
Thu, 15 Jan 2015 13:11:08 +0000 (16:11 +0300)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 20 Feb 2015 14:29:36 +0000 (15:29 +0100)
Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register,
its a 64-bit wide.

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8936/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/octeon_switch.S

index 590ca2d56b6a65b887cb3949b427e4b23cf3e999..f0a699d73627768e01a8cb551a01f867a0049cbe 100644 (file)
@@ -80,7 +80,7 @@
 1:
 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
        /* Check if we need to store CVMSEG state */
-       mfc0    t0, $11,7       /* CvmMemCtl */
+       dmfc0   t0, $11,7       /* CvmMemCtl */
        bbit0   t0, 6, 3f       /* Is user access enabled? */
 
        /* Store the CVMSEG state */
        .set reorder
 
        /* Disable access to CVMSEG */
-       mfc0    t0, $11,7       /* CvmMemCtl */
+       dmfc0   t0, $11,7       /* CvmMemCtl */
        xori    t0, t0, 0x40    /* Bit 6 is CVMSEG user enable */
-       mtc0    t0, $11,7       /* CvmMemCtl */
+       dmtc0   t0, $11,7       /* CvmMemCtl */
 #endif
 3: