Teach FastISel to support register-immediate-immediate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127496 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index fbb12005444f3a6e191aa9689fdc5b911aec9976..6b237f8460c71d7f105e205f611e11698ef1f711 100644 (file)
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -8,9 +8,9 @@
 //===----------------------------------------------------------------------===//
 //
 // This file defines the FastISel class.
-//  
+//
 //===----------------------------------------------------------------------===//
-  
+
 #ifndef LLVM_CODEGEN_FASTISEL_H
 #define LLVM_CODEGEN_FASTISEL_H
 
@@ -108,7 +108,7 @@ public:
                              const LoadInst * /*LI*/) {
     return false;
   }
-  
+
   /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions
   /// into the current block.
   void recomputeInsertPt();
@@ -203,7 +203,7 @@ protected:
                         unsigned Opcode,
                         unsigned Op0, bool Op0IsKill,
                         uint64_t Imm, MVT ImmType);
-  
+
   /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
   /// to emit an instruction with an immediate operand using FastEmit_rf.
   /// If that fails, it materializes the immediate into a register and try
@@ -212,7 +212,7 @@ protected:
                         unsigned Opcode,
                         unsigned Op0, bool Op0IsKill,
                         const ConstantFP *FPImm, MVT ImmType);
-  
+
   /// FastEmit_i - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
   /// immediate operand be emitted.
@@ -258,6 +258,14 @@ protected:
                            unsigned Op0, bool Op0IsKill,
                            uint64_t Imm);
 
+  /// FastEmitInst_rii - Emit a MachineInstr with one register operand
+  /// and two immediate operands.
+  ///
+  unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
+                           const TargetRegisterClass *RC,
+                           unsigned Op0, bool Op0IsKill,
+                           uint64_t Imm1, uint64_t Imm2);
+
   /// FastEmitInst_rf - Emit a MachineInstr with two register operands
   /// and a result register in the given register class.
   ///
@@ -274,7 +282,7 @@ protected:
                             unsigned Op0, bool Op0IsKill,
                             unsigned Op1, bool Op1IsKill,
                             uint64_t Imm);
-  
+
   /// FastEmitInst_i - Emit a MachineInstr with a single immediate
   /// operand, and a result register in the given register class.
   unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
@@ -300,8 +308,8 @@ protected:
   unsigned UpdateValueMap(const Value* I, unsigned Reg);
 
   unsigned createResultReg(const TargetRegisterClass *RC);
-  
-  /// TargetMaterializeConstant - Emit a constant in a register using 
+
+  /// TargetMaterializeConstant - Emit a constant in a register using
   /// target-specific logic, such as constant pool loads.
   virtual unsigned TargetMaterializeConstant(const Constant* C) {
     return 0;
@@ -323,7 +331,7 @@ private:
   bool SelectCall(const User *I);
 
   bool SelectBitCast(const User *I);
-  
+
   bool SelectCast(const User *I, unsigned Opcode);
 
   /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 490b857b0e9c80c0c4559b76f20cb13f8f58b4f8..ea8ace38bd3e51e3e4cb24f0688928493651f55f 100644 (file)
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1099,6 +1099,29 @@ unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
   return ResultReg;
 }
 
+unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode,
+                                   const TargetRegisterClass *RC,
+                                   unsigned Op0, bool Op0IsKill,
+                                   uint64_t Imm1, uint64_t Imm2) {
+  unsigned ResultReg = createResultReg(RC);
+  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
+
+  if (II.getNumDefs() >= 1)
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
+      .addReg(Op0, Op0IsKill * RegState::Kill)
+      .addImm(Imm1)
+      .addImm(Imm2);
+  else {
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
+      .addReg(Op0, Op0IsKill * RegState::Kill)
+      .addImm(Imm1)
+      .addImm(Imm2);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
+            ResultReg).addReg(II.ImplicitDefs[0]);
+  }
+  return ResultReg;
+}
+
 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
                                    const TargetRegisterClass *RC,
                                    unsigned Op0, bool Op0IsKill,