Merge branch 'prcm_scm_misc_fixes_3.2' of git://git.pwsan.com/linux-2.6 into fixes

diff --combined arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3008e1672c7a051e54e84ed2e147ea2674e019e4,ac12cd5fb0737c4e5511c692c8015106efbca709..87a3b01d254c1c01a051a787862d053fb83fe18e
--- 1/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
--- 2/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@@ -564,21 -564,6 +564,21 @@@ static struct omap_hwmod_class omap3xxx
        .rev =  OMAP_TIMER_IP_VERSION_1,
  };
  
 +/* secure timers dev attribute */
 +static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 +      .timer_capability       = OMAP_TIMER_SECURE,
 +};
 +
 +/* always-on timers dev attribute */
 +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 +      .timer_capability       = OMAP_TIMER_ALWON,
 +};
 +
 +/* pwm timers dev attribute */
 +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 +      .timer_capability       = OMAP_TIMER_HAS_PWM,
 +};
 +
  /* timer1 */
  static struct omap_hwmod omap3xxx_timer1_hwmod;
  
@@@ -619,7 -604,6 +619,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
                },
        },
 +      .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer1_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
@@@ -665,7 -649,6 +665,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
                },
        },
 +      .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer2_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
@@@ -711,7 -694,6 +711,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
                },
        },
 +      .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer3_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
@@@ -757,7 -739,6 +757,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
                },
        },
 +      .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer4_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
@@@ -803,7 -784,6 +803,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
                },
        },
 +      .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer5_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
@@@ -849,7 -829,6 +849,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
                },
        },
 +      .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer6_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
@@@ -895,7 -874,6 +895,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
                },
        },
 +      .dev_attr       = &capability_alwon_dev_attr,
        .slaves         = omap3xxx_timer7_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
@@@ -941,7 -919,6 +941,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
                },
        },
 +      .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer8_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
@@@ -987,7 -964,6 +987,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
                },
        },
 +      .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer9_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
@@@ -1024,7 -1000,6 +1024,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
                },
        },
 +      .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer10_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
@@@ -1061,7 -1036,6 +1061,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
                },
        },
 +      .dev_attr       = &capability_pwm_dev_attr,
        .slaves         = omap3xxx_timer11_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
@@@ -1111,7 -1085,6 +1111,7 @@@ static struct omap_hwmod omap3xxx_timer
                        .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
                },
        },
 +      .dev_attr       = &capability_secure_dev_attr,
        .slaves         = omap3xxx_timer12_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
@@@ -2569,7 -2542,7 +2569,7 @@@ static struct omap_hwmod omap34xx_sr1_h
        .name           = "sr1_hwmod",
        .class          = &omap34xx_smartreflex_hwmod_class,
        .main_clk       = "sr1_fck",
 -      .vdd_name       = "mpu",
 +      .vdd_name       = "mpu_iva",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
@@@ -2588,7 -2561,7 +2588,7 @@@ static struct omap_hwmod omap36xx_sr1_h
        .name           = "sr1_hwmod",
        .class          = &omap36xx_smartreflex_hwmod_class,
        .main_clk       = "sr1_fck",
 -      .vdd_name       = "mpu",
 +      .vdd_name       = "mpu_iva",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
@@@ -3159,7 -3132,6 +3159,6 @@@ static __initdata struct omap_hwmod *om
        &omap3xxx_mmc2_hwmod,
        &omap3xxx_mmc3_hwmod,
        &omap3xxx_mpu_hwmod,
-       &omap3xxx_iva_hwmod,
  
        &omap3xxx_timer1_hwmod,
        &omap3xxx_timer2_hwmod,
@@@ -3188,8 -3160,6 +3187,6 @@@
        &omap3xxx_i2c1_hwmod,
        &omap3xxx_i2c2_hwmod,
        &omap3xxx_i2c3_hwmod,
-       &omap34xx_sr1_hwmod,
-       &omap34xx_sr2_hwmod,
  
        /* gpio class */
        &omap3xxx_gpio1_hwmod,
@@@ -3211,8 -3181,6 +3208,6 @@@
        &omap3xxx_mcbsp2_sidetone_hwmod,
        &omap3xxx_mcbsp3_sidetone_hwmod,
  
-       /* mailbox class */
-       &omap3xxx_mailbox_hwmod,
  
        /* mcspi class */
        &omap34xx_mcspi1,
@@@ -3225,31 -3193,39 +3220,39 @@@
  
  /* 3430ES1-only hwmods */
  static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
+       &omap3xxx_iva_hwmod,
        &omap3430es1_dss_core_hwmod,
+       &omap3xxx_mailbox_hwmod,
        NULL
  };
  
  /* 3430ES2+-only hwmods */
  static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
+       &omap3xxx_iva_hwmod,
        &omap3xxx_dss_core_hwmod,
        &omap3xxx_usbhsotg_hwmod,
+       &omap3xxx_mailbox_hwmod,
        NULL
  };
  
  /* 34xx-only hwmods (all ES revisions) */
  static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
+       &omap3xxx_iva_hwmod,
        &omap34xx_sr1_hwmod,
        &omap34xx_sr2_hwmod,
+       &omap3xxx_mailbox_hwmod,
        NULL
  };
  
  /* 36xx-only hwmods (all ES revisions) */
  static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
+       &omap3xxx_iva_hwmod,
        &omap3xxx_uart4_hwmod,
        &omap3xxx_dss_core_hwmod,
        &omap36xx_sr1_hwmod,
        &omap36xx_sr2_hwmod,
        &omap3xxx_usbhsotg_hwmod,
+       &omap3xxx_mailbox_hwmod,
        NULL
  };