(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
[(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
- Requires<[HasV8FP]>;
+ Requires<[HasFPARMv8]>;
def D : ADbInp<0b11100, opc, 0,
(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
[(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
- Requires<[HasV8FP]>;
+ Requires<[HasFPARMv8]>;
}
}
(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
[(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
- Requires<[HasV8FP]>;
+ Requires<[HasFPARMv8]>;
def D : ADbInp<0b11101, 0b00, opc,
(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
[(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
- Requires<[HasV8FP]>;
+ Requires<[HasFPARMv8]>;
}
}
def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
(outs DPR:$Dd), (ins SPR:$Sm),
NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
// Instruction operands.
bits<5> Sm;
def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
(outs SPR:$Sd), (ins DPR:$Dm),
NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
// Instruction operands.
bits<5> Sd;
bits<5> Dm;
def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
(outs DPR:$Dd), (ins SPR:$Sm),
NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
// Instruction operands.
bits<5> Sm;
def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
(outs SPR:$Sd), (ins DPR:$Dm),
NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
// Instruction operands.
bits<5> Sd;
bits<5> Dm;
def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
let Inst{17-16} = rm;
}
def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
let Inst{17-16} = rm;
}
def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
(outs SPR:$Sd), (ins DPR:$Dm),
NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
bits<5> Dm;
let Inst{17-16} = rm;
def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
(outs SPR:$Sd), (ins DPR:$Dm),
NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
bits<5> Dm;
let Inst{17-16} = rm;
def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
let Inst{7} = op2;
let Inst{16} = op;
}
def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
(outs DPR:$Dd), (ins DPR:$Dm),
NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
let Inst{7} = op2;
let Inst{16} = op;
}
def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
let Inst{17-16} = rm;
}
def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
(outs DPR:$Dd), (ins DPR:$Dm),
NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
- []>, Requires<[HasV8FP]> {
+ []>, Requires<[HasFPARMv8]> {
let Inst{17-16} = rm;
}
}
; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7
; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8
; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8
-; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+v8fp | FileCheck %s --check-prefix=V8-V8FP
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8 | FileCheck %s --check-prefix=V8-FPARMv8
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+neon | FileCheck %s --check-prefix=V8-NEON
-; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+v8fp -mattr=+neon | FileCheck %s --check-prefix=V8-V8FP-NEON
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8 -mattr=+neon | FileCheck %s --check-prefix=V8-FPARMv8-NEON
; This tests that MC/asm header conversion is smooth
;
; V7: .syntax unified
; Vt8: .syntax unified
; Vt8: .eabi_attribute 6, 14
-; V8-V8FP: .syntax unified
-; V8-V8FP: .eabi_attribute 6, 14
-; V8-V8FP: .eabi_attribute 10, 7
-; V8-V8FP: .fpu fp-armv8
+; V8-FPARMv8: .syntax unified
+; V8-FPARMv8: .eabi_attribute 6, 14
+; V8-FPARMv8: .eabi_attribute 10, 7
+; V8-FPARMv8: .fpu fp-armv8
; V8-NEON: .syntax unified
; V8-NEON: .eabi_attribute 6, 14
; V8-NEON: .eabi_attribute 12, 3
-; V8-V8FP-NEON: .syntax unified
-; V8-V8FP-NEON: .eabi_attribute 6, 14
-; V8-V8FP-NEON: .fpu neon-fp-armv8
-; V8-V8FP-NEON: .eabi_attribute 10, 7
+; V8-FPARMv8-NEON: .syntax unified
+; V8-FPARMv8-NEON: .eabi_attribute 6, 14
+; V8-FPARMv8-NEON: .fpu neon-fp-armv8
+; V8-FPARMv8-NEON: .eabi_attribute 10, 7
define i32 @f(i64 %z) {
ret i32 0
; RUN: llc < %s -mtriple armv8 -mattr=+neon | FileCheck %s
-; RUN: llc < %s -mtriple armv8 -mattr=+neon,+v8fp -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
+; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK: vmaxnmq
ret <2 x float> %tmp3
}
-define float @v8fp_vminnm_o(float %a, float %b) {
-; CHECK-FAST: v8fp_vminnm_o
+define float @fp-armv8_vminnm_o(float %a, float %b) {
+; CHECK-FAST: fp-armv8_vminnm_o
; CHECK-FAST-NOT: vcmp
; CHECK-FAST: vminnm.f32
-; CHECK: v8fp_vminnm_o
+; CHECK: fp-armv8_vminnm_o
; CHECK-NOT: vminnm.f32
%cmp = fcmp olt float %a, %b
%cond = select i1 %cmp, float %a, float %b
ret float %cond
}
-define float @v8fp_vminnm_u(float %a, float %b) {
-; CHECK-FAST: v8fp_vminnm_u
+define float @fp-armv8_vminnm_u(float %a, float %b) {
+; CHECK-FAST: fp-armv8_vminnm_u
; CHECK-FAST-NOT: vcmp
; CHECK-FAST: vminnm.f32
-; CHECK: v8fp_vminnm_u
+; CHECK: fp-armv8_vminnm_u
; CHECK-NOT: vminnm.f32
%cmp = fcmp ult float %a, %b
%cond = select i1 %cmp, float %a, float %b
ret float %cond
}
-define float @v8fp_vmaxnm_o(float %a, float %b) {
-; CHECK-FAST: v8fp_vmaxnm_o
+define float @fp-armv8_vmaxnm_o(float %a, float %b) {
+; CHECK-FAST: fp-armv8_vmaxnm_o
; CHECK-FAST-NOT: vcmp
; CHECK-FAST: vmaxnm.f32
-; CHECK: v8fp_vmaxnm_o
+; CHECK: fp-armv8_vmaxnm_o
; CHECK-NOT: vmaxnm.f32
%cmp = fcmp ogt float %a, %b
%cond = select i1 %cmp, float %a, float %b
ret float %cond
}
-define float @v8fp_vmaxnm_u(float %a, float %b) {
-; CHECK-FAST: v8fp_vmaxnm_u
+define float @fp-armv8_vmaxnm_u(float %a, float %b) {
+; CHECK-FAST: fp-armv8_vmaxnm_u
; CHECK-FAST-NOT: vcmp
; CHECK-FAST: vmaxnm.f32
-; CHECK: v8fp_vmaxnm_u
+; CHECK: fp-armv8_vmaxnm_u
; CHECK-NOT: vmaxnm.f32
%cmp = fcmp ugt float %a, %b
%cond = select i1 %cmp, float %a, float %b