Fix merge problem

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81658 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index d5b1facfd92fde4551aca8018cc2cfb27ed140c2..20a7355b7653020c2815e648301be0b55646eba7 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -347,13 +347,6 @@ def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
   let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
 }
 
-// Subset of QPR that have 32-bit SPR subregs.
-def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
-                             128,
-                             [Q0,  Q1,  Q2,  Q3,  Q4,  Q5,  Q6,  Q7]> {
-  let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR];
-}
-
 // Condition code registers.
 def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;