put reg classes in namespaces

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22922 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index def3d54f01e5967949f29cc058071e493b91c9f6..515247fa30cd4310495c4e45bd1430a49c02ce02 100644 (file)
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -84,7 +84,7 @@ def Y   : Rs<0, "Y">;
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<"V8", i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5,
                                      G1,
                                      O0, O1, O2, O3, O4, O5, O7,
@@ -104,9 +104,9 @@ def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
   }];
 }
 
-def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
+def FPRegs : RegisterClass<"V8", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
   F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
   F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
+def DFPRegs : RegisterClass<"V8", f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
   D8, D9, D10, D11, D12, D13, D14, D15]>;

diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td
index def3d54f01e5967949f29cc058071e493b91c9f6..515247fa30cd4310495c4e45bd1430a49c02ce02 100644 (file)
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -84,7 +84,7 @@ def Y   : Rs<0, "Y">;
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<"V8", i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5,
                                      G1,
                                      O0, O1, O2, O3, O4, O5, O7,
@@ -104,9 +104,9 @@ def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
   }];
 }
 
-def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
+def FPRegs : RegisterClass<"V8", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
   F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
   F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
+def DFPRegs : RegisterClass<"V8", f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
   D8, D9, D10, D11, D12, D13, D14, D15]>;