drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue

Display register 420B0h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a7fc13d28b5c3f7cec37e277bd3244d19b80906d..d48558678e87aa9f8ca6772fd11f2728fa69652b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -980,6 +980,13 @@
 #define IVB_FBC_RT_BASE                        0x7020
 
 
+#define _HSW_PIPE_SLICE_CHICKEN_1_A    0x420B0
+#define _HSW_PIPE_SLICE_CHICKEN_1_B    0x420B4
+#define   HSW_BYPASS_FBC_QUEUE         (1<<22)
+#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
+                                            _HSW_PIPE_SLICE_CHICKEN_1_A, + \
+                                            _HSW_PIPE_SLICE_CHICKEN_1_B)
+
 /*
  * GPIO regs
  */

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 10f788b62fa8e6a5697b158b0ecdb172b4418967..4e678bad46d32054e80fe89b37b6faaec54e3f7e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -281,6 +281,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
                I915_WRITE(ILK_DSPCLK_GATE_D,
                           I915_READ(ILK_DSPCLK_GATE_D) |
                           ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
+       } else {
+               /* WaFbcAsynchFlipDisableFbcQueue */
+               I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
+                          HSW_BYPASS_FBC_QUEUE);
        }
 
        I915_WRITE(SNB_DPFC_CTL_SA,