Register sizes should be specified in bits

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16106 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Skeleton/SkeletonRegisterInfo.td b/lib/Target/Skeleton/SkeletonRegisterInfo.td
index 71c4aa21a4a0e4f4483ba817a8ca67f2151d09ee..b8b1bb20d267b3d7ab9ba6a281f50322db9cf000 100644 (file)
--- a/lib/Target/Skeleton/SkeletonRegisterInfo.td
+++ b/lib/Target/Skeleton/SkeletonRegisterInfo.td
@@ -77,10 +77,10 @@ def TBU : SPR<5>;
 
 /// Register classes: one for floats and another for non-floats.
 ///
-def GPRC : RegisterClass<i32, 4, [R0, R1, R2, R3, R4, R5, R6, R7,
+def GPRC : RegisterClass<i32, 32, [R0, R1, R2, R3, R4, R5, R6, R7,
   R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
   R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
-def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;