bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
const HexagonInstrInfo *TII = QTM.getInstrInfo();
- const HexagonRegisterInfo *RegInfo = QTM.getRegisterInfo();
// Loop over all of the basic blocks.
for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
if (Opc == Hexagon::STriw_pred) {
// STriw_pred [R30], ofst, SrcReg;
unsigned FP = MI->getOperand(0).getReg();
- assert(FP == RegInfo->getFrameRegister() &&
+ assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(1).isImm() && "Not an offset");
int Offset = MI->getOperand(1).getImm();
assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
"Not a predicate register");
unsigned FP = MI->getOperand(1).getReg();
- assert(FP == RegInfo->getFrameRegister() &&
+ assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(2).isImm() && "Not an offset");
int Offset = MI->getOperand(2).getImm();
} else if (VT == MVT::i64) {
TRC = Hexagon::DoubleRegsRegisterClass;
} else {
- assert(0 && "Cannot handle this register class");
+ llvm_unreachable("Cannot handle this register class");
}
unsigned NewReg = RegInfo.createVirtualRegister(TRC);
case Hexagon::JMPR:
return false;
- return true;
-
- default:
- return true;
}
return true;
case Hexagon::DEALLOC_RET_V4:
return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
Hexagon::DEALLOC_RET_cNotPt_V4;
- default:
- assert(false && "Unexpected predicable instruction");
}
+ llvm_unreachable("Unexpected predicable instruction");
}
return true;
}
- assert(0 && "No offset range is defined for this opcode. Please define it in \
- the above switch statement!");
+ llvm_unreachable("No offset range is defined for this opcode. "
+ "Please define it in the above switch statement!");
}
};
switch(Subtarget.getHexagonArchVersion()) {
+ case HexagonSubtarget::V1:
+ break;
case HexagonSubtarget::V2:
return CalleeSavedRegsV2;
- break;
case HexagonSubtarget::V3:
case HexagonSubtarget::V4:
return CalleeSavedRegsV3;
- break;
- default:
- const char *ErrorString =
- "Callee saved registers requested for unknown archtecture version";
- llvm_unreachable(ErrorString);
}
+ llvm_unreachable("Callee saved registers requested for unknown architecture "
+ "version");
}
BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
};
switch(Subtarget.getHexagonArchVersion()) {
+ case HexagonSubtarget::V1:
+ break;
case HexagonSubtarget::V2:
return CalleeSavedRegClassesV2;
- break;
case HexagonSubtarget::V3:
case HexagonSubtarget::V4:
return CalleeSavedRegClassesV3;
- break;
- default:
- const char *ErrorString =
- "Callee saved register classes requested for unknown archtecture version";
- llvm_unreachable(ErrorString);
}
+ llvm_unreachable("Callee saved register classes requested for unknown "
+ "architecture version");
}
void HexagonRegisterInfo::
RegType = PTXRegisterType::F32;
else if (TRC == PTX::RegF64RegisterClass)
RegType = PTXRegisterType::F64;
+ else
+ llvm_unreachable("Unkown register class.");
MFI->addRegister(Reg, RegType, PTXRegisterSpace::Reg);
}