Add or reg-reg pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75914 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index df921f891db8610f8921dd559a2a7e226396a5f5..66b2db972cb744e2d01ff35c6f0b8ec8237fd87d 100644 (file)
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -69,5 +69,13 @@ def ADD64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
                      [(set GR64:$dst, (add GR64:$src1, imm:$src2)),
                       (implicit PSW)]>;
 
+let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
+// FIXME: Provide proper encoding!
+def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
+                    "ogr\t{$dst, $src2}",
+                    [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
+}
+// FIXME: provide patterns for masked or-with-imm
+
 } // Defs = [PSW]
 } // isTwoAddress = 1

diff --git a/test/CodeGen/SystemZ/02-RetOr.ll b/test/CodeGen/SystemZ/02-RetOr.ll
new file mode 100644 (file)
index 0000000..ef9d63a
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetOr.ll
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+    %c = or i64 %a, %b
+    ret i64 %c
+}
\ No newline at end of file

diff --git a/test/CodeGen/SystemZ/02-RetOrImm.ll b/test/CodeGen/SystemZ/02-RetOrImm.ll
new file mode 100644 (file)
index 0000000..b5fdb00
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetOrImm.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+    %c = or i64 %a, 1
+    ret i64 %c
+}
+
+; FIXME: SystemZ has 4 or reg-imm instructions depending on imm,
+; we need to support them someday.
\ No newline at end of file