Aggregation buffer size is set separately per 18xx/12xx chip family.
For 18xx aggragation buffer is set to 13 pages to utilize all
the available tx/rx descriptors for aggregation.
[Arik - remove redundant parts from the patch]
Signed-off-by: Igal Chernobelsky <igalc@ti.com>
Signed-off-by: Arik Nemtsov <arik@wizery.com>
Signed-off-by: Luciano Coelho <luca@coelho.fi>
struct ieee80211_hw *hw;
struct wl12xx_priv *priv;
- hw = wlcore_alloc_hw(sizeof(*priv));
+ hw = wlcore_alloc_hw(sizeof(*priv), WL12XX_AGGR_BUFFER_SIZE);
if (IS_ERR(hw)) {
wl1271_error("can't allocate hw");
return PTR_ERR(hw);
#define WL128X_SUBTYPE_VER 2
#define WL128X_MINOR_VER 115
+#define WL12XX_AGGR_BUFFER_SIZE (4 * PAGE_SIZE)
+
#define WL12XX_NUM_TX_DESCRIPTORS 16
#define WL12XX_NUM_RX_DESCRIPTORS 8
struct wl18xx_priv *priv;
int ret;
- hw = wlcore_alloc_hw(sizeof(*priv));
+ hw = wlcore_alloc_hw(sizeof(*priv), WL18XX_AGGR_BUFFER_SIZE);
if (IS_ERR(hw)) {
wl1271_error("can't allocate hw");
ret = PTR_ERR(hw);
#define WL18XX_CMD_MAX_SIZE 740
+#define WL18XX_AGGR_BUFFER_SIZE (13 * PAGE_SIZE)
+
#define WL18XX_NUM_TX_DESCRIPTORS 32
#define WL18XX_NUM_RX_DESCRIPTORS 32
#define WL1271_DEFAULT_CHANNEL 0
-struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size)
+struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size)
{
struct ieee80211_hw *hw;
struct wl1271 *wl;
mutex_init(&wl->mutex);
mutex_init(&wl->flush_mutex);
- order = get_order(WL1271_AGGR_BUFFER_SIZE);
+ order = get_order(aggr_buf_size);
wl->aggr_buf = (u8 *)__get_free_pages(GFP_KERNEL, order);
if (!wl->aggr_buf) {
ret = -ENOMEM;
goto err_wq;
}
+ wl->aggr_buf_size = aggr_buf_size;
wl->dummy_packet = wl12xx_alloc_dummy_packet(wl);
if (!wl->dummy_packet) {
device_remove_file(wl->dev, &dev_attr_bt_coex_state);
free_page((unsigned long)wl->fwlog);
dev_kfree_skb(wl->dummy_packet);
- free_pages((unsigned long)wl->aggr_buf,
- get_order(WL1271_AGGR_BUFFER_SIZE));
+ free_pages((unsigned long)wl->aggr_buf, get_order(wl->aggr_buf_size));
wl1271_debugfs_exit(wl);
pkt_len = wlcore_rx_get_buf_size(wl, des);
align_pkt_len = wlcore_rx_get_align_buf_size(wl,
pkt_len);
- if (buf_size + align_pkt_len > WL1271_AGGR_BUFFER_SIZE)
+ if (buf_size + align_pkt_len > wl->aggr_buf_size)
break;
buf_size += align_pkt_len;
rx_counter++;
int id, ret = -EBUSY, ac;
u32 spare_blocks;
- if (buf_offset + total_len > WL1271_AGGR_BUFFER_SIZE)
+ if (buf_offset + total_len > wl->aggr_buf_size)
return -EAGAIN;
spare_blocks = wlcore_hw_get_spare_blocks(wl, is_gem);
/* Intermediate buffer, used for packet aggregation */
u8 *aggr_buf;
+ u32 aggr_buf_size;
/* Reusable dummy packet template */
struct sk_buff *dummy_packet;
int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
int __devexit wlcore_remove(struct platform_device *pdev);
-struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
+struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size);
int wlcore_free_hw(struct wl1271 *wl);
int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
struct ieee80211_vif *vif,