Make i64=expand_vector_elt(v2i64) work in 32-bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43535 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 5ec74cdc311fd31e581136287ccdf32173e61f75..9150e96cc027c1253eb02f874482882017a594ec 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -5299,6 +5299,11 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
 #endif
     assert(0 && "Do not know how to expand this operator!");
     abort();
+  case ISD::EXTRACT_VECTOR_ELT:
+    assert(VT==MVT::i64 && "Do not know how to expand this operator!");
+    // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
+    Lo  = ExpandEXTRACT_VECTOR_ELT(Op);
+    return ExpandOp(Lo, Lo, Hi);
   case ISD::UNDEF:
     NVT = TLI.getTypeToExpandTo(VT);
     Lo = DAG.getNode(ISD::UNDEF, NVT);

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index ab24083185503b0c066780a565283da13407ae4b..17c7534377d44ad0b883066b3a46de3bb4ddae2a 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -608,7 +608,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2f64, Custom);
     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2i64, Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
-    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
+    if (Subtarget->is64Bit())
+      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
 
     // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
     for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {