Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-Initiali...

with some changes I have to the new CFE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28022 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e9b30cb38bd745f642281bcca532fe473a80c993..ac70150f8e0c94b35e3f7e9b13dd7ebec100e482 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1899,13 +1899,6 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
   if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
     return DAG.getZeroExtendInReg(N0, EVT);
-  // fold (sext_in_reg (srl x)) -> sra x
-  if (N0.getOpcode() == ISD::SRL && 
-      N0.getOperand(1).getOpcode() == ISD::Constant &&
-      cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
-    return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 
-                       N0.getOperand(1));
-  }
   // fold (sext_inreg (extload x)) -> (sextload x)
   if (N0.getOpcode() == ISD::EXTLOAD && 
       EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&