staging: dwc2: remove use of bus_to_virt()

Remove the use of bus_to_virt() and just fail the transfer if an
unaligned buffer with no virtual address is found. AFAIK that
can't happen anyway.

Also change setting of coherent DMA mask to the normal 32 bits.
31 bits was only needed when calling bus_to_virt() AFAICR.

Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/dwc2/Kconfig b/drivers/staging/dwc2/Kconfig
index d15d9d58e5ac2a3022c92e9843f7de7b64685f1f..be947d673844507b70018db93f3be6cc626d75cb 100644 (file)
--- a/drivers/staging/dwc2/Kconfig
+++ b/drivers/staging/dwc2/Kconfig
@@ -1,7 +1,6 @@
 config USB_DWC2
        tristate "DesignWare USB2 DRD Core Support"
        depends on USB
-       depends on VIRT_TO_BUS
        help
          Say Y or M here if your system has a Dual Role HighSpeed
          USB controller based on the DesignWare HSOTG IP Core.

diff --git a/drivers/staging/dwc2/hcd.c b/drivers/staging/dwc2/hcd.c
index 26392090e2f8d9eb735c0e31f4d4dd2266370151..962468f067161b9fd7e5f47920a6bb68fb3b7e39 100644 (file)
--- a/drivers/staging/dwc2/hcd.c
+++ b/drivers/staging/dwc2/hcd.c
@@ -2396,14 +2396,15 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
                                                !(usb_pipein(urb->pipe))));
 
        buf = urb->transfer_buffer;
+
        if (hcd->self.uses_dma) {
-               /*
-                * Calculate virtual address from physical address, because
-                * some class driver may not fill transfer_buffer.
-                * In Buffer DMA mode virtual address is used, when handling
-                * non-DWORD aligned buffers.
-                */
-               buf = bus_to_virt(urb->transfer_dma);
+               if (!buf && (urb->transfer_dma & 3)) {
+                       dev_err(hsotg->dev,
+                               "%s: unaligned transfer with no transfer_buffer",
+                               __func__);
+                       retval = -EINVAL;
+                       goto fail1;
+               }
        }
 
        if (!(urb->transfer_flags & URB_NO_INTERRUPT))
@@ -2833,9 +2834,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
        if (hsotg->core_params->dma_enable > 0) {
                if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
                        dev_warn(hsotg->dev, "can't set DMA mask\n");
-               if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(31)) < 0)
-                       dev_warn(hsotg->dev,
-                                "can't enable workaround for >2GB RAM\n");
+               if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
+                       dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
        } else {
                dma_set_mask(hsotg->dev, 0);
                dma_set_coherent_mask(hsotg->dev, 0);