If movl top bits are undef, let it be selected to movlps, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50928 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index e9605bb174b846738027aa77e8042a0948d9b256..b30a13c67cc4e0aec480903f6be80b27b938e0ee 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -6326,8 +6326,7 @@ static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
     return SDOperand();
   // This must be an insertion into a zero vector.
   SDOperand HighElt = N->getOperand(1);
-  if (HighElt.getOpcode() != ISD::UNDEF &&
-      !isZeroNode(HighElt))
+  if (!isZeroNode(HighElt))
     return SDOperand();
 
   // Value must be a load.