+// $Id$
//***************************************************************************
// File:
// SparcInstrSelection.cpp
MachineInstr*& getMinstr2);
static void ForwardOperand (InstructionNode* treeNode,
- InstructionNode* parent,
+ InstrTreeNode* parent,
int operandNum);
// Convenience function to get the value of an integer constant, for an
// appropriate integer or non-integer type that can be held in an integer.
// The type of the argument must be the following:
-// GetConstantValueAsSignedInt: any of the above, but the value
-// must fit into a int64_t.
+// Signed or unsigned integer
+// Boolean
+// Pointer
//
// isValidConstant is set to true if a valid constant was found.
//
-
-static int64_t GetConstantValueAsSignedInt(const Value *V,
- bool &isValidConstant) {
+static int64_t
+GetConstantValueAsSignedInt(const Value *V,
+ bool &isValidConstant)
+{
if (!V->isConstant()) { isValidConstant = false; return 0; }
isValidConstant = true;
case 130:
case 131:
case 132:
+ case 133:
case 153:
- case 155: return true; break;
+ case 155:
+ case 221:
+ case 222:
+ case 232:
+ case 241:
+ case 242:
+ case 243:
+ case 244:
+ return true; break;
- default: return false; break;
+ default:
+ return false; break;
}
}
// Set mustClearReg=false if v3 need not be cleared before conditional move.
// Set valueToMove=0 if we want to conditionally move 0 instead of 1
// (i.e., we want to test inverse of a condition)
-//
+// (The latter two cases do not seem to arise because SetNE needs nothing.)
//
static MachineOpCode
ChooseMovpccAfterSub(const InstructionNode* instrNode,
switch(instrNode->getInstruction()->getOpcode())
{
- case Instruction::SetEQ: opCode = MOVNE; mustClearReg = false;
- valueToMove = 0; break;
+ case Instruction::SetEQ: opCode = MOVE; break;
case Instruction::SetLE: opCode = MOVLE; break;
case Instruction::SetGE: opCode = MOVGE; break;
case Instruction::SetLT: opCode = MOVL; break;
case Instruction::SetGT: opCode = MOVG; break;
-
- case Instruction::SetNE: assert(0 && "No move required!");
-
- default:
- assert(0 && "Unrecognized VM instruction!");
- break;
+ case Instruction::SetNE: assert(0 && "No move required!"); break;
+ default: assert(0 && "Unrecognized VM instr!"); break;
}
return opCode;
//
const Type* resultType = instrNode->getInstruction()->getType();
- if (resultType->isIntegral())
+ if (resultType->isIntegral() || resultType->isPointerType())
{
unsigned pow;
bool isValidConst;
//
static void
ForwardOperand(InstructionNode* treeNode,
- InstructionNode* parent,
+ InstrTreeNode* parent,
int operandNum)
{
+ assert(treeNode && parent && "Invalid invocation of ForwardOperand");
+
Instruction* unusedOp = treeNode->getInstruction();
Value* fwdOp = unusedOp->getOperand(operandNum);
- Instruction* userInstr = parent->getInstruction();
+
+ // The parent itself may be a list node, so find the real parent instruction
+ while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
+ {
+ parent = parent->parent();
+ assert(parent && "ERROR: Non-instruction node has no parent in tree.");
+ }
+ InstructionNode* parentInstrNode = (InstructionNode*) parent;
+
+ Instruction* userInstr = parentInstrNode->getInstruction();
MachineCodeForVMInstr& mvec = userInstr->getMachineInstrVec();
for (unsigned i=0, N=mvec.size(); i < N; i++)
{
const Type* opType;
int nextRule;
int forwardOperandNum = -1;
- BranchPattern brPattern;
int64_t s0 = 0; // variables holding zero to avoid
uint64_t u0 = 0; // overloading ambiguities below
mvec[numInstr++] = new MachineInstr(NOP);
break;
- case 6: // stmt: BrCond(boolconst)
- // boolconst => boolean was computed with `%b = setCC type reg1 constant'
+ case 206: // stmt: BrCond(setCCconst)
+ // setCCconst => boolean was computed with `%b = setCC type reg1 constant'
// If the constant is ZERO, we can use the branch-on-integer-register
// instructions and avoid the SUBcc instruction entirely.
// Otherwise this is just the same as case 5, so just fall through.
ConstPoolVal* constVal = (ConstPoolVal*) constNode->getValue();
bool isValidConst;
- if (constVal->getType()->isIntegral()
+ if ((constVal->getType()->isIntegral()
+ || constVal->getType()->isPointerType())
&& GetConstantValueAsSignedInt(constVal, isValidConst) == 0
&& isValidConst)
{
- // That constant ia a zero after all...
+ // That constant is a zero after all...
// Use the left child of the setCC instruction as the first argument!
mvec[0] = new MachineInstr(ChooseBprInstruction(subtreeRoot));
mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
// ELSE FALL THROUGH
}
- case 7: // stmt: BrCond(bool)
- // bool => boolean was computed with `%b = setcc type reg1 reg2'
+ case 6: // stmt: BrCond(bool)
+ // bool => boolean was computed with some boolean operator (setCC,Not,...)
// Need to check whether the type was a FP, signed int or unsigned int,
// and check the branching condition in order to choose the branch to use.
//
break;
}
- case 8: // stmt: BrCond(boolreg)
- // bool => boolean is stored in an existing register.
+ case 8: // stmt: BrCond(boolreg)
+ case 208: // stmt: BrCond(boolconst)
+ // boolreg => boolean is stored in an existing register.
+ // boolconst => boolean is a constant; can be loaded into a register.
// Just use the branch-on-integer-register instruction!
//
mvec[0] = new MachineInstr(BRNZ);
// delay slot
mvec[numInstr++] = new MachineInstr(NOP); // delay slot
-
+
// false branch
mvec[numInstr++] = new MachineInstr(BA);
mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
subtreeRoot->getValue());
break;
+ case 322: // reg: ToBoolTy(bool):
case 22: // reg: ToBoolTy(reg):
opType = subtreeRoot->leftChild()->getValue()->getType();
assert(opType->isIntegral() || opType == Type::BoolTy);
if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() ||
subtreeRoot->leftChild()->getValue()->getType()->isPointerType())
{
- // integer condition: destination should be %g0 or integer register
- // if result must be saved but condition is not SetEQ then we need
+ // Integer condition: destination should be %g0 or integer register.
+ // If result must be saved but condition is not SetEQ then we need
// a separate instruction to compute the bool result, so discard
// result of SUBcc instruction anyway.
//
case 62: // reg: Shl(reg, reg)
opType = subtreeRoot->leftChild()->getValue()->getType();
- assert(opType->isIntegral() || opType == Type::BoolTy);
+ assert(opType->isIntegral()
+ || opType == Type::BoolTy
+ || opType->isPointerType() && "Shl unsupported for other types");
mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL);
Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
break;
case 63: // reg: Shr(reg, reg)
opType = subtreeRoot->leftChild()->getValue()->getType();
- assert(opType->isIntegral() || opType == Type::BoolTy);
+ assert(opType->isIntegral()
+ || opType == Type::BoolTy
+ || opType->isPointerType() && "Shr unsupported for other types");
mvec[0] = new MachineInstr((opType->isSigned()
? ((opType == Type::LongTy)? SRAX : SRA)
: ((opType == Type::LongTy)? SRLX : SRL)));
case 130:
case 131:
case 132:
+ case 133:
case 153:
case 155:
+ case 221:
+ case 222:
+ case 232:
+ case 241:
+ case 242:
+ case 243:
+ case 244:
//
// These are all chain rules, which have a single nonterminal on the RHS.
// Get the rule that matches the RHS non-terminal and use that instead.
// If not, insert a copy instruction which should get coalesced away
// by register allocation.
if (subtreeRoot->parent() != NULL)
- ForwardOperand(subtreeRoot, (InstructionNode*) subtreeRoot->parent(),
- forwardOperandNum);
+ ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
else
{
int n = numInstr++;
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