memory: tegra: Add Tegra132 support
authorThierry Reding <treding@nvidia.com>
Fri, 7 Nov 2014 15:10:41 +0000 (16:10 +0100)
committerThierry Reding <treding@nvidia.com>
Mon, 4 May 2015 10:54:23 +0000 (12:54 +0200)
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/iommu/Kconfig
drivers/memory/tegra/Makefile
drivers/memory/tegra/mc.c
drivers/memory/tegra/mc.h
drivers/memory/tegra/tegra124.c

index 1ae4e547b419b909a9748b54cc6b973d31ff0221..73f918d066c628b7200f9a04700d932d38fe3c11 100644 (file)
@@ -219,7 +219,7 @@ config TEGRA_IOMMU_SMMU
        select IOMMU_API
        help
          This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
-         SoCs (Tegra30 up to Tegra124).
+         SoCs (Tegra30 up to Tegra132).
 
 config EXYNOS_IOMMU
        bool "Exynos IOMMU Support"
index 0d9f497b786c1d239b0ce72096d5539bae262053..9d4f4319b52761b1e21477b19f8f739d1ccba5f8 100644 (file)
@@ -3,5 +3,6 @@ tegra-mc-y := mc.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC)  += tegra30.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
+tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
 
 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
index fe3c44e7e1d1bf8268b1760fb8e9b828af4f3bc1..9b7c1645fd59ef3c2eadf9690b81cc08d3929093 100644 (file)
@@ -57,6 +57,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
 #endif
 #ifdef CONFIG_ARCH_TEGRA_124_SOC
        { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
+#endif
+#ifdef CONFIG_ARCH_TEGRA_132_SOC
+       { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
 #endif
        { }
 };
index d5d21147fc778368ea0451d8c008f643a621c94d..b7361b0a66964ce9a95dc02114cd276d759b6b60 100644 (file)
@@ -37,4 +37,8 @@ extern const struct tegra_mc_soc tegra114_mc_soc;
 extern const struct tegra_mc_soc tegra124_mc_soc;
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_132_SOC
+extern const struct tegra_mc_soc tegra132_mc_soc;
+#endif
+
 #endif /* MEMORY_TEGRA_MC_H */
index e63e05769d0ac8419776ec83f2f78bb1d043b1ed..b996dfb9358bcbc06cdb0a3b3f9984aa593bc253 100644 (file)
@@ -993,3 +993,36 @@ const struct tegra_mc_soc tegra124_mc_soc = {
        .smmu = &tegra124_smmu_soc,
 };
 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
+
+#ifdef CONFIG_ARCH_TEGRA_132_SOC
+static void tegra132_flush_dcache(struct page *page, unsigned long offset,
+                                 size_t size)
+{
+       void *virt = page_address(page) + offset;
+
+       __flush_dcache_area(virt, size);
+}
+
+static const struct tegra_smmu_ops tegra132_smmu_ops = {
+       .flush_dcache = tegra132_flush_dcache,
+};
+
+static const struct tegra_smmu_soc tegra132_smmu_soc = {
+       .clients = tegra124_mc_clients,
+       .num_clients = ARRAY_SIZE(tegra124_mc_clients),
+       .swgroups = tegra124_swgroups,
+       .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
+       .supports_round_robin_arbitration = true,
+       .supports_request_limit = true,
+       .num_asids = 128,
+       .ops = &tegra132_smmu_ops,
+};
+
+const struct tegra_mc_soc tegra132_mc_soc = {
+       .clients = tegra124_mc_clients,
+       .num_clients = ARRAY_SIZE(tegra124_mc_clients),
+       .num_address_bits = 34,
+       .atom_size = 32,
+       .smmu = &tegra132_smmu_soc,
+};
+#endif /* CONFIG_ARCH_TEGRA_132_SOC */