Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/Makefile.rules b/Makefile.rules
index 2acadd84003898f514b1f9ceb6a8beea0061b3ee..46a3f1bdb90883c0db4b6c6eb0bb02e22316e3f0 100644 (file)
--- a/Makefile.rules
+++ b/Makefile.rules
@@ -1720,35 +1720,15 @@ TDFiles := $(strip $(wildcard $(PROJ_SRC_DIR)/*.td) \
 # All of these files depend on tblgen and the .td files.
 $(INCTMPFiles) : $(TBLGEN) $(TDFiles)
 
-$(TARGET:%=$(ObjDir)/%GenRegisterNames.inc.tmp): \
-$(ObjDir)/%GenRegisterNames.inc.tmp : %.td $(ObjDir)/.dir
-       $(Echo) "Building $(<F) register names with tblgen"
-       $(Verb) $(TableGen) -gen-register-enums -o $(call SYSPATH, $@) $<
-
-$(TARGET:%=$(ObjDir)/%GenRegisterDesc.inc.tmp): \
-$(ObjDir)/%GenRegisterDesc.inc.tmp : %.td $(ObjDir)/.dir
-       $(Echo) "Building $(<F) register descriptions with tblgen"
-       $(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
-
-$(TARGET:%=$(ObjDir)/%GenRegisterInfo.h.inc.tmp): \
-$(ObjDir)/%GenRegisterInfo.h.inc.tmp : %.td $(ObjDir)/.dir
-       $(Echo) "Building $(<F) register information header with tblgen"
-       $(Verb) $(TableGen) -gen-register-info-header -o $(call SYSPATH, $@) $<
-
 $(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \
 $(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir
        $(Echo) "Building $(<F) register info implementation with tblgen"
        $(Verb) $(TableGen) -gen-register-info -o $(call SYSPATH, $@) $<
 
-$(TARGET:%=$(ObjDir)/%GenInstrNames.inc.tmp): \
-$(ObjDir)/%GenInstrNames.inc.tmp : %.td $(ObjDir)/.dir
-       $(Echo) "Building $(<F) instruction names with tblgen"
-       $(Verb) $(TableGen) -gen-instr-enums -o $(call SYSPATH, $@) $<
-
 $(TARGET:%=$(ObjDir)/%GenInstrInfo.inc.tmp): \
 $(ObjDir)/%GenInstrInfo.inc.tmp : %.td $(ObjDir)/.dir
        $(Echo) "Building $(<F) instruction information with tblgen"
-       $(Verb) $(TableGen) -gen-instr-desc -o $(call SYSPATH, $@) $<
+       $(Verb) $(TableGen) -gen-instr-info -o $(call SYSPATH, $@) $<
 
 $(TARGET:%=$(ObjDir)/%GenAsmWriter.inc.tmp): \
 $(ObjDir)/%GenAsmWriter.inc.tmp : %.td $(ObjDir)/.dir

diff --git a/include/llvm/MC/MCInstrDesc.h b/include/llvm/MC/MCInstrDesc.h
index 5d0779a12ac79faea4df657837881c47ed2159a6..17d5fdc5d3d39c143ae6aa62919cdf7ced980451 100644 (file)
--- a/include/llvm/MC/MCInstrDesc.h
+++ b/include/llvm/MC/MCInstrDesc.h
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines the McOperandInfo and McInstrDesc classes, which
+// This file defines the MCOperandInfo and MCInstrDesc classes, which
 // are used to describe target instructions and their operands. 
 //
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/ARM/ARMBaseInfo.h b/lib/Target/ARM/ARMBaseInfo.h
index 91e9fd1f9b87cde81b0d36bb966089a4b7ede55c..4c9ecdfdafe6eb7d526140fd2cac40712cb2245a 100644 (file)
--- a/lib/Target/ARM/ARMBaseInfo.h
+++ b/lib/Target/ARM/ARMBaseInfo.h
@@ -30,7 +30,8 @@
 
 // Defines symbolic names for the ARM instructions.
 //
-#include "ARMGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "ARMGenInstrInfo.inc"
 
 namespace llvm {
 

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index c619e8f8c6bc015a5ec0fba95abd20a9df4105ef..31ea95a9ea8519e0e8ae051504400505290defb3 100644 (file)
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -18,7 +18,6 @@
 #include "ARMHazardRecognizer.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMRegisterInfo.h"
-#include "ARMGenInstrInfo.inc"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
 #include "llvm/GlobalValue.h"
@@ -35,6 +34,10 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/ADT/STLExtras.h"
+
+#define GET_INSTRINFO_MC_DESC
+#include "ARMGenInstrInfo.inc"
+
 using namespace llvm;
 
 static cl::opt<bool>

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 6f48d967f919d72e910a861cb23df110ce32c6c1..adcbf1806fe3d182a221fbf37c80ae878d82e37a 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -14,7 +14,6 @@
 #include "ARMInstrInfo.h"
 #include "ARM.h"
 #include "ARMAddressingModes.h"
-#include "ARMGenInstrInfo.inc"
 #include "ARMMachineFunctionInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/LiveVariables.h"

diff --git a/lib/Target/ARM/CMakeLists.txt b/lib/Target/ARM/CMakeLists.txt
index 0a0ed3c741bd1f12b84d382434217d46fca22004..b1d4f540247af5d3847a1e2776ce58daa9e2a34f 100644 (file)
--- a/lib/Target/ARM/CMakeLists.txt
+++ b/lib/Target/ARM/CMakeLists.txt
@@ -1,8 +1,7 @@
 set(LLVM_TARGET_DEFINITIONS ARM.td)
 
 tablegen(ARMGenRegisterInfo.inc -gen-register-info)
-tablegen(ARMGenInstrNames.inc -gen-instr-enums)
-tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
+tablegen(ARMGenInstrInfo.inc -gen-instr-info)
 tablegen(ARMGenCodeEmitter.inc -gen-emitter)
 tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
 tablegen(ARMGenAsmWriter.inc -gen-asm-writer)

diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 851b2d0cf8c18b88cca2a05ee755d27829393068..fe165b04b4346169954c598a6091855aeb46f72b 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -71,6 +71,7 @@
 /// { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), 0 }
 ///
 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
+#define GET_INSTRINFO_MC_DESC
 #include "ARMGenInstrInfo.inc"
 
 using namespace llvm;

diff --git a/lib/Target/ARM/Makefile b/lib/Target/ARM/Makefile
index 9ecbd6b1b1e07b9cccfcb55f39d1f152fe3ca300..6472c53d0d0e0ce3146f0a7418bbe4d12045659b 100644 (file)
--- a/lib/Target/ARM/Makefile
+++ b/lib/Target/ARM/Makefile
@@ -12,8 +12,7 @@ LIBRARYNAME = LLVMARMCodeGen
 TARGET = ARM
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = ARMGenRegisterInfo.inc \
-               ARMGenInstrNames.inc ARMGenInstrInfo.inc \
+BUILT_SOURCES = ARMGenRegisterInfo.inc ARMGenInstrInfo.inc \
                ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
                 ARMGenDAGISel.inc ARMGenSubtarget.inc \
                 ARMGenCodeEmitter.inc ARMGenCallingConv.inc \

diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp
index 3fbb43340c3fd8008743143b21f56916698e3f78..b430ab3a6a6c64748cd02d327c0ce6e0e643b407 100644 (file)
--- a/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -13,7 +13,6 @@
 
 #include "Thumb1InstrInfo.h"
 #include "ARM.h"
-#include "ARMGenInstrInfo.inc"
 #include "ARMMachineFunctionInfo.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"

diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp
index 98151b96bfad72be0afb33620da1c1c72681098d..26e75db02c0257aeb74b9ae963ffb2d86fdce048 100644 (file)
--- a/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -15,7 +15,6 @@
 #include "ARM.h"
 #include "ARMConstantPoolValue.h"
 #include "ARMAddressingModes.h"
-#include "ARMGenInstrInfo.inc"
 #include "ARMMachineFunctionInfo.h"
 #include "Thumb2InstrInfo.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"

diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h
index 174d2613a920ba45c593d267ac9ae16fa3af0df8..435c95cd030690e81a5d1e3e9d7b8320a5142b75 100644 (file)
--- a/lib/Target/Alpha/Alpha.h
+++ b/lib/Target/Alpha/Alpha.h
@@ -50,6 +50,7 @@ namespace llvm {
 
 // Defines symbolic names for the Alpha instructions.
 //
-#include "AlphaGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "AlphaGenInstrInfo.inc"
 
 #endif

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 5a2f5610fdb49b6e1416d058da3094cc59fdc141..589e2d959d68f7591315893931595c8d21507314 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -14,12 +14,14 @@
 #include "Alpha.h"
 #include "AlphaInstrInfo.h"
 #include "AlphaMachineFunctionInfo.h"
-#include "AlphaGenInstrInfo.inc"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/Support/ErrorHandling.h"
+
+#define GET_INSTRINFO_MC_DESC
+#include "AlphaGenInstrInfo.inc"
 using namespace llvm;
 
 AlphaInstrInfo::AlphaInstrInfo()

diff --git a/lib/Target/Alpha/CMakeLists.txt b/lib/Target/Alpha/CMakeLists.txt
index bcde4474437d4c372ca604edaffe8abb66d9a76c..1f9edcf48ab1afbcad1b702ca60ecbf842f10214 100644 (file)
--- a/lib/Target/Alpha/CMakeLists.txt
+++ b/lib/Target/Alpha/CMakeLists.txt
@@ -1,8 +1,7 @@
 set(LLVM_TARGET_DEFINITIONS Alpha.td)
 
 tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
-tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
-tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
+tablegen(AlphaGenInstrInfo.inc -gen-instr-info)
 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
 tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
 tablegen(AlphaGenCallingConv.inc -gen-callingconv)

diff --git a/lib/Target/Alpha/Makefile b/lib/Target/Alpha/Makefile
index bd280a0e1b15f5dab86d90aa190051275bd60ea0..40c4f903f310bb0e743aded287904b680681a0e0 100644 (file)
--- a/lib/Target/Alpha/Makefile
+++ b/lib/Target/Alpha/Makefile
@@ -12,8 +12,7 @@ LIBRARYNAME = LLVMAlphaCodeGen
 TARGET = Alpha
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = AlphaGenRegisterInfo.inc \
-               AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
+BUILT_SOURCES = AlphaGenRegisterInfo.inc AlphaGenInstrInfo.inc \
                 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
                 AlphaGenCallingConv.inc AlphaGenSubtarget.inc
 

diff --git a/lib/Target/Blackfin/Blackfin.h b/lib/Target/Blackfin/Blackfin.h
index 3285c4f631c3592c01bc71d3f533fbc44073f826..c3ee7e71fd7e6b4844416a4cfd82171a24f63b69 100644 (file)
--- a/lib/Target/Blackfin/Blackfin.h
+++ b/lib/Target/Blackfin/Blackfin.h
@@ -34,6 +34,7 @@ namespace llvm {
 #include "BlackfinGenRegisterInfo.inc"
 
 // Defines symbolic names for the Blackfin instructions.
-#include "BlackfinGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "BlackfinGenInstrInfo.inc"
 
 #endif

diff --git a/lib/Target/Blackfin/BlackfinInstrInfo.cpp b/lib/Target/Blackfin/BlackfinInstrInfo.cpp
index 598cf2a68c6bd14d56995b4a11f36346e0da24f4..0b50a95f5e2c42eab57b08c5c86acc19185871d1 100644 (file)
--- a/lib/Target/Blackfin/BlackfinInstrInfo.cpp
+++ b/lib/Target/Blackfin/BlackfinInstrInfo.cpp
@@ -19,6 +19,8 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/Support/ErrorHandling.h"
+
+#define GET_INSTRINFO_MC_DESC
 #include "BlackfinGenInstrInfo.inc"
 
 using namespace llvm;

diff --git a/lib/Target/Blackfin/CMakeLists.txt b/lib/Target/Blackfin/CMakeLists.txt
index c59b5a311ec86f4222922c8fa64b7a873c3681e6..8fc63aa3dc77b0c861e34a28b48432cfa6cef517 100644 (file)
--- a/lib/Target/Blackfin/CMakeLists.txt
+++ b/lib/Target/Blackfin/CMakeLists.txt
@@ -1,8 +1,7 @@
 set(LLVM_TARGET_DEFINITIONS Blackfin.td)
 
 tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
-tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
-tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
+tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
 tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
 tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
 tablegen(BlackfinGenSubtarget.inc -gen-subtarget)

diff --git a/lib/Target/Blackfin/Makefile b/lib/Target/Blackfin/Makefile
index c05d27b4cca3c8c398d814597cb0ccae28d20462..a9edec78b5a0557c387aa2dea837d2a5bb8cd458 100644 (file)
--- a/lib/Target/Blackfin/Makefile
+++ b/lib/Target/Blackfin/Makefile
@@ -12,8 +12,8 @@ LIBRARYNAME = LLVMBlackfinCodeGen
 TARGET = Blackfin
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
-                BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
+BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrInfo.inc \
+               BlackfinGenAsmWriter.inc \
                 BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
                BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
 

diff --git a/lib/Target/CellSPU/CMakeLists.txt b/lib/Target/CellSPU/CMakeLists.txt
index 1cce2c1a6a527365ae912feff00f38235dc579c8..d769cb9316ce034bdb42243b7e395843cdac23dd 100644 (file)
--- a/lib/Target/CellSPU/CMakeLists.txt
+++ b/lib/Target/CellSPU/CMakeLists.txt
@@ -1,10 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS SPU.td)
 
-tablegen(SPUGenInstrNames.inc -gen-instr-enums)
 tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
 tablegen(SPUGenCodeEmitter.inc -gen-emitter)
 tablegen(SPUGenRegisterInfo.inc -gen-register-info)
-tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
+tablegen(SPUGenInstrInfo.inc -gen-instr-info)
 tablegen(SPUGenDAGISel.inc -gen-dag-isel)
 tablegen(SPUGenSubtarget.inc -gen-subtarget)
 tablegen(SPUGenCallingConv.inc -gen-callingconv)

diff --git a/lib/Target/CellSPU/Makefile b/lib/Target/CellSPU/Makefile
index 270bd6b8b380a1537f183970884acfb04557b69c..5bb6f9cc58f931a007143bb1c4f229bb0648e0ef 100644 (file)
--- a/lib/Target/CellSPU/Makefile
+++ b/lib/Target/CellSPU/Makefile
@@ -10,9 +10,9 @@
 LEVEL = ../../..
 LIBRARYNAME = LLVMCellSPUCodeGen
 TARGET = SPU
-BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \
+BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \
                SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
-               SPUGenInstrInfo.inc SPUGenDAGISel.inc \
+               SPUGenDAGISel.inc \
                SPUGenSubtarget.inc SPUGenCallingConv.inc
 
 DIRS = TargetInfo

diff --git a/lib/Target/CellSPU/SPU.h b/lib/Target/CellSPU/SPU.h
index 72f84300b2c3e43b869ea67c2230ba9ce79410e1..5c81c9a77a3c74afc2f01c0be6f34f97775fdc60 100644 (file)
--- a/lib/Target/CellSPU/SPU.h
+++ b/lib/Target/CellSPU/SPU.h
@@ -30,6 +30,7 @@ namespace llvm {
 
 // Defines symbolic names for the SPU instructions.
 //
-#include "SPUGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "SPUGenInstrInfo.inc"
 
 #endif /* LLVM_TARGET_IBMCELLSPU_H */

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 080434d66789503a8083c8178a54eafaf66d7fa2..1107cff9dabe38115a00663f30016129737acb31 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -15,7 +15,6 @@
 #include "SPUInstrInfo.h"
 #include "SPUInstrBuilder.h"
 #include "SPUTargetMachine.h"
-#include "SPUGenInstrInfo.inc"
 #include "SPUHazardRecognizers.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/Support/Debug.h"
@@ -23,6 +22,9 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/MC/MCContext.h"
 
+#define GET_INSTRINFO_MC_DESC
+#include "SPUGenInstrInfo.inc"
+
 using namespace llvm;
 
 namespace {

diff --git a/lib/Target/MBlaze/CMakeLists.txt b/lib/Target/MBlaze/CMakeLists.txt
index 498edd46fb28d7c293515c0a10ff2d8c1544378d..2aa984789d1bfabc3906327ac91b959d50d8503f 100644 (file)
--- a/lib/Target/MBlaze/CMakeLists.txt
+++ b/lib/Target/MBlaze/CMakeLists.txt
@@ -1,8 +1,7 @@
 set(LLVM_TARGET_DEFINITIONS MBlaze.td)
 
 tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
-tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
-tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
+tablegen(MBlazeGenInstrInfo.inc -gen-instr-info)
 tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
 tablegen(MBlazeGenAsmWriter.inc -gen-asm-writer)
 tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)

diff --git a/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp b/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
index 060a87b7c616a4e052511c22e4fb1bd2291424c8..14642742e349c8ac1f3f991b672195c35139db02 100644 (file)
--- a/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
+++ b/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
@@ -27,6 +27,7 @@
 
 // #include "MBlazeGenDecoderTables.inc"
 // #include "MBlazeGenRegisterNames.inc"
+#define GET_INSTRINFO_MC_DESC
 #include "MBlazeGenInstrInfo.inc"
 #include "MBlazeGenEDInfo.inc"
 

diff --git a/lib/Target/MBlaze/MBlaze.h b/lib/Target/MBlaze/MBlaze.h
index c6181f70bcf4e61ac4ce657bd3228fbbaba6bd9c..e9aff5b96be0ffcb3616741ac0c076b2de5a9185 100644 (file)
--- a/lib/Target/MBlaze/MBlaze.h
+++ b/lib/Target/MBlaze/MBlaze.h
@@ -43,6 +43,7 @@ namespace llvm {
 #include "MBlazeGenRegisterInfo.inc"
 
 // Defines symbolic names for the MBlaze instructions.
-#include "MBlazeGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "MBlazeGenInstrInfo.inc"
 
 #endif

diff --git a/lib/Target/MBlaze/MBlazeInstrInfo.cpp b/lib/Target/MBlaze/MBlazeInstrInfo.cpp
index 794ebedf1e6a5be1e327ca2de2aec9e83c5ddc16..adc81ff444e411aa6c79c66f38929a0d2850fb87 100644 (file)
--- a/lib/Target/MBlaze/MBlazeInstrInfo.cpp
+++ b/lib/Target/MBlaze/MBlazeInstrInfo.cpp
@@ -20,6 +20,8 @@
 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
+
+#define GET_INSTRINFO_MC_DESC
 #include "MBlazeGenInstrInfo.inc"
 
 using namespace llvm;

diff --git a/lib/Target/MBlaze/Makefile b/lib/Target/MBlaze/Makefile
index 010885f04b9425acbc2152c3c24dfe71089eb11e..171548f47bc166d76b1e62a82360af851629190a 100644 (file)
--- a/lib/Target/MBlaze/Makefile
+++ b/lib/Target/MBlaze/Makefile
@@ -11,8 +11,8 @@ LIBRARYNAME = LLVMMBlazeCodeGen
 TARGET = MBlaze
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
-                MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
+BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrInfo.inc \
+               MBlazeGenAsmWriter.inc \
                 MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
                 MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
                 MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \

diff --git a/lib/Target/MSP430/CMakeLists.txt b/lib/Target/MSP430/CMakeLists.txt
index bf58fd2e806f98144309a604454298eb2af74a5e..613b25919626633f558b97ab70552a094dcd71c0 100644 (file)
--- a/lib/Target/MSP430/CMakeLists.txt
+++ b/lib/Target/MSP430/CMakeLists.txt
@@ -1,8 +1,7 @@
 set(LLVM_TARGET_DEFINITIONS MSP430.td)
 
 tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
-tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
-tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
+tablegen(MSP430GenInstrInfo.inc -gen-instr-info)
 tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
 tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
 tablegen(MSP430GenCallingConv.inc -gen-callingconv)

diff --git a/lib/Target/MSP430/MSP430.h b/lib/Target/MSP430/MSP430.h
index 2dabe7c0d3fca6723d5488b9abac5b5d234b2b07..854d4e457c8d21ef9cef076bad076e43a53024f1 100644 (file)
--- a/lib/Target/MSP430/MSP430.h
+++ b/lib/Target/MSP430/MSP430.h
@@ -51,6 +51,7 @@ namespace llvm {
 #include "MSP430GenRegisterInfo.inc"
 
 // Defines symbolic names for the MSP430 instructions.
-#include "MSP430GenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "MSP430GenInstrInfo.inc"
 
 #endif

diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp
index 8ea84906bf08e79905ea887d3b0e441f700ecbb3..b883f46dc6b891af22f5c3cdd70da3d97dae1e89 100644 (file)
--- a/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -15,7 +15,6 @@
 #include "MSP430InstrInfo.h"
 #include "MSP430MachineFunctionInfo.h"
 #include "MSP430TargetMachine.h"
-#include "MSP430GenInstrInfo.inc"
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -23,6 +22,9 @@
 #include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Support/ErrorHandling.h"
 
+#define GET_INSTRINFO_MC_DESC
+#include "MSP430GenInstrInfo.inc"
+
 using namespace llvm;
 
 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)

diff --git a/lib/Target/MSP430/Makefile b/lib/Target/MSP430/Makefile
index cdbbf0ef53e52f27a3150a0c939fe951da87f5b5..266330ae996d108fa6d6fb1eaedb5b4da39beead 100644 (file)
--- a/lib/Target/MSP430/Makefile
+++ b/lib/Target/MSP430/Makefile
@@ -12,8 +12,8 @@ LIBRARYNAME = LLVMMSP430CodeGen
 TARGET = MSP430
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
-               MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
+BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrInfo.inc \
+               MSP430GenAsmWriter.inc \
                MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
                MSP430GenSubtarget.inc
 

diff --git a/lib/Target/Mips/CMakeLists.txt b/lib/Target/Mips/CMakeLists.txt
index aa51fbf8a57a81c08ff2b6152a143781f72936f1..71b13c8dcbd9c7813860bba4570e9dde1acf4ce7 100644 (file)
--- a/lib/Target/Mips/CMakeLists.txt
+++ b/lib/Target/Mips/CMakeLists.txt
@@ -1,8 +1,7 @@
 set(LLVM_TARGET_DEFINITIONS Mips.td)
 
 tablegen(MipsGenRegisterInfo.inc -gen-register-info)
-tablegen(MipsGenInstrNames.inc -gen-instr-enums)
-tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
+tablegen(MipsGenInstrInfo.inc -gen-instr-info)
 tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
 tablegen(MipsGenDAGISel.inc -gen-dag-isel)
 tablegen(MipsGenCallingConv.inc -gen-callingconv)

diff --git a/lib/Target/Mips/Makefile b/lib/Target/Mips/Makefile
index 3f5cfd7f0b6ddea9b0e35d36a83ebbb417158530..0b6dd563f1a6cb859cd1a082ce3ce337bf43b516 100644 (file)
--- a/lib/Target/Mips/Makefile
+++ b/lib/Target/Mips/Makefile
@@ -12,8 +12,8 @@ LIBRARYNAME = LLVMMipsCodeGen
 TARGET = Mips
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
-                MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
+BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
+               MipsGenAsmWriter.inc \
                 MipsGenDAGISel.inc MipsGenCallingConv.inc \
                 MipsGenSubtarget.inc
 

diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h
index d296b36e658d97000c767f9a06b24764b72ddb9d..738b48c7fbc11759c87bef1631326f25adea95ee 100644 (file)
--- a/lib/Target/Mips/Mips.h
+++ b/lib/Target/Mips/Mips.h
@@ -39,6 +39,7 @@ namespace llvm {
 #include "MipsGenRegisterInfo.inc"
 
 // Defines symbolic names for the Mips instructions.
-#include "MipsGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "MipsGenInstrInfo.inc"
 
 #endif

diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index df5a089588f16ca1d45465ea3693a6a7d96c9948..a56c68bdd844931d50ebe8dd6c36b67354ec0343 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -18,6 +18,8 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/ErrorHandling.h"
+
+#define GET_INSTRINFO_MC_DESC
 #include "MipsGenInstrInfo.inc"
 
 using namespace llvm;

diff --git a/lib/Target/PTX/CMakeLists.txt b/lib/Target/PTX/CMakeLists.txt
index 42b1925e9d5b58934b54a9b2626b15346735b566..33bae7cdbd282b0b67fb7942fa710f016c236579 100644 (file)
--- a/lib/Target/PTX/CMakeLists.txt
+++ b/lib/Target/PTX/CMakeLists.txt
@@ -3,8 +3,7 @@ set(LLVM_TARGET_DEFINITIONS PTX.td)
 tablegen(PTXGenAsmWriter.inc -gen-asm-writer)
 tablegen(PTXGenCallingConv.inc -gen-callingconv)
 tablegen(PTXGenDAGISel.inc -gen-dag-isel)
-tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
-tablegen(PTXGenInstrNames.inc -gen-instr-enums)
+tablegen(PTXGenInstrInfo.inc -gen-instr-info)
 tablegen(PTXGenRegisterInfo.inc -gen-register-info)
 tablegen(PTXGenSubtarget.inc -gen-subtarget)
 

diff --git a/lib/Target/PTX/Makefile b/lib/Target/PTX/Makefile
index 7c3f318aac9b253f4ef8ebe7fe7aa943ad83d789..9dccb4a72a606789991676da8d831c0a76b0cd9f 100644 (file)
--- a/lib/Target/PTX/Makefile
+++ b/lib/Target/PTX/Makefile
@@ -16,7 +16,6 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \
                PTXGenCallingConv.inc \
                PTXGenDAGISel.inc \
                PTXGenInstrInfo.inc \
-               PTXGenInstrNames.inc \
                PTXGenRegisterInfo.inc \
                PTXGenSubtarget.inc
 

diff --git a/lib/Target/PTX/PTX.h b/lib/Target/PTX/PTX.h
index 345f87a996ef59f08cfaa4674cad6bed6eeb1f4b..6aaf0686c2f7788034c98c2e6e43377959a1391c 100644 (file)
--- a/lib/Target/PTX/PTX.h
+++ b/lib/Target/PTX/PTX.h
@@ -51,6 +51,7 @@ namespace llvm {
 #include "PTXGenRegisterInfo.inc"
 
 // Defines symbolic names for the PTX instructions.
-#include "PTXGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "PTXGenInstrInfo.inc"
 
 #endif // PTX_H

diff --git a/lib/Target/PTX/PTXInstrInfo.cpp b/lib/Target/PTX/PTXInstrInfo.cpp
index 665685d602a37686eeb1136be872561227967de6..1bbd8d5bc58f6a3ddd03305d7591f3d6a271661d 100644 (file)
--- a/lib/Target/PTX/PTXInstrInfo.cpp
+++ b/lib/Target/PTX/PTXInstrInfo.cpp
@@ -21,10 +21,11 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
-using namespace llvm;
-
+#define GET_INSTRINFO_MC_DESC
 #include "PTXGenInstrInfo.inc"
 
+using namespace llvm;
+
 PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM)
   : TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)),
     RI(_TM, *this), TM(_TM) {}

diff --git a/lib/Target/PowerPC/CMakeLists.txt b/lib/Target/PowerPC/CMakeLists.txt
index ca5daec2102514ca509f5f3a8f3e020e7578540c..ea11f4c3a78a70a8f8435d288aacf08596cdbbc3 100644 (file)
--- a/lib/Target/PowerPC/CMakeLists.txt
+++ b/lib/Target/PowerPC/CMakeLists.txt
@@ -1,11 +1,10 @@
 set(LLVM_TARGET_DEFINITIONS PPC.td)
 
-tablegen(PPCGenInstrNames.inc -gen-instr-enums)
 tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
 tablegen(PPCGenCodeEmitter.inc -gen-emitter)
 tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
 tablegen(PPCGenRegisterInfo.inc -gen-register-info)
-tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
+tablegen(PPCGenInstrInfo.inc -gen-instr-info)
 tablegen(PPCGenDAGISel.inc -gen-dag-isel)
 tablegen(PPCGenCallingConv.inc -gen-callingconv)
 tablegen(PPCGenSubtarget.inc -gen-subtarget)

diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile
index d7a57f9fa2c969155f731e95627e864b7573ccdc..2a18db7ad9bb0542a3732bbe377fdeda2da356e3 100644 (file)
--- a/lib/Target/PowerPC/Makefile
+++ b/lib/Target/PowerPC/Makefile
@@ -12,7 +12,7 @@ LIBRARYNAME = LLVMPowerPCCodeGen
 TARGET = PPC
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \
+BUILT_SOURCES = PPCGenRegisterInfo.inc \
                 PPCGenAsmWriter.inc  PPCGenCodeEmitter.inc \
                 PPCGenInstrInfo.inc PPCGenDAGISel.inc \
                 PPCGenSubtarget.inc PPCGenCallingConv.inc \

diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h
index a8ab8f29954919e20b72db81969806bf7bfe55b5..55852e69da5dfba31f22609b81a3ad49d5e1ae1b 100644 (file)
--- a/lib/Target/PowerPC/PPC.h
+++ b/lib/Target/PowerPC/PPC.h
@@ -89,6 +89,7 @@ namespace llvm {
 
 // Defines symbolic names for the PowerPC instructions.
 //
-#include "PPCGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "PPCGenInstrInfo.inc"
 
 #endif

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index c3fbc8be5383c0ce8292ddfc3a5ae3be4915765b..dade833864fac68c6b7ada8892830afa20bf0e23 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -15,7 +15,6 @@
 #include "PPCInstrBuilder.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCPredicates.h"
-#include "PPCGenInstrInfo.inc"
 #include "PPCTargetMachine.h"
 #include "PPCHazardRecognizers.h"
 #include "llvm/ADT/STLExtras.h"
@@ -29,6 +28,9 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/MC/MCAsmInfo.h"
 
+#define GET_INSTRINFO_MC_DESC
+#include "PPCGenInstrInfo.inc"
+
 namespace llvm {
 extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
 extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.

diff --git a/lib/Target/Sparc/CMakeLists.txt b/lib/Target/Sparc/CMakeLists.txt
index 1a5b036c7ffed1072332c73dc9337d6f91851136..f3c691f52641848fc8654199fb93b312295250f0 100644 (file)
--- a/lib/Target/Sparc/CMakeLists.txt
+++ b/lib/Target/Sparc/CMakeLists.txt
@@ -1,8 +1,7 @@
 set(LLVM_TARGET_DEFINITIONS Sparc.td)
 
 tablegen(SparcGenRegisterInfo.inc -gen-register-info)
-tablegen(SparcGenInstrNames.inc -gen-instr-enums)
-tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
+tablegen(SparcGenInstrInfo.inc -gen-instr-info)
 tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
 tablegen(SparcGenDAGISel.inc -gen-dag-isel)
 tablegen(SparcGenSubtarget.inc -gen-subtarget)

diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile
index 4ef15193461ebc0c5fb5ef435493a03b2c3f1a15..c8741b525b547891446be2a4d20ccaf7882fc19e 100644 (file)
--- a/lib/Target/Sparc/Makefile
+++ b/lib/Target/Sparc/Makefile
@@ -12,8 +12,8 @@ LIBRARYNAME = LLVMSparcCodeGen
 TARGET = Sparc
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
-                SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
+BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
+               SparcGenAsmWriter.inc \
                 SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
 
 DIRS = TargetInfo

diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h
index 0f03ca359886e4d9e4706fcf8981036be1f286a3..d68535b60462393f985c448543ed96623d509207 100644 (file)
--- a/lib/Target/Sparc/Sparc.h
+++ b/lib/Target/Sparc/Sparc.h
@@ -41,7 +41,8 @@ namespace llvm {
 
 // Defines symbolic names for the Sparc instructions.
 //
-#include "SparcGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "SparcGenInstrInfo.inc"
 
 
 namespace llvm {

diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index afa3c1f88f96074b001d2bd007815935afe0aa4b..c323af8625d703ce5b10ac8b108f0afa1599ffa1 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -19,8 +19,11 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "SparcGenInstrInfo.inc"
 #include "SparcMachineFunctionInfo.h"
+
+#define GET_INSTRINFO_MC_DESC
+#include "SparcGenInstrInfo.inc"
+
 using namespace llvm;
 
 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)

diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt
index 5adf5e31615cb63d403b3aff173881f1cf8aef5b..47c7a9fe6c621078e82bcfce68a5c4b815922ec0 100644 (file)
--- a/lib/Target/SystemZ/CMakeLists.txt
+++ b/lib/Target/SystemZ/CMakeLists.txt
@@ -1,8 +1,7 @@
 set(LLVM_TARGET_DEFINITIONS SystemZ.td)
 
 tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
-tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
-tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
+tablegen(SystemZGenInstrInfo.inc -gen-instr-info)
 tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
 tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
 tablegen(SystemZGenCallingConv.inc -gen-callingconv)

diff --git a/lib/Target/SystemZ/Makefile b/lib/Target/SystemZ/Makefile
index 4b45615bc4f0237a7648bdbb186c8c10bd5bfac7..682f343046d5fade9148855e826e9f15ca27fcfc 100644 (file)
--- a/lib/Target/SystemZ/Makefile
+++ b/lib/Target/SystemZ/Makefile
@@ -12,8 +12,8 @@ LIBRARYNAME = LLVMSystemZCodeGen
 TARGET = SystemZ
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
-                SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
+BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrInfo.inc \
+               SystemZGenAsmWriter.inc \
                 SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
 
 DIRS = TargetInfo

diff --git a/lib/Target/SystemZ/SystemZ.h b/lib/Target/SystemZ/SystemZ.h
index 8bf9fc54e8048cd411029291cb7ca3795df4aeeb..84d83c00d9469a5e795231972c4b885c123423e0 100644 (file)
--- a/lib/Target/SystemZ/SystemZ.h
+++ b/lib/Target/SystemZ/SystemZ.h
@@ -57,6 +57,7 @@ namespace llvm {
 #include "SystemZGenRegisterInfo.inc"
 
 // Defines symbolic names for the SystemZ instructions.
-#include "SystemZGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "SystemZGenInstrInfo.inc"
 
 #endif

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 9488defc0afe8ff9d5b92e4242c593765649c12c..b70e075f750912cb110e10f13702b462b6c2bde6 100644 (file)
--- a/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -16,13 +16,16 @@
 #include "SystemZInstrInfo.h"
 #include "SystemZMachineFunctionInfo.h"
 #include "SystemZTargetMachine.h"
-#include "SystemZGenInstrInfo.inc"
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Support/ErrorHandling.h"
+
+#define GET_INSTRINFO_MC_DESC
+#include "SystemZGenInstrInfo.inc"
+
 using namespace llvm;
 
 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)

diff --git a/lib/Target/X86/CMakeLists.txt b/lib/Target/X86/CMakeLists.txt
index 31d69af890a3e4638346eef0cfe31b8c5972d127..50464e8e9e7d004d9b005dbb87a0ff27bb495ea0 100644 (file)
--- a/lib/Target/X86/CMakeLists.txt
+++ b/lib/Target/X86/CMakeLists.txt
@@ -2,8 +2,7 @@ set(LLVM_TARGET_DEFINITIONS X86.td)
 
 tablegen(X86GenRegisterInfo.inc -gen-register-info)
 tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
-tablegen(X86GenInstrNames.inc -gen-instr-enums)
-tablegen(X86GenInstrInfo.inc -gen-instr-desc)
+tablegen(X86GenInstrInfo.inc -gen-instr-info)
 tablegen(X86GenAsmWriter.inc -gen-asm-writer)
 tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
 tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)

diff --git a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
index d01a6007f21d0cac987d25e5076ebab5266ba434..53738b131df1e89d94f1fb772fab91369ee4cfa1 100644 (file)
--- a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
+++ b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
@@ -16,19 +16,17 @@
 #include "X86ATTInstPrinter.h"
 #include "X86InstComments.h"
 #include "X86Subtarget.h"
+#include "MCTargetDesc/X86TargetDesc.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/FormattedStream.h"
-#include "X86GenInstrNames.inc"
 #include <map>
 using namespace llvm;
 
 // Include the auto-generated portion of the assembly writer.
-#define GET_REGINFO_ENUM
-#include "X86GenRegisterInfo.inc"
 #define GET_INSTRUCTION_NAME
 #define PRINT_ALIAS_INSTR
 #include "X86GenAsmWriter.inc"

diff --git a/lib/Target/X86/InstPrinter/X86InstComments.cpp b/lib/Target/X86/InstPrinter/X86InstComments.cpp
index c642acc3b9a24c742b143340da57c47c98bfec75..5461c83d4d446833cbc16955a53bf479e8c2cdb3 100644 (file)
--- a/lib/Target/X86/InstPrinter/X86InstComments.cpp
+++ b/lib/Target/X86/InstPrinter/X86InstComments.cpp
@@ -13,7 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86InstComments.h"
-#include "X86GenInstrNames.inc"
+#include "MCTargetDesc/X86TargetDesc.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/raw_ostream.h"
 #include "../Utils/X86ShuffleDecode.h"

diff --git a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
index 5f581bab3906d44c9dd78269d402b9222b2401a2..411d832f278169971ee4cf41cc96daf02b3c9a89 100644 (file)
--- a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
+++ b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
@@ -16,12 +16,12 @@
 #include "X86IntelInstPrinter.h"
 #include "X86InstComments.h"
 #include "X86Subtarget.h"
+#include "MCTargetDesc/X86TargetDesc.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
-#include "X86GenInstrNames.inc"
 #include <cctype>
 using namespace llvm;
 

diff --git a/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
index 7aa77bdf6f8d35d4c33d7263c2ef565c81aab0d5..77bfbb9e74c39ff2937bc17e3a159baa33e594c5 100644 (file)
--- a/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
@@ -12,11 +12,16 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86TargetDesc.h"
+#include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Target/TargetRegistry.h"
 
 #define GET_REGINFO_MC_DESC
 #include "X86GenRegisterInfo.inc"
+
+#define GET_INSTRINFO_MC_DESC
+#include "X86GenInstrInfo.inc"
+
 using namespace llvm;
 
 MCRegisterInfo *createX86MCRegisterInfo() {

diff --git a/lib/Target/X86/MCTargetDesc/X86TargetDesc.h b/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
index 0d876dc953c7785a20cd17c1b5d6204aff1c54a5..9ab622d31d196f73256f5646be95abd977db992d 100644 (file)
--- a/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
+++ b/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
@@ -26,4 +26,9 @@ extern Target TheX86_32Target, TheX86_64Target;
 #define GET_REGINFO_ENUM
 #include "X86GenRegisterInfo.inc"
 
+// Defines symbolic names for the X86 instructions.
+//
+#define GET_INSTRINFO_ENUM
+#include "X86GenInstrInfo.inc"
+
 #endif

diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile
index fad83438d06a7445aeef7ff04b02ae7b43711e80..25da36740fba69daded8d579c90fd73a7163a7a8 100644 (file)
--- a/lib/Target/X86/Makefile
+++ b/lib/Target/X86/Makefile
@@ -12,8 +12,7 @@ LIBRARYNAME = LLVMX86CodeGen
 TARGET = X86
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = X86GenRegisterInfo.inc \
-               X86GenInstrNames.inc X86GenInstrInfo.inc \
+BUILT_SOURCES = X86GenRegisterInfo.inc X86GenInstrInfo.inc \
                X86GenAsmWriter.inc X86GenAsmMatcher.inc \
                 X86GenAsmWriter1.inc X86GenDAGISel.inc  \
                 X86GenDisassemblerTables.inc X86GenFastISel.inc \

diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index 896bf0a7dca70ccae8b6582e334e7a6bee1a7672..9d66c2f84f910597715e1f616319caba4d37c70e 100644 (file)
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -15,6 +15,7 @@
 #ifndef TARGET_X86_H
 #define TARGET_X86_H
 
+#include "MCTargetDesc/X86TargetDesc.h"
 #include "llvm/Support/DataTypes.h"
 #include "llvm/Target/TargetMachine.h"
 
@@ -86,10 +87,4 @@ MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
 
 } // End llvm namespace
 
-#include "MCTargetDesc/X86TargetDesc.h"
-
-// Defines symbolic names for the X86 instructions.
-//
-#include "X86GenInstrNames.inc"
-
 #endif

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index f875010e04e942ad2238e28d5411586f45561684..3112dc7382a4bdf15765845794244bafbe7db0bc 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -13,7 +13,6 @@
 
 #include "X86InstrInfo.h"
 #include "X86.h"
-#include "X86GenInstrInfo.inc"
 #include "X86InstrBuilder.h"
 #include "X86MachineFunctionInfo.h"
 #include "X86Subtarget.h"
@@ -36,6 +35,9 @@
 #include "llvm/MC/MCAsmInfo.h"
 #include <limits>
 
+#define GET_INSTRINFO_MC_DESC
+#include "X86GenInstrInfo.inc"
+
 using namespace llvm;
 
 static cl::opt<bool>

diff --git a/lib/Target/XCore/CMakeLists.txt b/lib/Target/XCore/CMakeLists.txt
index f6e7c20c910979a26fb3589c70dbe7e6b59cb451..358141cab9080ae84d28a2e5e4b542ce4625ae7c 100644 (file)
--- a/lib/Target/XCore/CMakeLists.txt
+++ b/lib/Target/XCore/CMakeLists.txt
@@ -1,8 +1,7 @@
 set(LLVM_TARGET_DEFINITIONS XCore.td)
 
 tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
-tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
-tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
+tablegen(XCoreGenInstrInfo.inc -gen-instr-info)
 tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
 tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
 tablegen(XCoreGenCallingConv.inc -gen-callingconv)

diff --git a/lib/Target/XCore/Makefile b/lib/Target/XCore/Makefile
index ddc85dd09c7a046d76b681443e37758691e109fc..ec6fb4c604080a99b08124b30752724b7389fd65 100644 (file)
--- a/lib/Target/XCore/Makefile
+++ b/lib/Target/XCore/Makefile
@@ -12,8 +12,8 @@ LIBRARYNAME = LLVMXCoreCodeGen
 TARGET = XCore
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
-                XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
+BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \
+               XCoreGenAsmWriter.inc \
                 XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
                XCoreGenSubtarget.inc
 

diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h
index 69c343dc2fbe9ddbecb7b293d49a40f68a1ea200..ec4ab911281853b6ee26fe67ba4df716016bc980 100644 (file)
--- a/lib/Target/XCore/XCore.h
+++ b/lib/Target/XCore/XCore.h
@@ -37,6 +37,7 @@ namespace llvm {
 
 // Defines symbolic names for the XCore instructions.
 //
-#include "XCoreGenInstrNames.inc"
+#define GET_INSTRINFO_ENUM
+#include "XCoreGenInstrInfo.inc"
 
 #endif

diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp
index 9cb6a7d17b5ed1f94431bd6b04305c6e2c5d8394..97a1d52be8691ff80b010d35c29dac91c3a771bd 100644 (file)
--- a/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -18,11 +18,13 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineLocation.h"
-#include "XCoreGenInstrInfo.inc"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 
+#define GET_INSTRINFO_MC_DESC
+#include "XCoreGenInstrInfo.inc"
+
 namespace llvm {
 namespace XCore {
 

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index fa2b19264d9f98b7ff4ab45301d19b3f1c539315..2f21ea6e3999e3cb8ce1f0cbaa70d3c6246146f5 100644 (file)
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -156,9 +156,15 @@ void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
 
 // run - Emit the main instruction description records for the target...
 void InstrInfoEmitter::run(raw_ostream &OS) {
+  emitEnums(OS);
+
   GatherItinClasses();
 
   EmitSourceFileHeader("Target Instruction Descriptors", OS);
+
+  OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
+  OS << "#undef GET_INSTRINFO_MC_DESC\n";
+
   OS << "namespace llvm {\n\n";
 
   CodeGenTarget &Target = CDP.getTargetInfo();
@@ -202,6 +208,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
                OperandInfoIDs, OS);
   OS << "};\n";
   OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
 }
 
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
@@ -283,3 +291,38 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
 
   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 }
+
+// emitEnums - Print out enum values for all of the instructions.
+void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
+  EmitSourceFileHeader("Target Instruction Enum Values", OS);
+
+  OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
+  OS << "#undef GET_INSTRINFO_ENUM\n";
+
+  OS << "namespace llvm {\n\n";
+
+  CodeGenTarget Target(Records);
+
+  // We must emit the PHI opcode first...
+  std::string Namespace = Target.getInstNamespace();
+  
+  if (Namespace.empty()) {
+    fprintf(stderr, "No instructions defined!\n");
+    exit(1);
+  }
+
+  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+    Target.getInstructionsByEnumValue();
+
+  OS << "namespace " << Namespace << " {\n";
+  OS << "  enum {\n";
+  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+    OS << "    " << NumberedInstructions[i]->TheDef->getName()
+       << "\t= " << i << ",\n";
+  }
+  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
+  OS << "  };\n}\n";
+  OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_INSTRINFO_ENUM\n\n";
+}

diff --git a/utils/TableGen/InstrInfoEmitter.h b/utils/TableGen/InstrInfoEmitter.h
index a665d40ecb19ff5b1fd4e178846756fd5e3ea841..165ce423ab60a61f98707a133601411390f77a88 100644 (file)
--- a/utils/TableGen/InstrInfoEmitter.h
+++ b/utils/TableGen/InstrInfoEmitter.h
@@ -39,8 +39,9 @@ public:
   void run(raw_ostream &OS);
 
 private:
-  typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
-  
+  void emitEnums(raw_ostream &OS);
+
+  typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;  
   void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                   Record *InstrInfo, 
                   std::map<std::vector<Record*>, unsigned> &EL,

diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index 6f220c92c6802799dab4d83e0caa85b1780ea041..ce16c9ade8ea59f9b679ac32c938c3d36380f7b8 100644 (file)
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -28,7 +28,6 @@
 #include "EDEmitter.h"
 #include "Error.h"
 #include "FastISelEmitter.h"
-#include "InstrEnumEmitter.h"
 #include "InstrInfoEmitter.h"
 #include "IntrinsicEmitter.h"
 #include "LLVMCConfigurationEmitter.h"
@@ -55,7 +54,9 @@ enum ActionType {
   PrintRecords,
   GenEmitter,
   GenRegisterInfo,
-  GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
+  GenInstrInfo,
+  GenAsmWriter,
+  GenAsmMatcher,
   GenARMDecoder,
   GenDisassembler,
   GenCallingConv,
@@ -95,9 +96,7 @@ namespace {
                                "Generate machine code emitter"),
                     clEnumValN(GenRegisterInfo, "gen-register-info",
                                "Generate registers and register classes info"),
-                    clEnumValN(GenInstrEnums, "gen-instr-enums",
-                               "Generate enum values for instructions"),
-                    clEnumValN(GenInstrs, "gen-instr-desc",
+                    clEnumValN(GenInstrInfo, "gen-instr-info",
                                "Generate instruction descriptions"),
                     clEnumValN(GenCallingConv, "gen-callingconv",
                                "Generate calling convention descriptions"),
@@ -260,10 +259,7 @@ int main(int argc, char **argv) {
     case GenRegisterInfo:
       RegisterInfoEmitter(Records).run(Out.os());
       break;
-    case GenInstrEnums:
-      InstrEnumEmitter(Records).run(Out.os());
-      break;
-    case GenInstrs:
+    case GenInstrInfo:
       InstrInfoEmitter(Records).run(Out.os());
       break;
     case GenCallingConv: