If two instructions are both two-address code, favors (schedule closer to

terminator) the one that has a CopyToReg use. This fixes
2006-05-11-InstrSched.ll with -new-cc-modeling-scheme.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42453 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index cb95c214dfbf663909d01f117150dfed8fc39cdc..9b5724bef92b7e36dbbd6849f8166c6e63576f7e 100644 (file)
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -115,7 +115,7 @@ namespace llvm {
     short NumSuccsLeft;                 // # of succs not scheduled.
     bool isTwoAddress     : 1;          // Is a two-address instruction.
     bool isCommutable     : 1;          // Is a commutable instruction.
-    bool hasImplicitDefs  : 1;          // Has implicit physical reg defs.
+    bool hasPhysRegDefs  : 1;           // Has physreg defs that are being used.
     bool isPending        : 1;          // True once pending.
     bool isAvailable      : 1;          // True once available.
     bool isScheduled      : 1;          // True once scheduled.
@@ -129,7 +129,7 @@ namespace llvm {
     SUnit(SDNode *node, unsigned nodenum)
       : Node(node), InstanceNo(0), NodeNum(nodenum), Latency(0),
         NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
-        isTwoAddress(false), isCommutable(false), hasImplicitDefs(false),
+        isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
         isPending(false), isAvailable(false), isScheduled(false),
         CycleBound(0), Cycle(0), Depth(0), Height(0),
         CopyDstRC(NULL), CopySrcRC(NULL) {}

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 4fdf6a8673111f688fc0d40e30ae668d721c6901..d90accda627fd9a329b069768c2c6ba435d0fc71 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -63,7 +63,7 @@ SUnit *ScheduleDAG::Clone(SUnit *Old) {
   SU->Latency = Old->Latency;
   SU->isTwoAddress = Old->isTwoAddress;
   SU->isCommutable = Old->isCommutable;
-  SU->hasImplicitDefs = Old->hasImplicitDefs;
+  SU->hasPhysRegDefs = Old->hasPhysRegDefs;
   SUnitMap[Old->Node].push_back(SU);
   return SU;
 }
@@ -167,8 +167,6 @@ void ScheduleDAG::BuildSchedUnits() {
     if (MainNode->isTargetOpcode()) {
       unsigned Opc = MainNode->getTargetOpcode();
       const TargetInstrDescriptor &TID = TII->get(Opc);
-      if (TID.ImplicitDefs)
-        SU->hasImplicitDefs = true;
       for (unsigned i = 0; i != TID.numOperands; ++i) {
         if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
           SU->isTwoAddress = true;
@@ -185,8 +183,10 @@ void ScheduleDAG::BuildSchedUnits() {
     
     for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
       SDNode *N = SU->FlaggedNodes[n];
-      if (N->isTargetOpcode() && TII->getImplicitDefs(N->getTargetOpcode()))
-        SU->hasImplicitDefs = true;
+      if (N->isTargetOpcode() &&
+          TII->getImplicitDefs(N->getTargetOpcode()) &&
+          CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode()))
+        SU->hasPhysRegDefs = true;
       
       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
         SDNode *OpN = N->getOperand(i).Val;

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 92dbb7cfd0dc4abac88096a4f0420a7a9d2daca7..ff751a944413459ff6bc864e3339467fe3a76f56 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1144,10 +1144,26 @@ bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
 }
 
 
+/// hasCopyToRegUse - Return true if SU has a value successor that is a
+/// CopyToReg node.
+static bool hasCopyToRegUse(SUnit *SU) {
+  for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
+       I != E; ++I) {
+    if (I->isCtrl) continue;
+    SUnit *SuccSU = I->Dep;
+    if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg)
+      return true;
+  }
+  return false;
+}
+
 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
 /// it as a def&use operand. Add a pseudo control edge from it to the other
 /// node (if it won't create a cycle) so the two-address one will be scheduled
-/// first (lower in the schedule).
+/// first (lower in the schedule). If both nodes are two-address, favor the
+/// one that has a CopyToReg use (more likely to be a loop induction update).
+/// If both are two-address, but one is commutable while the other is not
+/// commutable, favor the one that's not commutable.
 template<class SF>
 void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
   for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
@@ -1156,7 +1172,7 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
       continue;
 
     SDNode *Node = SU->Node;
-    if (!Node || !Node->isTargetOpcode())
+    if (!Node || !Node->isTargetOpcode() || SU->FlaggedNodes.size() > 0)
       continue;
 
     unsigned Opc = Node->getTargetOpcode();
@@ -1173,12 +1189,13 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
           SUnit *SuccSU = I->Dep;
           // Don't constraint nodes with implicit defs. It can create cycles
           // plus it may increase register pressures.
-          if (SuccSU == SU || SuccSU->hasImplicitDefs)
+          if (SuccSU == SU || SuccSU->hasPhysRegDefs)
             continue;
           // Be conservative. Ignore if nodes aren't at the same depth.
           if (SuccSU->Depth != SU->Depth)
             continue;
           if ((!canClobber(SuccSU, DUSU) ||
+               (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
                (!SU->isCommutable && SuccSU->isCommutable)) &&
               !isReachable(SuccSU, SU)) {
             DOUT << "Adding an edge from SU # " << SU->NodeNum