fold sext_in_reg, sext_in_reg where both have the same VT. This was

popping up in Fourinarow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23722 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4997dba4680ca03a67aa1dec56ca670f54345c43..879dc5b36f7e67be1d525d82c3183e05e72e8ccf 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1330,7 +1330,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   }
   // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
   if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 
-      cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) {
+      cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
     return N0;
   }
   // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2