}
}
} else if (const Operator *Op = dyn_cast<Operator>(V)) {
- if (!SelectOperator(Op, Op->getOpcode())) return 0;
+ if (!SelectOperator(Op, Op->getOpcode()))
+ if (!isa<Instruction>(Op) ||
+ !TargetSelectInstruction(cast<Instruction>(Op)))
+ return 0;
Reg = lookUpRegForValue(Op);
} else if (isa<UndefValue>(V)) {
Reg = createResultReg(TLI.getRegClassFor(VT));
FastIS->startNewBlock(BB);
// Do FastISel on as many instructions as possible.
for (; BI != End; ++BI) {
+ // Defer instructions with no side effects; they'll be emitted
+ // on-demand later.
+ if (BI->isSafeToSpeculativelyExecute() &&
+ !FuncInfo->ValueMap.count(BI))
+ continue;
+
// Try to select the instruction with FastISel.
if (FastIS->SelectInstruction(BI))
continue;
if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
const MachineInstr *SetMI = 0;
- unsigned Reg = lookUpRegForValue(EI);
+ unsigned Reg = getRegForValue(EI);
for (MachineBasicBlock::const_reverse_iterator
RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %eax}
; PR3242
-define i32 @foo(i32 %x) nounwind {
+define void @foo(i32 %x, i32* %p) nounwind {
%y = ashr i32 %x, 50000
- ret i32 %y
+ store i32 %y, i32* %p
+ ret void
}