Remove isImplicitDef TargetInstrDesc flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h
index 16142c656aae0e620e3c1f19b60425a70ca81014..5d31a00dd33758d6444e3aeab8033d5f122c3c50 100644 (file)
--- a/include/llvm/Target/TargetInstrDesc.h
+++ b/include/llvm/Target/TargetInstrDesc.h
@@ -81,7 +81,6 @@ namespace TID {
     HasOptionalDef,
     Return,
     Call,
-    ImplicitDef,
     Barrier,
     Terminator,
     Branch,
@@ -219,13 +218,6 @@ public:
     return Flags & (1 << TID::Call);
   }
   
-  /// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
-  /// which defines a register to an unspecified value.  These basically
-  /// correspond to x = undef.
-  bool isImplicitDef() const {
-    return Flags & (1 << TID::ImplicitDef);
-  }
-  
   /// isBarrier - Returns true if the specified instruction stops control flow
   /// from executing the instruction immediately following it.  Examples include
   /// unconditional branches and return instructions.

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index d7c5544c366f6a3a6a3d32ec1ff10b9bfd8ba624..3dde8195a44d108e9e85009744db7fce2e35e73d 100644 (file)
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -641,8 +641,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
     return false;
 
   isLoad = false;
-  const TargetInstrDesc &TID = MI->getDesc();
-  if (TID.isImplicitDef())
+  if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
     return true;
 
   int FrameIdx = 0;
@@ -655,6 +654,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
     return true;
 
   if (tii_->isTriviallyReMaterializable(MI)) {
+    const TargetInstrDesc &TID = MI->getDesc();
     isLoad = TID.isSimpleLoad();
 
     unsigned ImpUse = getReMatImplicitUse(li, MI);
@@ -741,9 +741,8 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
                                          unsigned InstrIdx,
                                          SmallVector<unsigned, 2> &Ops,
                                          bool isSS, int Slot, unsigned Reg) {
-  const TargetInstrDesc &TID = MI->getDesc();
   // If it is an implicit def instruction, just delete it.
-  if (TID.isImplicitDef()) {
+  if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
     RemoveMachineInstrFromMaps(MI);
     vrm.RemoveMachineInstrFromMaps(MI);
     MI->eraseFromParent();

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index d7f1e38c118c181721feccd398edec72dc582f94..9d49bd2185d095558370a4891d022458e0c88e0c 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -193,7 +193,6 @@ class Instruction {
   bit isSimpleLoad = 0;     // Is this just a load instruction?
   bit mayLoad      = 0;     // Is it possible for this inst to read memory?
   bit mayStore     = 0;     // Is it possible for this inst to write memory?
-  bit isImplicitDef = 0;    // Is this instruction an implicit def instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?

diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index 8b70647907743ba3ae615d86c249fa34c81f792c..53daf9d94463bb0bae3b9cae756c31fe3a5c5bca 100644 (file)
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -86,7 +86,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   isSimpleLoad = R->getValueAsBit("isSimpleLoad");
   mayLoad      = R->getValueAsBit("mayLoad");
   mayStore     = R->getValueAsBit("mayStore");
-  isImplicitDef= R->getValueAsBit("isImplicitDef");
   bool isTwoAddress = R->getValueAsBit("isTwoAddress");
   isPredicable = R->getValueAsBit("isPredicable");
   isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");

diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index ad076a2074ed3d2818e14a661fdda6eeacc5ecc7..9bfd4323f914e5d376617c4aba149b56c2eeb1c2 100644 (file)
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -91,7 +91,6 @@ namespace llvm {
     bool isCall;
     bool isSimpleLoad;
     bool mayLoad, mayStore;
-    bool isImplicitDef;
     bool isPredicable;
     bool isConvertibleToThreeAddress;
     bool isCommutable;

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 2ac76349d70049834f3ad0d32a95c7da8c6147d3..d765152d23aeae5dee73f2ec7795fc329e64eee1 100644 (file)
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -346,7 +346,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
   if (mayLoad)           OS << "|(1<<TID::MayLoad)";
   if (mayStore)          OS << "|(1<<TID::MayStore)";
-  if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
   if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
   if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
   if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";