HasOptionalDef,
Return,
Call,
- ImplicitDef,
Barrier,
Terminator,
Branch,
return Flags & (1 << TID::Call);
}
- /// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
- /// which defines a register to an unspecified value. These basically
- /// correspond to x = undef.
- bool isImplicitDef() const {
- return Flags & (1 << TID::ImplicitDef);
- }
-
/// isBarrier - Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it. Examples include
/// unconditional branches and return instructions.
return false;
isLoad = false;
- const TargetInstrDesc &TID = MI->getDesc();
- if (TID.isImplicitDef())
+ if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
return true;
int FrameIdx = 0;
return true;
if (tii_->isTriviallyReMaterializable(MI)) {
+ const TargetInstrDesc &TID = MI->getDesc();
isLoad = TID.isSimpleLoad();
unsigned ImpUse = getReMatImplicitUse(li, MI);
unsigned InstrIdx,
SmallVector<unsigned, 2> &Ops,
bool isSS, int Slot, unsigned Reg) {
- const TargetInstrDesc &TID = MI->getDesc();
// If it is an implicit def instruction, just delete it.
- if (TID.isImplicitDef()) {
+ if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
RemoveMachineInstrFromMaps(MI);
vrm.RemoveMachineInstrFromMaps(MI);
MI->eraseFromParent();
bit isSimpleLoad = 0; // Is this just a load instruction?
bit mayLoad = 0; // Is it possible for this inst to read memory?
bit mayStore = 0; // Is it possible for this inst to write memory?
- bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
bit isTwoAddress = 0; // Is this a two address instruction?
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
isSimpleLoad = R->getValueAsBit("isSimpleLoad");
mayLoad = R->getValueAsBit("mayLoad");
mayStore = R->getValueAsBit("mayStore");
- isImplicitDef= R->getValueAsBit("isImplicitDef");
bool isTwoAddress = R->getValueAsBit("isTwoAddress");
isPredicable = R->getValueAsBit("isPredicable");
isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
bool isCall;
bool isSimpleLoad;
bool mayLoad, mayStore;
- bool isImplicitDef;
bool isPredicable;
bool isConvertibleToThreeAddress;
bool isCommutable;
if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
if (mayLoad) OS << "|(1<<TID::MayLoad)";
if (mayStore) OS << "|(1<<TID::MayStore)";
- if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";