Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138760 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 56a4d831e165678fcfd27d6fdafce1b483d1f2f7..523f7393b0436f8a7e671070248494faede6b9a4 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1507,6 +1507,7 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
     let Inst{19-16} = shift{16-13}; // Rn
     let Inst{15-12} = 0b1111;
     let Inst{11-0}  = shift{11-0};
+    let Inst{4} = 0;
   }
 }