MI Sched fix: assert "Disconnected LRG within the scheduling region."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187435 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index 4e3cc3c5d4f61d6af7b5cbad3f1aa9a1c8587107..b088d1ad17c17a4ea10b5ff1200a2c741cd56c9f 100644 (file)
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -1017,6 +1017,12 @@ void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG) {
                                GlobalSegment->start)) {
       return;
     }
+    // If the prior global segment may be defined by the same two-address
+    // instruction that also defines LocalLI, then can't make a hole here.
+    if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->start,
+                               LocalLI->beginIndex())) {
+      return;
+    }
     // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
     // it would be a disconnected component in the live range.
     assert(llvm::prior(GlobalSegment)->start < LocalLI->beginIndex() &&

diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll
index 4b15326008a43f97b226d7cd43b2892d173eeca1..6445b4a3a7f5217b79613020fee25367d757b12b 100644 (file)
--- a/test/CodeGen/ARM/misched-copy-arm.ll
+++ b/test/CodeGen/ARM/misched-copy-arm.ll
@@ -1,5 +1,5 @@
 ; REQUIRES: asserts
-; RUN: llc < %s -march=thumb -mcpu=swift -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -march=thumb -mcpu=swift -pre-RA-sched=source -join-globalcopies -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
 ;
 ; Loop counter copies should be eliminated.
 ; There is also a MUL here, but we don't care where it is scheduled.
@@ -28,3 +28,56 @@ for.end:                                          ; preds = %for.body, %entry
   %s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ]
   ret i32 %s.0.lcssa
 }
+
+
+; This case was a crasher in constrainLocalCopy.
+; The problem was the t2LDR_PRE defining both the global and local lrg.
+; CHECK-LABEL: *** Final schedule for BB#5 ***
+; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>, 4
+; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]]
+; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
+; CHECK-LABEL: MACHINEINSTRS
+%struct.rtx_def = type { [4 x i8], [1 x %union.rtunion_def] }
+%union.rtunion_def = type { i64 }
+
+; Function Attrs: nounwind ssp
+declare hidden fastcc void @df_ref_record(i32* nocapture, %struct.rtx_def*, %struct.rtx_def**, %struct.rtx_def*, i32, i32) #0
+
+; Function Attrs: nounwind ssp
+define hidden fastcc void @df_def_record_1(i32* nocapture %df, %struct.rtx_def* %x, %struct.rtx_def* %insn) #0 {
+entry:
+  br label %while.cond
+
+while.cond:                                       ; preds = %if.end28, %entry
+  %loc.0 = phi %struct.rtx_def** [ %rtx31, %if.end28 ], [ undef, %entry ]
+  %dst.0 = phi %struct.rtx_def* [ %0, %if.end28 ], [ undef, %entry ]
+  switch i32 undef, label %if.end47 [
+    i32 61, label %if.then46
+    i32 64, label %if.then24
+    i32 132, label %if.end28
+    i32 133, label %if.end28
+  ]
+
+if.then24:                                        ; preds = %while.cond
+  br label %if.end28
+
+if.end28:                                         ; preds = %if.then24, %while.cond, %while.cond
+  %dst.1 = phi %struct.rtx_def* [ undef, %if.then24 ], [ %dst.0, %while.cond ], [ %dst.0, %while.cond ]
+  %arrayidx30 = getelementptr inbounds %struct.rtx_def* %dst.1, i32 0, i32 1, i32 0
+  %rtx31 = bitcast %union.rtunion_def* %arrayidx30 to %struct.rtx_def**
+  %0 = load %struct.rtx_def** %rtx31, align 4, !tbaa !0
+  br label %while.cond
+
+if.then46:                                        ; preds = %while.cond
+  tail call fastcc void @df_ref_record(i32* %df, %struct.rtx_def* %dst.0, %struct.rtx_def** %loc.0, %struct.rtx_def* %insn, i32 0, i32 undef)
+  unreachable
+
+if.end47:                                         ; preds = %while.cond
+  ret void
+}
+
+attributes #0 = { nounwind ssp }
+
+!0 = metadata !{metadata !"any pointer", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}