arm and carve out a place ot mention segmented stacks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145204 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html
index f7c3edefb3659573767525d37e79cdfa76bb3f83..b1b1e14f865619fd0401243025d55f46ea1a39ce 100644 (file)
--- a/docs/ReleaseNotes.html
+++ b/docs/ReleaseNotes.html
@@ -929,6 +929,7 @@ be used to verify some algorithms.
    make it run faster:</p>
 
 <ul>
+<li>XXX: Segmented stacks.</li>
 <li>LLVM generates substantially better code for indirect gotos due to a new
     tail duplication pass, which can be a substantial performance win for
     interpreter loops that use them.</li>
@@ -991,15 +992,15 @@ be used to verify some algorithms.
 <p>New features of the ARM target include:</p>
 
 <ul>
-  <li>Reworked Set Jump Long Jump EH Lowering,</li>
-  <li>improved support for Cortex-M series processors, and</li>
-  <li>beta quality integrated assembler support.</li>
-  
-  Better code generation for Cortex-A9
-  ARM inline asm constraints implemented.
-  Old arm disassembler replaced with a new one based on autogenerated encoding information from ARM .td files.
-  Better performance for Neon code in clang due to SRoA improvements.
-
+<li>The ARM backend generates much faster code for Cortex-A9 chips.</li>
+<li>The ARM backend has improved support for Cortex-M series processors.</li>
+<li>The ARM inline assembly constraints have been implemented and are now fully
+    supported.</li>
+<li>NEON code produced by Clang often runs much faster due to improvements in
+    the Scalar Replacement of Aggregates pass.</li>
+<li>The old ARM disassembler is replaced with a new one based on autogenerated
+    encoding information from ARM .td files.</li>
+<li>The integrated assembler has made major leaps forward, but is still beta quality in LLVM 3.0.</li>
 </ul>
 </div>
 
@@ -1011,7 +1012,8 @@ be used to verify some algorithms.
 
 <div>
 
-<p>New features and major changes in the MIPS target include:</p>
+<p>This release has seen major new work on just about every aspect of the MIPS
+  backend.  Some of the major new features include:</p>
 
 <ul>
   <li>Most MIPS32r1 and r2 instructions are now supported.</li>