: T2I<(outs), (ins), NoItinerary, opc, asm,
[/* For disassembly only; pattern left blank */]> {
let Inst{31-20} = 0xf3a;
+ let Inst{19-16} = 0b1111;
let Inst{15-14} = 0b10;
let Inst{12} = 0;
let Inst{10-8} = 0b000;
@ CHECK: qdsub r1, r2, r3 @ encoding: [0x52,0x10,0x63,0xe1]
qdsub r1, r2, r3
+
+@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
+ wfe
+
+@ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3]
+ wfi
+
+@ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3]
+ yield
+
+@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3]
+ nop
@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xee,0x81,0x17]
cdp p7, #1, c1, c1, c1, #4
+@ CHECK: nop @ encoding: [0x00,0xbf]
+ nop
+
+@ CHECK: yield @ encoding: [0x10,0xbf]
+ yield
+
+@ CHECK: wfe @ encoding: [0x20,0xbf]
+ wfe
+
+@ CHECK: wfi @ encoding: [0x30,0xbf]
+ wfi
@ CHECK: qdsub r1, r2, r3 @ encoding: [0x83,0xfa,0xb2,0xf1]
qdsub r1, r2, r3
+
+@ CHECK: nop.w @ encoding: [0xaf,0xf3,0x00,0x80]
+ nop.w
+
+@ CHECK: yield.w @ encoding: [0xaf,0xf3,0x01,0x80]
+ yield.w
+
+@ CHECK: wfe.w @ encoding: [0xaf,0xf3,0x02,0x80]
+ wfe.w
+
+@ CHECK: wfi.w @ encoding: [0xaf,0xf3,0x03,0x80]
+ wfi.w
+