ARM: mvebu: Low level function to disable HW coherency support

When going to deep idle we need to disable the SoC snooping (aka
hardware coherency support). Playing with the coherency fabric
requires to use assembly code to be sure that the compiler doesn't
reorder the instructions nor do wrong optimization.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-7-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index f2e2e8677c4b05a0d800f8e9dff69172aac63a71..6828f9f157b0b36d02abb6daab4843c143d2bf4d 100644 (file)
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -102,6 +102,26 @@ ENTRY(ll_enable_coherency)
        mov     pc, lr
 ENDPROC(ll_enable_coherency)
 
+ENTRY(ll_disable_coherency)
+       /*
+        * r0 being untouched in ll_get_coherency_base and
+        * ll_get_cpuid, we can use it to save lr modifing it with the
+        * following bl
+        */
+       mov r0, lr
+       bl      ll_get_coherency_base
+       bl      ll_get_cpuid
+       mov lr, r0
+       add     r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
+1:
+       ldrex   r2, [r0]
+       bic     r2, r2, r3
+       strex   r1, r2, [r0]
+       cmp     r1, #0
+       bne     1b
+       dsb
+       mov     pc, lr
+ENDPROC(ll_disable_coherency)
 
        .align 2
 3: