Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i1...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147337 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 9f309142793c6d103676e7292c25d02a3f551829..a723f0a2dc72611d68e42512defbc1796dde079b 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5182,17 +5182,16 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
 
       if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
         Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
+        Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
         if (VT.getSizeInBits() == 256) {
-          EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2);
-          Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item);
-          SDValue ZeroVec = getZeroVector(VT, true, DAG, dl);
-          return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
-                              DAG, dl);
+          SDValue ZeroVec = getZeroVector(MVT::v8i32, true, DAG, dl);
+          Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
+                                    DAG, dl);
+        } else {
+          assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
+          Item = getShuffleVectorZeroOrUndef(Item, 0, true,
+                                             Subtarget->hasXMMInt(), DAG);
         }
-        assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
-        Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
-        Item = getShuffleVectorZeroOrUndef(Item, 0, true,
-                                           Subtarget->hasXMMInt(), DAG);
         return DAG.getNode(ISD::BITCAST, dl, VT, Item);
       }
     }