Only insert an AND when converting from BR_COND to BRCC if needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25832 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 79037d3020f52aac22a557fae3b0eb946f9cfbc9..f09fa625006adf489be6232f421ec06396a3ee63 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -703,7 +703,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       } else {
         // Make sure the condition is either zero or one.  It may have been
         // promoted from something else.
-        Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
+        unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
+        if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
+          Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
         
         Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 
                              DAG.getCondCode(ISD::SETNE), Tmp2,