LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.

The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16.  Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 78d73d3a272b41e2d24d1fc0af4bc6b1597aa9fb..54b13dc21a575072f03acc59b42f7e7850e8b224 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -94,6 +94,9 @@ static unsigned decodeARMInstruction(uint32_t &insn) {
   // As a result, the decoder fails to deocode USAT properly.
   if (slice(insn, 27, 21) == 0x37 && slice(insn, 5, 4) == 1)
     return ARM::USAT;
+  // As a result, the decoder fails to deocode UQADD16 properly.
+  if (slice(insn, 27, 20) == 0x66 && slice(insn, 7, 4) == 1)
+    return ARM::UQADD16;
 
   // Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8.
   // As a result, the decoder fails to decode UMULL properly.

diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index d707565894b4c4f9e437d7326726c191b7e661cd..5d804745419e225442bad1ab02a210870dec5143 100644 (file)
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -139,3 +139,6 @@
 
 # CHECK: bx r12
 0x1c 0xff 0x2f 0xe1
+
+# CHECK:       uqadd16mi       r6, r11, r8
+0x18 0x60 0x6b 0x46