ARM: dt: tegra114: Add new SoC base, Tegra114 SoC
authorHiroshi Doyu <hdoyu@nvidia.com>
Thu, 24 Jan 2013 01:10:23 +0000 (01:10 +0000)
committerStephen Warren <swarren@nvidia.com>
Mon, 28 Jan 2013 18:23:05 +0000 (11:23 -0700)
Initial support for Tegra 114 SoC. This is expected to be included in
the board DTS files, Tegra 114 SoC based evaluation board family.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/boot/dts/tegra114.dtsi [new file with mode: 0644]

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
new file mode 100644 (file)
index 0000000..c567916
--- /dev/null
@@ -0,0 +1,114 @@
+/include/ "skeleton.dtsi"
+
+/ {
+       compatible = "nvidia,tegra114";
+       interrupt-parent = <&gic>;
+
+       gic: interrupt-controller {
+               compatible = "arm,cortex-a15-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0x50041000 0x1000>,
+                     <0x50042000 0x1000>,
+                     <0x50044000 0x2000>,
+                     <0x50046000 0x2000>;
+               interrupts = <1 9 0xf04>;
+       };
+
+       timer@60005000 {
+               compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
+               reg = <0x60005000 0x400>;
+               interrupts = <0 0 0x04
+                             0 1 0x04
+                             0 41 0x04
+                             0 42 0x04
+                             0 121 0x04
+                             0 122 0x04>;
+       };
+
+       tegra_car: clock {
+               compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+               reg = <0x60006000 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       serial@70006000 {
+               compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+               reg = <0x70006000 0x40>;
+               reg-shift = <2>;
+               interrupts = <0 36 0x04>;
+               status = "disabled";
+       };
+
+       serial@70006040 {
+               compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+               reg = <0x70006040 0x40>;
+               reg-shift = <2>;
+               interrupts = <0 37 0x04>;
+               status = "disabled";
+       };
+
+       serial@70006200 {
+               compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+               reg = <0x70006200 0x100>;
+               reg-shift = <2>;
+               interrupts = <0 46 0x04>;
+               status = "disabled";
+       };
+
+       serial@70006300 {
+               compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+               reg = <0x70006300 0x100>;
+               reg-shift = <2>;
+               interrupts = <0 90 0x04>;
+               status = "disabled";
+       };
+
+       rtc {
+               compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
+               reg = <0x7000e000 0x100>;
+               interrupts = <0 2 0x04>;
+       };
+
+       pmc {
+               compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
+               reg = <0x7000e400 0x400>;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <1>;
+               };
+
+               cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <2>;
+               };
+
+               cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <3>;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <1 13 0xf08>,
+                            <1 14 0xf08>,
+                            <1 11 0xf08>,
+                            <1 10 0xf08>;
+       };
+};