Add MULHU and MULHS nodes for the high part of an (un)signed 32x32=64b

multiply.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21102 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 568f66c9f633970e2f355df815e3847b6dfd7223..cdb84eef4725858fb84cc12ebb4c4038128d5f41 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -90,7 +90,7 @@ namespace ISD {
 
 
     // Simple binary arithmetic operators.
-    ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
+    ADD, SUB, MUL, MULHU, MULHS, SDIV, UDIV, SREM, UREM,
 
     // Bitwise operators.
     AND, OR, XOR, SHL, SRA, SRL,

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 105d39d1fa59e68bb3f3596cafd1097e97f7f232..858b8ddab8eb7534e564f26e165726246c972377 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1130,6 +1130,8 @@ const char *SDNode::getOperationName() const {
   case ISD::ADD:    return "add";
   case ISD::SUB:    return "sub";
   case ISD::MUL:    return "mul";
+  case ISD::MULHU:  return "mulhu";
+  case ISD::MULHS:  return "mulhs";
   case ISD::SDIV:   return "sdiv";
   case ISD::UDIV:   return "udiv";
   case ISD::SREM:   return "srem";