#include <asm/mach/arch.h>
#include <linux/interrupt.h>
#include "generic.h"
-#include <asm/serial.h>
static struct resource cs89x0_resources[] = {
[0] = {
uart.type = PORT_UNKNOWN;
uart.uartclk = 18432000;
uart.irq = COBALT_SERIAL_IRQ;
- uart.flags = STD_COM_FLAGS;
+ uart.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
uart.iobase = 0xc800000;
uart.iotype = UPIO_PORT;
memset(&s, 0, sizeof(s));
- s.flags = STD_COM_FLAGS;
- s.iotype = SERIAL_IO_MEM;
+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
+ s.iotype = UPIO_MEM;
if (mips_machtype == MACH_LASAT_100) {
s.uartclk = LASAT_BASE_BAUD_100 * 16;
#endif
s.irq = ATLASINT_UART;
s.uartclk = ATLAS_BASE_BAUD * 16;
- s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ;
- s.iotype = SERIAL_IO_PORT;
+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ;
+ s.iotype = UPIO_PORT;
s.regshift = 3;
if (early_serial_setup(&s) != 0) {
#endif
s.irq = MIPSCPU_INT_BASE + MIPSCPU_INT_UART0;
s.uartclk = SEAD_BASE_BAUD * 16;
- s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ;
- s.iotype = 0;
+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ;
+ s.iotype = UPIO_PORT;
s.regshift = 3;
if (early_serial_setup(&s) != 0) {
but poll for now */
s.irq = 0;
s.uartclk = BASE_BAUD * 16;
- s.flags = ASYNC_BOOT_AUTOCONF | UPF_SKIP_TEST;
- s.iotype = SERIAL_IO_PORT | ASYNC_SKIP_TEST;
+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
+ s.iotype = UPIO_PORT;
s.regshift = 0;
s.timeout = 4;
up.uartclk = JAGUAR_ATX_UART_CLK;
up.regshift = 2;
up.iotype = UPIO_MEM;
- up.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
up.line = 0;
if (early_serial_setup(&up))
[0] = {
.port = {
.type = PORT_IP3106,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.membase = (void __iomem *)PNX8550_UART_PORT0,
.mapbase = PNX8550_UART_PORT0,
.irq = PNX8550_UART_INT(0),
.uartclk = 3692300,
.fifosize = 16,
.ops = &ip3106_pops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
},
[1] = {
.port = {
.type = PORT_IP3106,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.membase = (void __iomem *)PNX8550_UART_PORT1,
.mapbase = PNX8550_UART_PORT1,
.irq = PNX8550_UART_INT(1),
.uartclk = 3692300,
.fifosize = 16,
.ops = &ip3106_pops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
},
up.uartclk = TITAN_UART_CLK;
up.regshift = 0;
up.iotype = UPIO_MEM;
- up.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
up.line = 0;
if (early_serial_setup(&up))
#include <linux/tty.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
-extern int early_serial_setup(struct uart_port *port);
-
-#define STD_COM_FLAGS (ASYNC_SKIP_TEST)
-#define BASE_BAUD (1843200 / 16)
-
#endif /* CONFIG_SERIAL_8250 */
/* An arbitrary time; this can be decreased if reliability looks good */
o2_serial[0].type = PORT_16550A;
o2_serial[0].line = 0;
o2_serial[0].irq = MACEISA_SERIAL1_IRQ;
- o2_serial[0].flags = STD_COM_FLAGS;
- o2_serial[0].uartclk = BASE_BAUD * 16;
+ o2_serial[0].flags = UPF_SKIP_TEST;
+ o2_serial[0].uartclk = 1843200;
o2_serial[0].iotype = UPIO_MEM;
o2_serial[0].membase = (char *)&mace->isa.serial1;
o2_serial[0].fifosize = 14;
o2_serial[1].type = PORT_16550A;
o2_serial[1].line = 1;
o2_serial[1].irq = MACEISA_SERIAL2_IRQ;
- o2_serial[1].flags = STD_COM_FLAGS;
- o2_serial[1].uartclk = BASE_BAUD * 16;
+ o2_serial[1].flags = UPF_SKIP_TEST;
+ o2_serial[1].uartclk = 1843200;
o2_serial[1].iotype = UPIO_MEM;
o2_serial[1].membase = (char *)&mace->isa.serial2;
o2_serial[1].fifosize = 14;
port.irq = 0;
port.uartclk = clocks.uart0;
port.regshift = 0;
- port.iotype = SERIAL_IO_MEM;
- port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.iotype = UPIO_MEM;
+ port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
port.irq = ACTING_UART0_INT;
port.uartclk = uart_clock;
port.regshift = 0;
- port.iotype = SERIAL_IO_MEM;
- port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.iotype = UPIO_MEM;
+ port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
port.irq = 0;
port.uartclk = clocks.uart0;
port.regshift = 0;
- port.iotype = SERIAL_IO_MEM;
- port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.iotype = UPIO_MEM;
+ port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
port.irq = UART0_INT;
port.uartclk = clocks.uart0;
port.regshift = 0;
- port.iotype = SERIAL_IO_MEM;
- port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.iotype = UPIO_MEM;
+ port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
port.irq = UART0_INT;
port.uartclk = clocks.uart0;
port.regshift = 0;
- port.iotype = SERIAL_IO_MEM;
- port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.iotype = UPIO_MEM;
+ port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
port.irq = old_ports[i].irq;
port.uartclk = old_ports[i].baud_base * 16;
port.regshift = old_ports[i].iomem_reg_shift;
- port.iotype = SERIAL_IO_MEM;
- port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.iotype = UPIO_MEM;
+ port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = i;
if (early_serial_setup(&port) != 0) {
port.irq = UART0_INT;
port.uartclk = clocks.uart0;
port.regshift = 0;
- port.iotype = SERIAL_IO_MEM;
- port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.iotype = UPIO_MEM;
+ port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
struct uart_port p;
memset(&p, 0, sizeof (p));
- p.iotype = SERIAL_IO_MEM;
+ p.iotype = UPIO_MEM;
p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4500);
p.uartclk = binfo->bi_busfreq;
gen550_init(0, &p);
memset(&p, 0, sizeof (p));
- p.iotype = SERIAL_IO_MEM;
+ p.iotype = UPIO_MEM;
p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4600);
p.uartclk = binfo->bi_busfreq;
binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
memset(&p, 0, sizeof (p));
- p.iotype = SERIAL_IO_MEM;
+ p.iotype = UPIO_MEM;
p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
p.uartclk = binfo->bi_busfreq;
gen550_init(0, &p);
memset(&p, 0, sizeof (p));
- p.iotype = SERIAL_IO_MEM;
+ p.iotype = UPIO_MEM;
p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
p.uartclk = binfo->bi_busfreq;
binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
memset(&p, 0, sizeof (p));
- p.iotype = SERIAL_IO_MEM;
+ p.iotype = UPIO_MEM;
p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
p.uartclk = binfo->bi_busfreq;
gen550_init(0, &p);
memset(&p, 0, sizeof (p));
- p.iotype = SERIAL_IO_MEM;
+ p.iotype = UPIO_MEM;
p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
p.uartclk = binfo->bi_busfreq;
uart_req.irq = MPC85xx_IRQ_EXT9;
uart_req.flags = STD_COM_FLAGS;
uart_req.uartclk = BASE_BAUD * 16;
- uart_req.iotype = SERIAL_IO_MEM;
+ uart_req.iotype = UPIO_MEM;
uart_req.mapbase = UARTA_ADDR;
uart_req.membase = ioremap(uart_req.mapbase, MPC85xx_UART0_SIZE);
uart_req.type = PORT_16650;
binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
memset(&p, 0, sizeof (p));
- p.iotype = SERIAL_IO_MEM;
+ p.iotype = UPIO_MEM;
p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
p.uartclk = binfo->bi_busfreq;
gen550_init(0, &p);
memset(&p, 0, sizeof (p));
- p.iotype = SERIAL_IO_MEM;
+ p.iotype = UPIO_MEM;
p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
p.uartclk = binfo->bi_busfreq;
port.uartclk = BASE_BAUD * 16;
port.irq = UART0_INT;
port.flags = STD_COM_FLAGS | UPF_IOREMAP;
- port.iotype = SERIAL_IO_MEM;
+ port.iotype = UPIO_MEM;
port.mapbase = CHESTNUT_UART0_IO_BASE;
port.regshift = 0;
port.irq = EV64260_UART_0_IRQ;
port.uartclk = BASE_BAUD * 16;
port.regshift = 2;
- port.iotype = SERIAL_IO_MEM;
+ port.iotype = UPIO_MEM;
port.flags = STD_COM_FLAGS;
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
serial_req.uartclk = UART_CLK;
serial_req.irq = 4;
serial_req.flags = STD_COM_FLAGS;
- serial_req.iotype = SERIAL_IO_MEM;
+ serial_req.iotype = UPIO_MEM;
serial_req.membase = (u_char *) PPC7D_SERIAL_0;
gen550_init(0, &serial_req);
memset(&serial_req, 0, sizeof(serial_req));
serial_req.uartclk = uart_clk;
serial_req.irq = UART0_INT;
- serial_req.flags = ASYNC_BOOT_AUTOCONF;
- serial_req.iotype = SERIAL_IO_MEM;
+ serial_req.flags = UPF_BOOT_AUTOCONF;
+ serial_req.iotype = UPIO_MEM;
serial_req.membase = (u_char *)UART0_IO_BASE;
serial_req.regshift = 0;
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
memset(&serial_req, 0, sizeof (serial_req));
- serial_req.iotype = SERIAL_IO_MEM;
+ serial_req.iotype = UPIO_MEM;
serial_req.mapbase = pdata[0].mapbase;
serial_req.membase = pdata[0].membase;
serial_req.regshift = 0;
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
memset(&serial_req, 0, sizeof (serial_req));
- serial_req.iotype = SERIAL_IO_MEM;
+ serial_req.iotype = UPIO_MEM;
serial_req.mapbase = pdata[0].mapbase;
serial_req.membase = pdata[0].membase;
serial_req.regshift = 0;
static struct uart_port serial21285_port = {
.mapbase = 0x42000160,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = NO_IRQ,
.fifosize = 16,
.ops = &serial21285_ops,
* and restore the IER
*/
wait_for_xmitr(up, BOTH_EMPTY);
+ up->ier |= UART_IER_THRI;
serial_out(up, UART_IER, ier | UART_IER_THRI);
}
#elif defined(CONFIG_SOC_AU1550)
PORT(UART0_ADDR, AU1550_UART0_INT),
PORT(UART1_ADDR, AU1550_UART1_INT),
- PORT(UART2_ADDR, AU1550_UART2_INT),
PORT(UART3_ADDR, AU1550_UART3_INT),
#elif defined(CONFIG_SOC_AU1200)
PORT(UART0_ADDR, AU1200_UART0_INT),
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
pbn_b0_4_1843200 },
+ { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+ PCI_VENDOR_ID_AFAVLAB,
+ PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
+ pbn_b0_4_1152000 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
.port = {
.membase = (void *)IO_ADDRESS(INTEGRATOR_UART0_BASE),
.mapbase = INTEGRATOR_UART0_BASE,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = IRQ_UARTINT0,
.uartclk = 14745600,
.fifosize = 16,
.port = {
.membase = (void *)IO_ADDRESS(INTEGRATOR_UART1_BASE),
.mapbase = INTEGRATOR_UART1_BASE,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = IRQ_UARTINT1,
.uartclk = 14745600,
.fifosize = 16,
int ret = 0;
switch (up->port.iotype) {
- case SERIAL_IO_MEM:
+ case UPIO_MEM:
if (up->port.mapbase) {
*res = request_mem_region(up->port.mapbase, size, "serial");
if (!*res)
}
break;
- case SERIAL_IO_HUB6:
- case SERIAL_IO_PORT:
+ case UPIO_HUB6:
+ case UPIO_PORT:
*res = request_region(up->port.iobase, size, "serial");
if (!*res)
ret = -EBUSY;
size <<= up->port.regshift;
switch (up->port.iotype) {
- case SERIAL_IO_MEM:
+ case UPIO_MEM:
if (up->port.mapbase) {
/*
* Unmap the area.
}
break;
- case SERIAL_IO_HUB6:
- case SERIAL_IO_PORT:
+ case UPIO_HUB6:
+ case UPIO_PORT:
start = up->port.iobase;
if (size)
/* If we have not enough room in tty flip buffer, then we try
* later, which will be the next rx-interrupt or a timeout
*/
- if ((tty->flip.count + i) >= TTY_FLIPBUF_SIZE) {
- tty->flip.work.func((void *)tty);
- if ((tty->flip.count + i) >= TTY_FLIPBUF_SIZE) {
- printk(KERN_WARNING "TTY_DONT_FLIP set\n");
- return;
- }
+ if(tty_buffer_request_room(tty, i) < i) {
+ printk(KERN_WARNING "No room in flip buffer\n");
+ return;
}
/* get pointer */
continue;
error_return:
- *tty->flip.char_buf_ptr++ = ch;
- *tty->flip.flag_buf_ptr++ = flg;
- tty->flip.count++;
+ tty_insert_flip_char(tty, ch, flg);
} /* End while (i--) */
.port = {
.irq = SMC1_IRQ,
.ops = &cpm_uart_pops,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.lock = SPIN_LOCK_UNLOCKED,
},
.flags = FLAG_SMC,
.port = {
.irq = SMC2_IRQ,
.ops = &cpm_uart_pops,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.lock = SPIN_LOCK_UNLOCKED,
},
.flags = FLAG_SMC,
.port = {
.irq = SCC1_IRQ,
.ops = &cpm_uart_pops,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.lock = SPIN_LOCK_UNLOCKED,
},
.tx_nrfifos = TX_NUM_FIFO,
.port = {
.irq = SCC2_IRQ,
.ops = &cpm_uart_pops,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.lock = SPIN_LOCK_UNLOCKED,
},
.tx_nrfifos = TX_NUM_FIFO,
.port = {
.irq = SCC3_IRQ,
.ops = &cpm_uart_pops,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.lock = SPIN_LOCK_UNLOCKED,
},
.tx_nrfifos = TX_NUM_FIFO,
.port = {
.irq = SCC4_IRQ,
.ops = &cpm_uart_pops,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.lock = SPIN_LOCK_UNLOCKED,
},
.tx_nrfifos = TX_NUM_FIFO,
}
tty_insert_flip_char(tty, ch, flag);
ignore_char:
+ ;
} while (status & DZ_DVAL);
if (tty)
for (i = 0, dport = dz_ports; i < DZ_NB_PORT; i++, dport++) {
spin_lock_init(&dport->port.lock);
dport->port.membase = (char *) base;
- dport->port.iotype = SERIAL_IO_PORT;
+ dport->port.iotype = UPIO_PORT;
dport->port.irq = dec_interrupt[DEC_IRQ_DZ11];
dport->port.line = i;
dport->port.fifosize = 1;
.rtsirq = UART1_MINT_RTS,
.port = {
.type = PORT_IMX,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.membase = (void *)IMX_UART1_BASE,
.mapbase = IMX_UART1_BASE, /* FIXME */
.irq = UART1_MINT_RX,
.rtsirq = UART2_MINT_RTS,
.port = {
.type = PORT_IMX,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.membase = (void *)IMX_UART2_BASE,
.mapbase = IMX_UART2_BASE, /* FIXME */
.irq = UART2_MINT_RX,
/* Lower and upper byte of baud rate generator divisor. */
write_zsreg(channel, R12, regs[R12]);
write_zsreg(channel, R13, regs[R13]);
-
+
/* Now rewrite R14, with BRENAB (if set). */
write_zsreg(channel, R14, regs[R14]);
else
clear_bits |= DTR;
- /* NOTE: Not subject to 'transmitter active' rule. */
+ /* NOTE: Not subject to 'transmitter active' rule. */
up->curregs[R5] |= set_bits;
up->curregs[R5] &= ~clear_bits;
write_zsreg(channel, R5, up->curregs[R5]);
if (new_reg != up->curregs[R15]) {
up->curregs[R15] = new_reg;
- /* NOTE: Not subject to 'transmitter active' rule. */
+ /* NOTE: Not subject to 'transmitter active' rule. */
write_zsreg(channel, R15, up->curregs[R15]);
}
}
if (new_reg != up->curregs[R5]) {
up->curregs[R5] = new_reg;
- /* NOTE: Not subject to 'transmitter active' rule. */
+ /* NOTE: Not subject to 'transmitter active' rule. */
write_zsreg(channel, R5, up->curregs[R5]);
}
#include <asm/serial.h>
/* Standard COM flags */
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
/*
* SERIAL_PORT_DFNS tells us about built-in ports that have no
port->mapbase = dev->hpa.start + MUX_OFFSET +
(i * MUX_LINE_OFFSET);
port->membase = ioremap(port->mapbase, MUX_LINE_OFFSET);
- port->iotype = SERIAL_IO_MEM;
+ port->iotype = UPIO_MEM;
port->type = PORT_MUX;
port->irq = NO_IRQ;
port->uartclk = 0;
/*
* Init remaining bits of "port" structure
*/
- uap->port.iotype = SERIAL_IO_MEM;
+ uap->port.iotype = UPIO_MEM;
uap->port.irq = np->intrs[0].line;
uap->port.uartclk = ZS_CLOCK;
uap->port.fifosize = 1;
sa1100_ports[i].port.ops = &sa1100_pops;
sa1100_ports[i].port.fifosize = 8;
sa1100_ports[i].port.line = i;
- sa1100_ports[i].port.iotype = SERIAL_IO_MEM;
+ sa1100_ports[i].port.iotype = UPIO_MEM;
init_timer(&sa1100_ports[i].timer);
sa1100_ports[i].timer.function = sa1100_timeout;
sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i];
.port = {
.membase = (void*) io_p2v (UART1_PHYS),
.mapbase = UART1_PHYS,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = IRQ_UART1INTR,
.uartclk = 14745600/2,
.fifosize = 16,
.port = {
.membase = (void*) io_p2v (UART2_PHYS),
.mapbase = UART2_PHYS,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = IRQ_UART2INTR,
.uartclk = 14745600/2,
.fifosize = 16,
.port = {
.membase = (void*) io_p2v (UART3_PHYS),
.mapbase = UART3_PHYS,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = IRQ_UART3INTR,
.uartclk = 14745600/2,
.fifosize = 16,
.port = {
.membase = (void *)0xff923000,
.mapbase = 0xff923000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 61,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xff924000,
.mapbase = 0xff924000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 62,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xff925000,
.mapbase = 0xff925000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 63,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 2,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xffe00000,
.mapbase = 0xffe00000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 43,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCIF,
.port = {
.membase = (void *)0xffe10000,
.mapbase = 0xffe10000,
- .iotype = SERIAL_IO_MEM,
+ .iotype = UPIO_MEM,
.irq = 79,
.ops = &sci_uart_ops,
- .flags = ASYNC_BOOT_AUTOCONF,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
.type = PORT_SCIF,
up->port.irq = edev->irqs[0];
up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
up->port.mapbase = (unsigned long)up->regs;
- up->port.iotype = SERIAL_IO_MEM;
+ up->port.iotype = UPIO_MEM;
writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
offset <<= up->port.regshift;
switch (up->port.iotype) {
- case SERIAL_IO_HUB6:
+ case UPIO_HUB6:
outb(up->port.hub6 - 1 + offset, up->port.iobase);
return inb(up->port.iobase + 1);
- case SERIAL_IO_MEM:
+ case UPIO_MEM:
return readb(up->port.membase + offset);
default:
offset <<= up->port.regshift;
switch (up->port.iotype) {
- case SERIAL_IO_HUB6:
+ case UPIO_HUB6:
outb(up->port.hub6 - 1 + offset, up->port.iobase);
outb(value, up->port.iobase + 1);
break;
- case SERIAL_IO_MEM:
+ case UPIO_MEM:
writeb(value, up->port.membase + offset);
break;
return;
up->type_probed = PORT_UNKNOWN;
- up->port.iotype = SERIAL_IO_MEM;
+ up->port.iotype = UPIO_MEM;
/*
* First we look for Ebus-bases su's
up[(chip * 2) + 1].port.membase = (void __iomem *)&rp->channelB;
/* Channel A */
- up[(chip * 2) + 0].port.iotype = SERIAL_IO_MEM;
+ up[(chip * 2) + 0].port.iotype = UPIO_MEM;
up[(chip * 2) + 0].port.irq = zilog_irq;
up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
up[(chip * 2) + 0].port.fifosize = 1;
up[(chip * 2) + 0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
/* Channel B */
- up[(chip * 2) + 1].port.iotype = SERIAL_IO_MEM;
+ up[(chip * 2) + 1].port.iotype = UPIO_MEM;
up[(chip * 2) + 1].port.irq = zilog_irq;
up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
up[(chip * 2) + 1].port.fifosize = 1;
port->ops = &v850e_uart_ops;
port->line = chan;
- port->iotype = SERIAL_IO_MEM;
+ port->iotype = UPIO_MEM;
port->flags = UPF_BOOT_AUTOCONF;
/* We actually use multiple IRQs, but the serial
#define PCI_VENDOR_ID_AFAVLAB 0x14db
#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180
#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
+#define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
#define PCI_VENDOR_ID_BROADCOM 0x14e4
#define PCI_DEVICE_ID_TIGON3_5752 0x1600