If BitWidth equals to ShtAmt, the RHSKnownZero[BitWidth-ShiftAmt-1] will

crash the opt. Just fix this.

Test case in llvm/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52003 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index 516841a763959dacfc12e769166db0c781a065bf..05e12692f4c129d33e49878b3f9e77e539c6ada7 100644 (file)
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -1236,7 +1236,7 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask,
         
       // If the input sign bit is known to be zero, or if none of the top bits
       // are demanded, turn this into an unsigned shift right.
-      if (RHSKnownZero[BitWidth-ShiftAmt-1] || 
+      if (BitWidth == ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] || 
           (HighBits & ~DemandedMask) == HighBits) {
         // Perform the logical shift right.
         Value *NewVal = BinaryOperator::CreateLShr(