}
multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
- let DecoderNamespace = "Common" in {
def _OFFSET : ACI<(outs),
!con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
!strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
let Inst{20} = load;
let DecoderMethod = "DecodeCopMemInstruction";
}
- }
}
defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
return result;
}
- // Instructions that are shared between ARM and Thumb modes.
- // FIXME: This shouldn't really exist. It's an artifact of the
- // fact that we fail to encode a few instructions properly for Thumb.
- MI.clear();
- result = decodeCommonInstruction32(MI, insn, Address, this, STI);
- if (result != MCDisassembler::Fail) {
- Size = 4;
- return result;
- }
-
// VFP and NEON instructions, similarly, are shared between ARM
// and Thumb modes.
MI.clear();
return result;
}
- MI.clear();
- result = decodeCommonInstruction32(MI, insn32, Address, this, STI);
- if (result != MCDisassembler::Fail) {
- Size = 4;
- AddThumbPredicate(MI);
- return result;
- }
-
MI.clear();
result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
if (result != MCDisassembler::Fail) {