FROMLIST: drm/rockchip: dw_hdmi: introduce the pclk for grf

For RK3399's GRF module, if we want to operate the graphic related grf
registers, we need to enable the pclk_vio_grf which supply power for VIO
GRF IOs, so it's better to introduce an optional grf clock in driver.

Change-Id: I8f43e5c46c8559d6b6fe96a12cd026319b1d84e5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9223317/)

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
index 4e23ca433940a78474fe675efa7c8d2c14b02868..e22d70f669a26e759cb25f672ecdfe98fff3f331 100644 (file)
--- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
@@ -18,7 +18,8 @@ Required properties:
 Optional properties
 - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
 - clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec",
-                      phandle to the VPLL clock, name should be "vpll".
+                      phandle to the VPLL clock, name should be "vpll",
+                      phandle to the GRF clock, name should be "grf".
 
 Example:
 hdmi: hdmi@ff980000 {

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 701bb739dd3fc15cd5f9a46de17e14212017206c..69e6efb80433db4595bba769c1d32ac85be654ab 100644 (file)
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -36,6 +36,7 @@ struct rockchip_hdmi {
        struct drm_encoder encoder;
        enum dw_hdmi_devtype dev_type;
        struct clk *vpll_clk;
+       struct clk *grf_clk;
 };
 
 #define to_rockchip_hdmi(x)    container_of(x, struct rockchip_hdmi, x)
@@ -166,6 +167,16 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
                return PTR_ERR(hdmi->vpll_clk);
        }
 
+       hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
+       if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
+               hdmi->grf_clk = NULL;
+       } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
+               return -EPROBE_DEFER;
+       } else if (IS_ERR(hdmi->grf_clk)) {
+               dev_err(hdmi->dev, "failed to get grf clock\n");
+               return PTR_ERR(hdmi->grf_clk);
+       }
+
        ret = clk_prepare_enable(hdmi->vpll_clk);
        if (ret) {
                dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
@@ -225,6 +236,7 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
        u32 lcdsel_grf_reg, lcdsel_mask;
        u32 val;
        int mux;
+       int ret;
 
        switch (hdmi->dev_type) {
        case RK3288_HDMI:
@@ -245,9 +257,17 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
        else
                val = HIWORD_UPDATE(0, lcdsel_mask);
 
+       ret = clk_prepare_enable(hdmi->grf_clk);
+       if (ret < 0) {
+               dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
+               return;
+       }
+
        regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
        dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
                (mux) ? "LIT" : "BIG");
+
+       clk_disable_unprepare(hdmi->grf_clk);
 }
 
 static int