Merge branch 'develop-3.10' of ssh://10.10.10.29/rk/kernel into develop-3.10

diff --git a/arch/arm/boot/dts/rk312x-sdk.dtsi b/arch/arm/boot/dts/rk312x-sdk.dtsi
index 7d364c78fda8ef459628675db70473792ef46519..78318f99edf65e1431e642c4ab0e0194d28a8640 100755 (executable)
--- a/arch/arm/boot/dts/rk312x-sdk.dtsi
+++ b/arch/arm/boot/dts/rk312x-sdk.dtsi
@@ -172,7 +172,12 @@
        rt5025: rt5025@35 {
                        compatible = "rt,rt5025";
                        reg = <0x35>;
-                       status = "okay";
+                       status = "disabled";
+       };
+       rt5036: rt5036@38 {
+                       compatible = "rt,rt5036";
+                       reg = <0x38>;
+                       status = "disabled";
        };
 };
 
@@ -305,6 +310,136 @@
        };
 };
 
+/include/ "rt5036.dtsi"
+&rt5036 {
+
+                       rt5036_dcdc1: regulator_0 {
+                               regulator-name = "vdd_arm";
+                               regulator-min-microvolt = < 800000>;
+                               regulator-max-microvolt = <3300000>;
+                               qcom,comsumer-supplies = "vdd_arm", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                               rt,standby_vol = <950000>; 
+                       };
+
+                       rt5036_dcdc2: regulator_1 {
+                               regulator-name = "vdd_logic";
+                               regulator-min-microvolt = < 800000>;
+                               regulator-max-microvolt = <3300000>;
+                               qcom,comsumer-supplies = "vdd_logic", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                               rt,standby_vol = <950000>; 
+                       };
+
+                       rt5036_dcdc3: regulator_2 {
+                               regulator-name = "rt5036-dcdc3";
+                               regulator-min-microvolt = < 800000>;
+                               regulator-max-microvolt = <3300000>;
+                               qcom,comsumer-supplies = "rt5036-dcdc3", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                               rt,standby_vol = <2800000>; 
+                       };
+
+                       rt5036_dcdc4: regulator_3 {
+                               regulator-name = "rt5036-dcdc4";
+                               regulator-min-microvolt = < 800000>;
+                               regulator-max-microvolt = <3300000>;
+                               qcom,comsumer-supplies = "rt5036-dcdc4", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                               rt,standby_vol = <1200000>; 
+                       };
+
+                       rt5036_ldo1: regulator_4 {
+                               regulator-name = "rt5036-ldo1";
+                               regulator-min-microvolt = < 3000000>;
+                               regulator-max-microvolt = <3000000>;
+                               qcom,comsumer-supplies = "rt5036-ldo1", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                               rt,standby_vol = <3000000>; 
+                       };
+
+                       rt5036_ldo2: regulator_5 {
+                               regulator-name = "rt5036-ldo2";
+                               regulator-min-microvolt = < 1100000>;
+                               regulator-max-microvolt = <1100000>;
+                               qcom,comsumer-supplies = "rt5036-ldo2", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                               rt,standby_vol = <1100000>; 
+                       };
+
+                       rt5036_ldo3: regulator_6 {
+                               regulator-name = "rt5036-ldo3";
+                               regulator-min-microvolt = < 1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               qcom,comsumer-supplies = "rt5036-ldo3", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                               rt,standby_vol = <1800000>; 
+                       };
+
+                       rt5036_ldo4: regulator_7 {
+                               regulator-name = "rt5036-ldo4";
+                               regulator-min-microvolt = < 1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               qcom,comsumer-supplies = "rt5036-ldo4", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                               rt,standby_vol = <1800000>; 
+                       };
+
+                       rt5036_ldo5: regulator_8 {
+                               regulator-name = "rt5036-ldo5";
+                               qcom,comsumer-supplies = "rt5036-ldo5", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                       };
+
+                       rt5036_ldo6: regulator_9 {
+                               regulator-name = "rt5036-ldo6";
+                               qcom,comsumer-supplies = "rt5036-ldo6", "";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               rt,standby_enabled;
+                       };
+
+                       rt5036-irq {
+                               compatible = "rt,rt5036-irq";
+                               rt,irq-gpio = <&gpio1 GPIO_B1 GPIO_ACTIVE_HIGH>;
+                       };
+
+                       rt5036-charger {
+                               compatible = "rt,rt5036-charger";
+                               rt,te_en;
+                               rt,iprec = <0x2>;
+                               rt,ieoc = <0x3>;
+                               rt,vprec = <0xA>;
+                               rt,batlv = <0x4>;
+                               rt,vrechg = <1>;
+                               rt,chg_volt = <4200>;
+                               rt,otg_volt = <5025>;
+                               rt,acchg_icc = <2000>;
+                               rt,usbtachg_icc = <2000>;
+                               rt,usbchg_icc = <900>;
+                               /*rt,acdet_gpio = <&gpio1 GPIO_B1 GPIO_ACTIVE_HIGH>;*/
+                               /*rt,usbdet_gpio = <&gpio1 GPIO_B1 GPIO_ACTIVE_HIGH>;*/
+                       };
+};
+
 /include/ "rk818.dtsi"
 &rk818 {
        gpios =<&gpio1 GPIO_B1 GPIO_ACTIVE_HIGH>,<&gpio1 GPIO_A1 GPIO_ACTIVE_LOW>;
@@ -483,11 +618,11 @@
 &clk_core_dvfs_table {
        operating-points = <
                /* KHz    uV */
-               408000 1250000
-               600000 1250000
-               696000 1250000
-               816000 1250000
-               1008000 1250000
+               408000 1300000
+               600000 1300000
+               696000 1300000
+               816000 1300000
+               1008000 1300000
                >;
        status="okay";
 };

diff --git a/arch/arm/boot/dts/rt5036.dtsi b/arch/arm/boot/dts/rt5036.dtsi
new file mode 100755 (executable)
index 0000000..fd59ded
--- /dev/null
+++ b/arch/arm/boot/dts/rt5036.dtsi
@@ -0,0 +1,108 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&rt5036 {
+       compatible = "rt,rt5036";
+
+                       rt5036_dcdc1: regulator_0 {
+                               compatible = "rt,rt5036-dcdc1";
+                               cell-index = <0>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036_dcdc2: regulator_1 {
+                               compatible = "rt,rt5036-dcdc2";
+                               cell-index = <1>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036_dcdc3: regulator_2 {
+                               compatible = "rt,rt5036-dcdc3";
+                               cell-index = <2>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036_dcdc4: regulator_3 {
+                               compatible = "rt,rt5036-dcdc4";
+                               cell-index = <3>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036_ldo1: regulator_4 {
+                               supply-regulator = "rt5036-dcdc3";
+                               compatible = "rt,rt5036-ldo1";
+                               cell-index = <4>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036_ldo2: regulator_5 {
+                               supply-regulator = "rt5036-dcdc3";
+                               compatible = "rt,rt5036-ldo2";
+                               cell-index = <5>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036_ldo3: regulator_6 {
+                               supply-regulator = "rt5036-dcdc3";
+                               compatible = "rt,rt5036-ldo3";
+                               cell-index = <6>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036_ldo4: regulator_7 {
+                               supply-regulator = "rt5036-dcdc3";
+                               compatible = "rt,rt5036-ldo4";
+                               cell-index = <7>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036_lsw1: regulator_8 {
+                               supply-regulator = "rt5036-dcdc3";
+                               compatible = "rt,rt5036-lsw1";
+                               cell-index = <8>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036_lsw2: regulator_9 {
+                               supply-regulator = "rt5036-dcdc3";
+                               compatible = "rt,rt5036-lsw2";
+                               cell-index = <9>;
+                               rt,nramp_sel = <0x00>;
+                               rt,sramp_sel = <0x00>;
+                               rt,allow_mode_mask;
+                       };
+                       rt5036-rtc {
+                               compatible = "rt,rt5036-rtc";
+                       };
+                       rt5036-misc {
+                               compatible = "rt,rt5036-misc";
+                               rt,shdn_press = <0x1>;
+                               rt,stb_en = <1>;
+                               rt,lp_enshdn;
+                               rt,vsysuvlo = <0x2>;
+                               rt,syslv_enshdn;
+                               rt,system-power-controller;
+                       };
+                       rt5036-debug {
+                               compatible = "rt,rt5036-debug";
+                       };
+       };
+

diff --git a/arch/arm/configs/rockchip_defconfig b/arch/arm/configs/rockchip_defconfig
old mode 100644 (file)
new mode 100755 (executable)
index bd288d7..929d664
--- a/arch/arm/configs/rockchip_defconfig
+++ b/arch/arm/configs/rockchip_defconfig
@@ -329,12 +329,23 @@ CONFIG_SPI_ROCKCHIP_DMA=y
 CONFIG_SPI_ROCKCHIP_TEST=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_CHARGER_RT5025=y
+CONFIG_BATTERY_RT5025=y
+CONFIG_CHARGER_RT5036=y
+CONFIG_RT_POWER=y
 CONFIG_BATTERY_RICOH619=y
 CONFIG_BATTERY_BQ24296=y
 CONFIG_BATTERY_BQ27320=y
 CONFIG_CW2015_BATTERY=y
 CONFIG_SENSORS_ROCKCHIP_TSADC=y
 CONFIG_THERMAL=y
+CONFIG_MFD_RT5025=y
+CONFIG_MISC_RT5025=y
+CONFIG_IRQ_RT5025=y
+CONFIG_DEBUG_RT5025=y
+CONFIG_MFD_RT5036=y
+CONFIG_MISC_RT5036=y
+CONFIG_IRQ_RT5036=y
 CONFIG_MFD_RK808=y
 CONFIG_MFD_RK818=y
 CONFIG_MFD_RICOH619=y
@@ -342,6 +353,8 @@ CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_ACT8846=y
 CONFIG_ACT8846_SUPPORT_RESET=y
+CONFIG_REGULATOR_RT5025=y
+CONFIG_REGULATOR_RT5036=y
 CONFIG_ROCKCHIP_PWM_REGULATOR=y
 CONFIG_REGULATOR_SYR82X=y
 CONFIG_REGULATOR_RICOH619=y
@@ -509,6 +522,7 @@ CONFIG_SWITCH=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HYM8563=y
 CONFIG_RK808_RTC=y
+CONFIG_RTC_RT5036=y
 CONFIG_RTC_DRV_RC5T619=y
 CONFIG_STAGING=y
 CONFIG_ZSMALLOC=y

diff --git a/arch/arm/mach-rockchip/ddr_rk3036.c b/arch/arm/mach-rockchip/ddr_rk3036.c
new file mode 100755 (executable)
index 0000000..518cac4
--- /dev/null
+++ b/arch/arm/mach-rockchip/ddr_rk3036.c
@@ -0,0 +1,2125 @@
+/*
+ * arch/arm/mach-rk2928/ddr.c-- for ddr3&ddr2
+ *
+ * Function Driver for DDR controller
+ *
+ * Copyright (C) 2012 Fuzhou Rockchip Electronics Co.,Ltd
+ * Author: 
+ * hcy@rock-chips.com
+ * yk@rock-chips.com
+ * typ@rock-chips.com
+ * 
+ * v1.00 
+ */
+ 
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <linux/cpu.h>
+#include <dt-bindings/clock/ddr.h>
+#include <linux/rockchip/cru.h>
+#include <linux/rk_fb.h>
+#include "cpu_axi.h"
+
+
+typedef uint32_t uint32 ;
+
+
+#define DDR3_DDR2_DLL_DISABLE_FREQ    (300)  // ¿ÅÁ£dll disableµÄƵÂÊ
+#define DDR3_DDR2_ODT_DISABLE_FREQ    (333)  //¿ÅÁ£odt disableµÄƵÂÊ
+#define SR_IDLE                       (0x1)   //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
+#define PD_IDLE                       (0x40)  //unit:DDR clk cycle, and 0 for disable auto power-down
+#define PHY_ODT_DISABLE_FREQ          (333)  //¶¨ÒåÖ÷¿Ø¶Ëodt disableµÄƵÂÊ
+#define PHY_DLL_DISABLE_FREQ          (266)  //¶¨ÒåÖ÷¿Ø¶Ëdll bypassµÄƵÂÊ
+
+#define ddr_print(x...) printk( "DDR DEBUG: " x )
+
+#define SRAM_CODE_OFFSET        rockchip_sram_virt
+#define SRAM_SIZE               rockchip_sram_size
+
+
+/***********************************
+ * DDR3 define
+ ***********************************/
+//mr0 for ddr3
+#define DDR3_BL8          (0)
+#define DDR3_BC4_8        (1)
+#define DDR3_BC4          (2)
+#define DDR3_CL(n)        (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
+#define DDR3_WR(n)        (((n)&0x7)<<9)
+#define DDR3_DLL_RESET    (1<<8)
+#define DDR3_DLL_DeRESET  (0<<8)
+    
+//mr1 for ddr3
+#define DDR3_DLL_ENABLE    (0)
+#define DDR3_DLL_DISABLE   (1)
+#define DDR3_MR1_AL(n)  (((n)&0x7)<<3)
+    
+#define DDR3_DS_40            (0)
+#define DDR3_DS_34            (1<<1)
+#define DDR3_Rtt_Nom_DIS      (0)
+#define DDR3_Rtt_Nom_60       (1<<2)
+#define DDR3_Rtt_Nom_120      (1<<6)
+#define DDR3_Rtt_Nom_40       ((1<<2)|(1<<6))
+    
+//mr2 for ddr3
+#define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
+#define DDR3_Rtt_WR_DIS       (0)
+#define DDR3_Rtt_WR_60        (1<<9)
+#define DDR3_Rtt_WR_120       (2<<9)
+
+#define DDR_PLL_REFDIV  (1)
+#define FBDIV(n)        ((0xFFF<<16) | (n&0xfff))
+#define REFDIV(n)       ((0x3F<<16) | (n&0x3f))
+#define POSTDIV1(n)     ((0x7<<(12+16)) | ((n&0x7)<<12))
+#define POSTDIV2(n)     ((0x7<<(6+16)) | ((n&0x7)<<6))
+
+#define PLL_LOCK_STATUS  (0x1<<10)
+ //CRU Registers
+typedef volatile struct tagCRU_STRUCT
+{
+    uint32 CRU_PLL_CON[4][4]; 
+    uint32 CRU_MODE_CON;
+    uint32 CRU_CLKSEL_CON[35];
+    uint32 CRU_CLKGATE_CON[10];
+    uint32 reserved1[2];
+    uint32 CRU_GLB_SRST_FST_VALUE;
+    uint32 CRU_GLB_SRST_SND_VALUE;
+    uint32 reserved2[2];
+    uint32 CRU_SOFTRST_CON[9];
+    uint32 CRU_MISC_CON;
+    uint32 reserved3[2];
+    uint32 CRU_GLB_CNT_TH;
+    uint32 CRU_SDMMC_CON[2];
+    uint32 CRU_SDIO_CON[2];
+    uint32 CRU_EMMC_CON[2];
+    uint32 reserved4;
+    uint32 CRU_RST_ST;
+    uint32 reserved5[(0x1f0-0x164)/4];
+    uint32 CRU_PLL_MASK_CON;
+} CRU_REG, *pCRU_REG;
+
+typedef struct tagGPIO_LH
+{
+    uint32 GPIOL;
+    uint32 GPIOH;
+}GPIO_LH_T;
+
+typedef struct tagGPIO_IOMUX
+{
+    uint32 GPIOA_IOMUX;
+    uint32 GPIOB_IOMUX;
+    uint32 GPIOC_IOMUX;
+    uint32 GPIOD_IOMUX;
+}GPIO_IOMUX_T;
+
+/********************************
+GRF ¼Ä´æÆ÷ÖÐGRF_OS_REG1 ´æddr rank£¬typeµÈÐÅÏ¢
+GRF_SOC_CON2¼Ä´æÆ÷ÖпØÖÆc_sysreqÐźÅÏòpctl·¢ËͽøÈëlow power ÇëÇó
+GRF_DDRC_STAT ¿É²éѯpctlÊÇ·ñ½ÓÊÜÇëÇó ½øÈëlow power 
+********************************/
+//REG FILE registers    
+//GRF_SOC_STATUS0
+#define sys_pwr_idle     (1<<27)
+#define gpu_pwr_idle     (1<<26)
+#define vpu_pwr_idle     (1<<25)
+#define vio_pwr_idle     (1<<24)
+#define peri_pwr_idle    (1<<23)
+#define core_pwr_idle     (1<<22)
+//GRF_SOC_CON2
+#define core_pwr_idlereq    (13)
+#define peri_pwr_idlereq    (12)
+#define vio_pwr_idlereq     (11)
+#define vpu_pwr_idlereq     (10)
+#define gpu_pwr_idlereq     (9)
+#define sys_pwr_idlereq     (8)
+
+typedef volatile struct tagREG_FILE
+{
+    uint32 reserved0[(0xa8-0x0)/4];
+    GPIO_IOMUX_T GRF_GPIO_IOMUX[3]; // 0x00a8
+    uint32 reserved1[(0x100-0xd8)/4];
+    uint32 GRF_GPIO_DS;             //0x100
+    uint32 reserved2[(0x118-0x104)/4];
+    GPIO_LH_T GRF_GPIO_PULL[3];     // 0x118
+    uint32 reserved3[(0x140-0x130)/4];
+    uint32 GRF_SOC_CON[3];          // 0x140
+    uint32 GRF_SOC_STATUS0;
+    //uint32 GRF_LVDS_CON0;
+    uint32 reserved4;               //0x150
+    uint32 GRF_SOC_CON3;
+    uint32 reserved5[(0x15c-0x158)/4];
+    uint32 GRF_DMAC_CON[3];        //0x15c
+    uint32 reserved6[(0x17c-0x168)/4];
+    uint32 GRF_UOC0_CON5;         //0x17c
+    uint32 reserved7[(0x190-0x180)/4];
+    uint32 GRF_UOC1_CON4;         //0x190
+    uint32 GRF_UOC1_COM5;
+    uint32 reserved8;
+    uint32 GRF_DDRC_STAT;
+    uint32 GRF_UOC_CON6;
+    uint32 GRF_SOC_STATUS1;
+    uint32 GRF_CPU_CON[4];
+    uint32 reserved9[(0x1c0-0x1b8)/4];
+    uint32 GRF_CPU_STATUS[2];
+    uint32 GRF_OS_REG[8];
+    uint32 reserved10[(0x200-0x1e8)/4];
+    uint32 GRF_DLL_CON[4];          //0X200
+    uint32 GRF_DLL_STATUS[4];
+    //uint32 reserved10[(0x220-0x214)/4];
+    uint32 GRF_DFI_WRNUM;           //0X220
+    uint32 GRF_DFI_RDNUM;
+    uint32 GRF_DFI_ACTNUM;
+    uint32 GRF_DFI_TIMERVAL;
+    uint32 GRF_NIF_FIFO[4];
+    uint32 reserved11[(0x280-0x240)/4];
+    uint32 GRF_USBPHY0_CON[8];
+    uint32 GRF_USBPHY1_CON[8];
+    uint32 reserved12[(0x300-0x2c0)/4];
+    uint32 GRF_CHIP_TAG;
+    uint32 GRF_SDMMC_DET_CNT;
+} REG_FILE, *pREG_FILE;
+
+//SCTL
+#define INIT_STATE                     (0)
+#define CFG_STATE                      (1)
+#define GO_STATE                       (2)
+#define SLEEP_STATE                    (3)
+#define WAKEUP_STATE                   (4)
+
+//STAT
+#define Init_mem                       (0)
+#define Config                         (1)
+#define Config_req                     (2)
+#define Access                         (3)
+#define Access_req                     (4)
+#define Low_power                      (5)
+#define Low_power_entry_req            (6)
+#define Low_power_exit_req             (7)
+
+//MCFG
+#define mddr_lpddr2_clk_stop_idle(n)   ((n)<<24)
+#define pd_idle(n)                     ((n)<<8)
+#define mddr_en                        (2<<22)
+#define lpddr2_en                      (3<<22)
+#define ddr2_en                        (0<<5)
+#define ddr3_en                        (1<<5)
+#define lpddr2_s2                      (0<<6)
+#define lpddr2_s4                      (1<<6)
+#define mddr_lpddr2_bl_2               (0<<20)
+#define mddr_lpddr2_bl_4               (1<<20)
+#define mddr_lpddr2_bl_8               (2<<20)
+#define mddr_lpddr2_bl_16              (3<<20)
+#define ddr2_ddr3_bl_4                 (0)
+#define ddr2_ddr3_bl_8                 (1)
+#define tfaw_cfg(n)                    (((n)-4)<<18)
+#define pd_exit_slow                   (0<<17)
+#define pd_exit_fast                   (1<<17)
+#define pd_type(n)                     ((n)<<16)
+#define two_t_en(n)                    ((n)<<3)
+#define bl8int_en(n)                   ((n)<<2)
+#define cke_or_en(n)                   ((n)<<1)
+
+//POWCTL
+#define power_up_start                 (1<<0)
+
+//POWSTAT
+#define power_up_done                  (1<<0)
+
+//DFISTSTAT0
+#define dfi_init_complete              (1<<0)
+
+//CMDTSTAT
+#define cmd_tstat                      (1<<0)
+
+//CMDTSTATEN
+#define cmd_tstat_en                   (1<<1)
+
+//MCMD
+#define Deselect_cmd                   (0)
+#define PREA_cmd                       (1)
+#define REF_cmd                        (2)
+#define MRS_cmd                        (3)
+#define ZQCS_cmd                       (4)
+#define ZQCL_cmd                       (5)
+#define RSTL_cmd                       (6)
+#define MRR_cmd                        (8)
+#define DPDE_cmd                       (9)
+
+#define lpddr2_op(n)                   ((n)<<12)
+#define lpddr2_ma(n)                   ((n)<<4)
+
+#define bank_addr(n)                   ((n)<<17)
+#define cmd_addr(n)                    ((n)<<4)
+
+#define start_cmd                      (1u<<31)
+
+typedef union STAT_Tag
+{
+    uint32 d32;
+    struct
+    {
+        unsigned ctl_stat : 3;
+        unsigned reserved3 : 1;
+        unsigned lp_trig : 3;
+        unsigned reserved7_31 : 25;
+    }b;
+}STAT_T;
+
+typedef union SCFG_Tag
+{
+    uint32 d32;
+    struct
+    {
+        unsigned hw_low_power_en : 1;
+        unsigned reserved1_5 : 5;
+        unsigned nfifo_nif1_dis : 1;
+        unsigned reserved7 : 1;
+        unsigned bbflags_timing : 4;
+        unsigned reserved12_31 : 20;
+    } b;
+}SCFG_T;
+
+/* DDR Controller register struct */
+typedef volatile struct DDR_REG_Tag
+{
+    //Operational State, Control, and Status Registers
+    SCFG_T SCFG;                   //State Configuration Register
+    volatile uint32 SCTL;                   //State Control Register
+    STAT_T STAT;                   //State Status Register
+    volatile uint32 INTRSTAT;               //Interrupt Status Register
+    uint32 reserved0[(0x40-0x10)/4];
+    //Initailization Control and Status Registers
+    volatile uint32 MCMD;                   //Memory Command Register
+    volatile uint32 POWCTL;                 //Power Up Control Registers
+    volatile uint32 POWSTAT;                //Power Up Status Register
+    volatile uint32 CMDTSTAT;               //Command Timing Status Register
+    volatile uint32 CMDTSTATEN;             //Command Timing Status Enable Register
+    uint32 reserved1[(0x60-0x54)/4];
+    volatile uint32 MRRCFG0;                //MRR Configuration 0 Register
+    volatile uint32 MRRSTAT0;               //MRR Status 0 Register
+    volatile uint32 MRRSTAT1;               //MRR Status 1 Register
+    uint32 reserved2[(0x7c-0x6c)/4];
+    //Memory Control and Status Registers
+    volatile uint32 MCFG1;                  //Memory Configuration 1 Register
+    volatile uint32 MCFG;                   //Memory Configuration Register
+    volatile uint32 PPCFG;                  //Partially Populated Memories Configuration Register
+    volatile uint32 MSTAT;                  //Memory Status Register
+    volatile uint32 LPDDR2ZQCFG;            //LPDDR2 ZQ Configuration Register
+    uint32 reserved3;
+    //DTU Control and Status Registers
+    volatile uint32 DTUPDES;                //DTU Status Register
+    volatile uint32 DTUNA;                  //DTU Number of Random Addresses Created Register
+    volatile uint32 DTUNE;                  //DTU Number of Errors Register
+    volatile uint32 DTUPRD0;                //DTU Parallel Read 0
+    volatile uint32 DTUPRD1;                //DTU Parallel Read 1
+    volatile uint32 DTUPRD2;                //DTU Parallel Read 2
+    volatile uint32 DTUPRD3;                //DTU Parallel Read 3
+    volatile uint32 DTUAWDT;                //DTU Address Width
+    uint32 reserved4[(0xc0-0xb4)/4];
+    //Memory Timing Registers
+    volatile uint32 TOGCNT1U;               //Toggle Counter 1U Register
+    volatile uint32 TINIT;                  //t_init Timing Register
+    volatile uint32 TRSTH;                  //Reset High Time Register
+    volatile uint32 TOGCNT100N;             //Toggle Counter 100N Register
+    volatile uint32 TREFI;                  //t_refi Timing Register
+    volatile uint32 TMRD;                   //t_mrd Timing Register
+    volatile uint32 TRFC;                   //t_rfc Timing Register
+    volatile uint32 TRP;                    //t_rp Timing Register
+    volatile uint32 TRTW;                   //t_rtw Timing Register
+    volatile uint32 TAL;                    //AL Latency Register
+    volatile uint32 TCL;                    //CL Timing Register
+    volatile uint32 TCWL;                   //CWL Register
+    volatile uint32 TRAS;                   //t_ras Timing Register
+    volatile uint32 TRC;                    //t_rc Timing Register
+    volatile uint32 TRCD;                   //t_rcd Timing Register
+    volatile uint32 TRRD;                   //t_rrd Timing Register
+    volatile uint32 TRTP;                   //t_rtp Timing Register
+    volatile uint32 TWR;                    //t_wr Timing Register
+    volatile uint32 TWTR;                   //t_wtr Timing Register
+    volatile uint32 TEXSR;                  //t_exsr Timing Register
+    volatile uint32 TXP;                    //t_xp Timing Register
+    volatile uint32 TXPDLL;                 //t_xpdll Timing Register
+    volatile uint32 TZQCS;                  //t_zqcs Timing Register
+    volatile uint32 TZQCSI;                 //t_zqcsi Timing Register
+    volatile uint32 TDQS;                   //t_dqs Timing Register
+    volatile uint32 TCKSRE;                 //t_cksre Timing Register
+    volatile uint32 TCKSRX;                 //t_cksrx Timing Register
+    volatile uint32 TCKE;                   //t_cke Timing Register
+    volatile uint32 TMOD;                   //t_mod Timing Register
+    volatile uint32 TRSTL;                  //Reset Low Timing Register
+    volatile uint32 TZQCL;                  //t_zqcl Timing Register
+    volatile uint32 TMRR;                   //t_mrr Timing Register
+    volatile uint32 TCKESR;                 //t_ckesr Timing Register
+    volatile uint32 TDPD;                   //t_dpd Timing Register
+    uint32 reserved5[(0x180-0x148)/4];
+    //ECC Configuration, Control, and Status Registers
+    volatile uint32 ECCCFG;                   //ECC Configuration Register
+    volatile uint32 ECCTST;                   //ECC Test Register
+    volatile uint32 ECCCLR;                   //ECC Clear Register
+    volatile uint32 ECCLOG;                   //ECC Log Register
+    uint32 reserved6[(0x200-0x190)/4];
+    //DTU Control and Status Registers
+    volatile uint32 DTUWACTL;                 //DTU Write Address Control Register
+    volatile uint32 DTURACTL;                 //DTU Read Address Control Register
+    volatile uint32 DTUCFG;                   //DTU Configuration Control Register
+    volatile uint32 DTUECTL;                  //DTU Execute Control Register
+    volatile uint32 DTUWD0;                   //DTU Write Data 0
+    volatile uint32 DTUWD1;                   //DTU Write Data 1
+    volatile uint32 DTUWD2;                   //DTU Write Data 2
+    volatile uint32 DTUWD3;                   //DTU Write Data 3
+    volatile uint32 DTUWDM;                   //DTU Write Data Mask
+    volatile uint32 DTURD0;                   //DTU Read Data 0
+    volatile uint32 DTURD1;                   //DTU Read Data 1
+    volatile uint32 DTURD2;                   //DTU Read Data 2
+    volatile uint32 DTURD3;                   //DTU Read Data 3
+    volatile uint32 DTULFSRWD;                //DTU LFSR Seed for Write Data Generation
+    volatile uint32 DTULFSRRD;                //DTU LFSR Seed for Read Data Generation
+    volatile uint32 DTUEAF;                   //DTU Error Address FIFO
+    //DFI Control Registers
+    volatile uint32 DFITCTRLDELAY;            //DFI tctrl_delay Register
+    volatile uint32 DFIODTCFG;                //DFI ODT Configuration Register
+    volatile uint32 DFIODTCFG1;               //DFI ODT Configuration 1 Register
+    volatile uint32 DFIODTRANKMAP;            //DFI ODT Rank Mapping Register
+    //DFI Write Data Registers
+    volatile uint32 DFITPHYWRDATA;            //DFI tphy_wrdata Register
+    volatile uint32 DFITPHYWRLAT;             //DFI tphy_wrlat Register
+    uint32 reserved7[(0x260-0x258)/4];
+    volatile uint32 DFITRDDATAEN;             //DFI trddata_en Register
+    volatile uint32 DFITPHYRDLAT;             //DFI tphy_rddata Register
+    uint32 reserved8[(0x270-0x268)/4];
+    //DFI Update Registers
+    volatile uint32 DFITPHYUPDTYPE0;          //DFI tphyupd_type0 Register
+    volatile uint32 DFITPHYUPDTYPE1;          //DFI tphyupd_type1 Register
+    volatile uint32 DFITPHYUPDTYPE2;          //DFI tphyupd_type2 Register
+    volatile uint32 DFITPHYUPDTYPE3;          //DFI tphyupd_type3 Register
+    volatile uint32 DFITCTRLUPDMIN;           //DFI tctrlupd_min Register
+    volatile uint32 DFITCTRLUPDMAX;           //DFI tctrlupd_max Register
+    volatile uint32 DFITCTRLUPDDLY;           //DFI tctrlupd_dly Register
+    uint32 reserved9;
+    volatile uint32 DFIUPDCFG;                //DFI Update Configuration Register
+    volatile uint32 DFITREFMSKI;              //DFI Masked Refresh Interval Register
+    volatile uint32 DFITCTRLUPDI;             //DFI tctrlupd_interval Register
+    uint32 reserved10[(0x2ac-0x29c)/4];
+    volatile uint32 DFITRCFG0;                //DFI Training Configuration 0 Register
+    volatile uint32 DFITRSTAT0;               //DFI Training Status 0 Register
+    volatile uint32 DFITRWRLVLEN;             //DFI Training dfi_wrlvl_en Register
+    volatile uint32 DFITRRDLVLEN;             //DFI Training dfi_rdlvl_en Register
+    volatile uint32 DFITRRDLVLGATEEN;         //DFI Training dfi_rdlvl_gate_en Register
+    //DFI Status Registers
+    volatile uint32 DFISTSTAT0;               //DFI Status Status 0 Register
+    volatile uint32 DFISTCFG0;                //DFI Status Configuration 0 Register
+    volatile uint32 DFISTCFG1;                //DFI Status configuration 1 Register
+    uint32 reserved11;
+    volatile uint32 DFITDRAMCLKEN;            //DFI tdram_clk_enalbe Register
+    volatile uint32 DFITDRAMCLKDIS;           //DFI tdram_clk_disalbe Register
+    volatile uint32 DFISTCFG2;                //DFI Status configuration 2 Register
+    volatile uint32 DFISTPARCLR;              //DFI Status Parity Clear Register
+    volatile uint32 DFISTPARLOG;              //DFI Status Parity Log Register
+    uint32 reserved12[(0x2f0-0x2e4)/4];
+    //DFI Low Power Registers
+    volatile uint32 DFILPCFG0;                //DFI Low Power Configuration 0 Register
+    uint32 reserved13[(0x300-0x2f4)/4];
+    //DFI Training 2 Registers
+    volatile uint32 DFITRWRLVLRESP0;          //DFI Training dif_wrlvl_resp Status 0 Register
+    volatile uint32 DFITRWRLVLRESP1;          //DFI Training dif_wrlvl_resp Status 1 Register
+    volatile uint32 DFITRWRLVLRESP2;          //DFI Training dif_wrlvl_resp Status 2 Register
+    volatile uint32 DFITRRDLVLRESP0;          //DFI Training dif_rdlvl_resp Status 0 Register
+    volatile uint32 DFITRRDLVLRESP1;          //DFI Training dif_rdlvl_resp Status 1 Register
+    volatile uint32 DFITRRDLVLRESP2;          //DFI Training dif_rdlvl_resp Status 2 Register
+    volatile uint32 DFITRWRLVLDELAY0;         //DFI Training dif_wrlvl_delay Configuration 0 Register
+    volatile uint32 DFITRWRLVLDELAY1;         //DFI Training dif_wrlvl_delay Configuration 1 Register
+    volatile uint32 DFITRWRLVLDELAY2;         //DFI Training dif_wrlvl_delay Configuration 2 Register
+    volatile uint32 DFITRRDLVLDELAY0;         //DFI Training dif_rdlvl_delay Configuration 0 Register
+    volatile uint32 DFITRRDLVLDELAY1;         //DFI Training dif_rdlvl_delay Configuration 1 Register
+    volatile uint32 DFITRRDLVLDELAY2;         //DFI Training dif_rdlvl_delay Configuration 2 Register
+    volatile uint32 DFITRRDLVLGATEDELAY0;     //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
+    volatile uint32 DFITRRDLVLGATEDELAY1;     //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
+    volatile uint32 DFITRRDLVLGATEDELAY2;     //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
+    volatile uint32 DFITRCMD;                 //DFI Training Command Register
+    uint32 reserved14[(0x3f8-0x340)/4];
+    //IP Status Registers
+    volatile uint32 IPVR;                     //IP Version Register
+    volatile uint32 IPTR;                     //IP Type Register
+}DDR_REG_T, *pDDR_REG_T;
+
+//PHY_REG2
+#define PHY_AUTO_CALIBRATION (1<<0)
+#define PHY_SW_CALIBRATION   (1<<1)
+#define PHY_MEM_TYPE         (6)
+
+//PHY_REG22,25,26,27,28
+#define PHY_RON_DISABLE     (0)
+#define PHY_RON_309ohm      (1)
+#define PHY_RON_155ohm      (2)
+#define PHY_RON_103ohm      (3)
+#define PHY_RON_77ohm       (4)
+#define PHY_RON_63ohm       (5)
+#define PHY_RON_52ohm       (6)
+#define PHY_RON_45ohm       (7)
+//#define PHY_RON_77ohm       (8)
+#define PHY_RON_62ohm       (9)
+//#define PHY_RON_52ohm       (10)
+#define PHY_RON_44ohm       (11)
+#define PHY_RON_39ohm       (12)
+#define PHY_RON_34ohm       (13)
+#define PHY_RON_31ohm       (14)
+#define PHY_RON_28ohm       (15)
+
+#define PHY_RTT_DISABLE     (0)
+#define PHY_RTT_816ohm      (1)
+#define PHY_RTT_431ohm      (2)
+#define PHY_RTT_287ohm      (3)
+#define PHY_RTT_216ohm      (4)
+#define PHY_RTT_172ohm      (5)
+#define PHY_RTT_145ohm      (6)
+#define PHY_RTT_124ohm      (7)
+#define PHY_RTT_215ohm      (8)
+//#define PHY_RTT_172ohm      (9)
+#define PHY_RTT_144ohm      (10)
+#define PHY_RTT_123ohm      (11)
+#define PHY_RTT_108ohm      (12)
+#define PHY_RTT_96ohm       (13)
+#define PHY_RTT_86ohm       (14)
+#define PHY_RTT_78ohm       (15)
+
+/* DDR PHY register struct */
+typedef volatile struct DDRPHY_REG_Tag
+{
+    volatile uint32 PHY_REG1;               //PHY soft reset Register
+    volatile uint32 PHY_REG3;               //Burst type select Register
+    volatile uint32 PHY_REG2;               //PHY DQS squelch calibration Register
+    uint32 reserved1[(0x38-0x0a)/4];
+    volatile uint32 PHY_REG4a;              //CL,AL set register
+    volatile uint32 PHY_REG4b;              //dqs gata delay select bypass mode register
+    uint32 reserved2[(0x54-0x40)/4];
+    volatile uint32 PHY_REG16;              //
+    uint32 reserved3[(0x5c-0x58)/4];
+    volatile uint32 PHY_REG18;              //0x5c
+    volatile uint32 PHY_REG19;
+    uint32 reserved4[(0x68-0x64)/4];
+    volatile uint32 PHY_REG21;              //0x68
+    uint32 reserved5[(0x70-0x6c)/4];     
+    volatile uint32 PHY_REG22;              //0x70
+    uint32 reserved6[(0x80-0x74)/4];
+    volatile uint32 PHY_REG25;              //0x80
+    volatile uint32 PHY_REG26;
+    volatile uint32 PHY_REG27;
+    volatile uint32 PHY_REG28;
+    uint32 reserved7[(0xd4-0x90)/4];
+    volatile uint32 PHY_REG6;               //0xd4
+    volatile uint32 PHY_REG7;
+    uint32 reserved8[(0xe0-0xdc)/4];
+    volatile uint32 PHY_REG8;               //0xe0
+    volatile uint32 PHY_REG0e4;             //use for DQS ODT off
+    uint32 reserved9[(0x114-0xe8)/4];
+    volatile uint32 PHY_REG9;               //0x114
+    volatile uint32 PHY_REG10;
+    uint32 reserved10[(0x120-0x11c)/4];
+    volatile uint32 PHY_REG11;              //0x120
+    volatile uint32 PHY_REG124;             //use for DQS ODT off
+    uint32 reserved11[(0x1c0-0x128)/4];
+    volatile uint32 PHY_REG29;              //0x1c0
+    uint32 reserved12[(0x264-0x1c4)/4];
+       volatile uint32 PHY_REG264;             //use for phy soft reset
+       uint32 reserved13[(0x2b0-0x268)/4];
+    volatile uint32 PHY_REG2a;              //0x2b0
+    uint32 reserved14[(0x2c4-0x2b4)/4];
+//    volatile uint32 PHY_TX_DeSkew[24];        //0x2c4-0x320
+    volatile uint32 PHY_REG30;
+    volatile uint32 PHY_REG31;
+    volatile uint32 PHY_REG32;
+    volatile uint32 PHY_REG33;
+    volatile uint32 PHY_REG34;
+    volatile uint32 PHY_REG35;
+    volatile uint32 PHY_REG36;
+    volatile uint32 PHY_REG37;
+    volatile uint32 PHY_REG38;
+    volatile uint32 PHY_REG39;
+    volatile uint32 PHY_REG40;
+    volatile uint32 PHY_REG41;
+    volatile uint32 PHY_REG42;
+    volatile uint32 PHY_REG43;
+    volatile uint32 PHY_REG44;
+    volatile uint32 PHY_REG45;
+    volatile uint32 PHY_REG46;
+    volatile uint32 PHY_REG47;
+    volatile uint32 PHY_REG48;
+    volatile uint32 PHY_REG49;
+    volatile uint32 PHY_REG50;
+    volatile uint32 PHY_REG51;
+    volatile uint32 PHY_REG52;
+    volatile uint32 PHY_REG53;
+    uint32 reserved15[(0x328-0x324)/4];
+//    volatile uint32 PHY_RX_DeSkew[11];      //0x328-0x350
+    volatile uint32 PHY_REG54;
+    volatile uint32 PHY_REG55;
+    volatile uint32 PHY_REG56;
+    volatile uint32 PHY_REG57;
+    volatile uint32 PHY_REG58;
+    volatile uint32 PHY_REG59;
+    volatile uint32 PHY_REG5a;
+    volatile uint32 PHY_REG5b;
+    volatile uint32 PHY_REG5c;
+    volatile uint32 PHY_REG5d;
+    volatile uint32 PHY_REG5e;    
+    uint32 reserved16[(0x3c4-0x354)/4];
+    volatile uint32 PHY_REG5f;              //0x3c4
+    uint32 reserved17[(0x3e0-0x3c8)/4];
+    volatile uint32 PHY_REG60;
+    volatile uint32 PHY_REG61;
+    volatile uint32 PHY_REG62;            
+}DDRPHY_REG_T, *pDDRPHY_REG_T;
+
+#define pCRU_Reg               ((pCRU_REG)RK_CRU_VIRT)
+#define pGRF_Reg               ((pREG_FILE)RK_GRF_VIRT)
+#define pDDR_Reg               ((pDDR_REG_T)RK_DDR_VIRT)
+#define pPHY_Reg               ((pDDRPHY_REG_T)(RK_DDR_VIRT+RK3036_DDR_PCTL_SIZE))
+#define SysSrv_DdrTiming       (RK_CPU_AXI_BUS_VIRT+0xc)
+#define READ_CS_INFO()   ((((pGRF_Reg->GRF_OS_REG[1])>>11)&0x1)+1)
+#define READ_COL_INFO()  (9+(((pGRF_Reg->GRF_OS_REG[1])>>9)&0x3))
+#define READ_BK_INFO()   (3-(((pGRF_Reg->GRF_OS_REG[1])>>8)&0x1))
+#define READ_CS0_ROW_INFO()  (13+(((pGRF_Reg->GRF_OS_REG[1])>>6)&0x3))
+#define READ_CS1_ROW_INFO()  (13+(((pGRF_Reg->GRF_OS_REG[1])>>4)&0x3))
+#define READ_BW_INFO()   (2>>(((pGRF_Reg->GRF_OS_REG[1])&0xc)>>2))    //´úÂëÖÐ 0->8bit 1->16bit 2->32bit  ÓëgrfÖж¨ÒåÏà·´
+#define READ_DIE_BW_INFO()   (2>>((pGRF_Reg->GRF_OS_REG[1])&0x3))
+
+typedef enum PLL_ID_Tag
+{
+    APLL=0,
+    DPLL,
+    CPLL,
+    GPLL,
+    PLL_MAX
+}PLL_ID;
+
+typedef enum DRAM_TYPE_Tag
+{
+    LPDDR = 0,
+    DDR,
+    DDR2,
+    DDR3,
+    LPDDR2_S2,
+    LPDDR2_S4,
+
+    DRAM_MAX
+}DRAM_TYPE;
+
+struct ddr_freq_t {
+    unsigned long screen_ft_us;
+    unsigned long long t0;
+    unsigned long long t1;
+    unsigned long t2;
+};
+
+
+typedef struct PCTRL_TIMING_Tag
+{
+    uint32 ddrFreq;
+    //Memory Timing Registers
+    uint32 togcnt1u;               //Toggle Counter 1U Register
+    uint32 tinit;                  //t_init Timing Register
+    uint32 trsth;                  //Reset High Time Register
+    uint32 togcnt100n;             //Toggle Counter 100N Register
+    uint32 trefi;                  //t_refi Timing Register
+    uint32 tmrd;                   //t_mrd Timing Register
+    uint32 trfc;                   //t_rfc Timing Register
+    uint32 trp;                    //t_rp Timing Register
+    uint32 trtw;                   //t_rtw Timing Register
+    uint32 tal;                    //AL Latency Register
+    uint32 tcl;                    //CL Timing Register
+    uint32 tcwl;                   //CWL Register
+    uint32 tras;                   //t_ras Timing Register
+    uint32 trc;                    //t_rc Timing Register
+    uint32 trcd;                   //t_rcd Timing Register
+    uint32 trrd;                   //t_rrd Timing Register
+    uint32 trtp;                   //t_rtp Timing Register
+    uint32 twr;                    //t_wr Timing Register
+    uint32 twtr;                   //t_wtr Timing Register
+    uint32 texsr;                  //t_exsr Timing Register
+    uint32 txp;                    //t_xp Timing Register
+    uint32 txpdll;                 //t_xpdll Timing Register
+    uint32 tzqcs;                  //t_zqcs Timing Register
+    uint32 tzqcsi;                 //t_zqcsi Timing Register
+    uint32 tdqs;                   //t_dqs Timing Register
+    uint32 tcksre;                 //t_cksre Timing Register
+    uint32 tcksrx;                 //t_cksrx Timing Register
+    uint32 tcke;                   //t_cke Timing Register
+    uint32 tmod;                   //t_mod Timing Register
+    uint32 trstl;                  //Reset Low Timing Register
+    uint32 tzqcl;                  //t_zqcl Timing Register
+    uint32 tmrr;                   //t_mrr Timing Register
+    uint32 tckesr;                 //t_ckesr Timing Register
+    uint32 tdpd;                   //t_dpd Timing Register
+}PCTL_TIMING_T;
+
+struct ddr_change_freq_sram_param {
+    uint32 freq;
+    uint32 freq_slew;
+};
+
+
+typedef union NOC_TIMING_Tag
+{
+    uint32 d32;
+    struct 
+    {
+        unsigned ActToAct : 6;
+        unsigned RdToMiss : 6;
+        unsigned WrToMiss : 6;
+        unsigned BurstLen : 3;
+        unsigned RdToWr : 5;
+        unsigned WrToRd : 5;
+        unsigned BwRatio : 1;
+    } b;
+}NOC_TIMING_T;
+
+typedef struct BACKUP_REG_Tag
+{
+    PCTL_TIMING_T pctl_timing;
+    NOC_TIMING_T noc_timing;
+    uint32 ddrMR[4];
+    uint32 mem_type;
+    uint32 ddr_speed_bin;
+    uint32 ddr_capability_per_die;
+}BACKUP_REG_T;
+
+BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
+static BACKUP_REG_T *p_ddr_reg;
+
+uint32 DEFINE_PIE_DATA(ddr_freq);
+static uint32 *p_ddr_freq;
+uint32 DEFINE_PIE_DATA(ddr_sr_idle);
+uint32 DEFINE_PIE_DATA(ddr_dll_status);  // ¼Ç¼ddr dllµÄ״̬£¬ÔÚselfrefresh exitʱѡÔñÊÇ·ñ½øÐÐdll reset
+
+
+
+static uint32_t  ddr3_cl_cwl[22][4]={
+/*   0~330           330~400         400~533        speed
+* tCK  >3             2.5~3          1.875~2.5     1.875~1.5
+*    cl<<16, cwl    cl<<16, cwl     cl<<16, cwl              */
+    {((5<<16)|5),   ((5<<16)|5),    0          ,   0}, //DDR3_800D
+    {((5<<16)|5),   ((6<<16)|5),    0          ,   0}, //DDR3_800E
+
+    {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   0}, //DDR3_1066E
+    {((5<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   0}, //DDR3_1066F
+    {((5<<16)|5),   ((6<<16)|5),    ((8<<16)|6),   0}, //DDR3_1066G
+
+    {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((7<<16)|7)}, //DDR3_1333F
+    {((5<<16)|5),   ((5<<16)|5),    ((7<<16)|6),   ((8<<16)|7)}, //DDR3_1333G
+    {((5<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   ((9<<16)|7)}, //DDR3_1333H
+    {((5<<16)|5),   ((6<<16)|5),    ((8<<16)|6),   ((10<<16)|7)}, //DDR3_1333J
+
+    {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((7<<16)|7)}, //DDR3_1600G
+    {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((8<<16)|7)}, //DDR3_1600H
+    {((5<<16)|5),   ((5<<16)|5),    ((7<<16)|6),   ((9<<16)|7)}, //DDR3_1600J
+    {((5<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   ((10<<16)|7)}, //DDR3_1600K
+
+    {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((8<<16)|7)}, //DDR3_1866J
+    {((5<<16)|5),   ((5<<16)|5),    ((7<<16)|6),   ((8<<16)|7)}, //DDR3_1866K
+    {((6<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   ((9<<16)|7)}, //DDR3_1866L
+    {((6<<16)|5),   ((6<<16)|5),    ((8<<16)|6),   ((10<<16)|7)}, //DDR3_1866M
+
+    {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((7<<16)|7)}, //DDR3_2133K
+    {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((8<<16)|7)}, //DDR3_2133L
+    {((5<<16)|5),   ((5<<16)|5),    ((7<<16)|6),   ((9<<16)|7)}, //DDR3_2133M
+    {((6<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   ((9<<16)|7)},  //DDR3_2133N
+
+    {((6<<16)|5),   ((6<<16)|5),    ((8<<16)|6),   ((10<<16)|7)} //DDR3_DEFAULT
+
+};
+static uint32_t  ddr3_tRC_tFAW[22]={
+/**    tRC    tFAW   */
+    ((50<<16)|50), //DDR3_800D
+    ((53<<16)|50), //DDR3_800E
+
+    ((49<<16)|50), //DDR3_1066E
+    ((51<<16)|50), //DDR3_1066F
+    ((53<<16)|50), //DDR3_1066G
+
+    ((47<<16)|45), //DDR3_1333F
+    ((48<<16)|45), //DDR3_1333G
+    ((50<<16)|45), //DDR3_1333H
+    ((51<<16)|45), //DDR3_1333J
+
+    ((45<<16)|40), //DDR3_1600G
+    ((47<<16)|40), //DDR3_1600H
+    ((48<<16)|40), //DDR3_1600J
+    ((49<<16)|40), //DDR3_1600K
+
+    ((45<<16)|35), //DDR3_1866J
+    ((46<<16)|35), //DDR3_1866K
+    ((47<<16)|35), //DDR3_1866L
+    ((48<<16)|35), //DDR3_1866M
+
+    ((44<<16)|35), //DDR3_2133K
+    ((45<<16)|35), //DDR3_2133L
+    ((46<<16)|35), //DDR3_2133M
+    ((47<<16)|35), //DDR3_2133N
+
+    ((53<<16)|50)  //DDR3_DEFAULT
+};
+
+
+/****************************************************************************
+Internal sram us delay function
+Cpu highest frequency is 1.6 GHz
+1 cycle = 1/1.6 ns
+1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
+*****************************************************************************/
+//__sramdata volatile uint32 loops_per_us;
+volatile uint32 DEFINE_PIE_DATA(loops_per_us);
+#define LPJ_100MHZ  999456UL
+
+/*----------------------------------------------------------------------
+Name   : void __sramlocalfunc ddr_delayus(uint32_t us)
+Desc   : ddr ÑÓʱº¯Êý
+Params  : uint32_t us  --ÑÓʱʱ¼ä
+Return  : void
+Notes   : loops_per_us Ϊȫ¾Ö±äÁ¿ ÐèÒª¸ù¾Ýarm freq¶ø¶¨
+----------------------------------------------------------------------*/
+static void __sramfunc ddr_delayus(uint32 us)
+{
+    do
+    {
+        volatile unsigned int i = (DATA(loops_per_us)*us);
+        if (i < 7) i = 7;
+        barrier();
+        asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
+    } while (0);
+}
+
+
+/*----------------------------------------------------------------------
+Name   : __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
+Desc   : ddr ¿½±´¼Ä´æÆ÷º¯Êý
+Params  : pDest ->Ä¿±ê¼Ä´æÆ÷Ê×µØÖ·
+          pSrc  ->Ô´±ê¼Ä´æÆ÷Ê×µØÖ·
+          words ->¿½±´³¤¶È
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+
+static __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
+{
+    uint32 i;
+
+    for(i=0; i<words; i++)
+    {
+        pDest[i] = pSrc[i];
+    }
+}
+
+/*----------------------------------------------------------------------
+Name   : __sramfunc void ddr_move_to_Lowpower_state(void)
+Desc   : pctl ½øÈë lowpower state
+Params  : void
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+static __sramfunc void ddr_move_to_Lowpower_state(void)
+{
+    volatile uint32 value;
+
+    while(1)
+    {
+        value = pDDR_Reg->STAT.b.ctl_stat;
+        if(value == Low_power)
+        {
+            break;
+        }
+        switch(value)
+        {
+            case Init_mem:
+                pDDR_Reg->SCTL = CFG_STATE;
+                dsb();
+                while((pDDR_Reg->STAT.b.ctl_stat) != Config);
+            case Config:
+                pDDR_Reg->SCTL = GO_STATE;
+                dsb();
+                while((pDDR_Reg->STAT.b.ctl_stat) != Access);
+            case Access:
+                pDDR_Reg->SCTL = SLEEP_STATE;
+                dsb();
+                while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
+                break;
+            default:  //Transitional state
+                break;
+        }
+    }
+}
+
+/*----------------------------------------------------------------------
+Name   : __sramfunc void ddr_move_to_Access_state(void)
+Desc   : pctl ½øÈë Access state
+Params  : void
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+static __sramfunc void ddr_move_to_Access_state(void)
+{
+    volatile uint32 value;
+
+    //set auto self-refresh idle
+    //pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)| DATA(ddr_sr_idle) | (1<<31);
+       pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)| 0 | (1<<31);
+
+    while(1)
+    {
+        value = pDDR_Reg->STAT.b.ctl_stat;
+        if((value == Access)
+           || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
+        {
+            break;
+        }
+        switch(value)
+        {
+            case Low_power:
+                pDDR_Reg->SCTL = WAKEUP_STATE;
+                dsb();
+                while((pDDR_Reg->STAT.b.ctl_stat) != Access);
+                break;
+            case Init_mem:
+                pDDR_Reg->SCTL = CFG_STATE;
+                dsb();
+                while((pDDR_Reg->STAT.b.ctl_stat) != Config);
+            case Config:
+                pDDR_Reg->SCTL = GO_STATE;
+                dsb();
+                while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
+                      || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
+                break;
+            default:  //Transitional state
+                break;
+        }
+    }
+    pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
+}
+
+/*----------------------------------------------------------------------
+Name   : __sramfunc void ddr_move_to_Config_state(void)
+Desc   : pctl ½øÈë config state
+Params  : void
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+static __sramfunc void ddr_move_to_Config_state(void)
+{
+    volatile uint32 value;
+    pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
+    while(1)
+    {
+        value = pDDR_Reg->STAT.b.ctl_stat;
+        if(value == Config)
+        {          
+            break;
+        }
+        switch(value)
+        {
+            case Low_power:
+                pDDR_Reg->SCTL = WAKEUP_STATE;
+                dsb();
+            case Access:
+            case Init_mem:
+                pDDR_Reg->SCTL = CFG_STATE;
+                dsb();
+                break;
+            default:  //Transitional state
+                break;
+        }
+    }
+}
+
+/*----------------------------------------------------------------------
+Name   : void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
+Desc   : ͨ¹ýд pctl MCMD¼Ä´æÆ÷Ïòddr·¢ËÍÃüÁî
+Params  : rank ->ddr rank Êý
+          cmd  ->·¢ËÍÃüÁîÀàÐÍ
+          arg  ->·¢Ë͵ÄÊý¾Ý
+Return  : void 
+Notes   : arg°üÀ¨bank_addrºÍcmd_addr
+----------------------------------------------------------------------*/
+static void __sramfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
+{
+    pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
+    dsb();
+    while(pDDR_Reg->MCMD & start_cmd);
+}
+
+__sramdata uint32 copy_data[8]={0xffffffff,0x00000000,0x55555555,0xAAAAAAAA,
+                               0xEEEEEEEE,0x11111111,0x22222222,0xDDDDDDDD};/**/
+EXPORT_PIE_SYMBOL(copy_data[8]);
+static uint32 * p_copy_data;
+
+/*----------------------------------------------------------------------
+Name   : uint32_t __sramlocalfunc ddr_data_training(void)
+Desc   : ¶Ôddr×ödata training
+Params  : void
+Return  : void 
+Notes   : ûÓÐ×ödata trainingУÑé
+----------------------------------------------------------------------*/
+static uint32_t __sramfunc ddr_data_training(void)
+{
+    uint32 value;
+    value = pDDR_Reg->TREFI;
+    pDDR_Reg->TREFI = 0;
+    // trigger DTT
+    pPHY_Reg->PHY_REG2 = ((pPHY_Reg->PHY_REG2 & (~0x1)) | PHY_AUTO_CALIBRATION);
+    // wait echo byte DTDONE
+       dsb();
+//    ddr_delayus(1);
+    // stop DTT
+    while((pPHY_Reg->PHY_REG62 & 0x3)!=0x3);
+    pPHY_Reg->PHY_REG2 = (pPHY_Reg->PHY_REG2 & (~0x1));
+    // send some auto refresh to complement the lost while DTT
+    ddr_send_command(3, REF_cmd, 0);    
+    ddr_send_command(3, REF_cmd, 0);
+    ddr_send_command(3, REF_cmd, 0);    
+    ddr_send_command(3, REF_cmd, 0);
+
+    // resume auto refresh
+    pDDR_Reg->TREFI = value;
+
+    return(0);
+}
+
+/*----------------------------------------------------------------------
+Name    : void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
+Desc    : ÉèÖÃPHY dll ¹¤×÷ģʽ
+Params  : freq -> ddr¹¤×÷ƵÂÊ
+Return  : void 
+Notes   : 
+----------------------------------------------------------------------*/
+static void __sramfunc ddr_set_dll_bypass(uint32 freq)
+{
+    if(freq <= PHY_DLL_DISABLE_FREQ)
+    {
+        pPHY_Reg->PHY_REG2a = 0x1F;         //set cmd,left right dll bypass
+        pPHY_Reg->PHY_REG19 = 0x08;         //cmd slave dll
+        pPHY_Reg->PHY_REG6 = 0x18;          //left TX DQ DLL
+        pPHY_Reg->PHY_REG7 = 0x00;          //left TX DQS DLL
+        pPHY_Reg->PHY_REG9 = 0x18;          //right TX DQ DLL
+        pPHY_Reg->PHY_REG10 = 0x00;         //right TX DQS DLL
+        
+    }
+    else 
+    {
+        pPHY_Reg->PHY_REG2a = 0x03;         //set cmd,left right dll bypass
+        pPHY_Reg->PHY_REG19 = 0x08;         //cmd slave dll
+        pPHY_Reg->PHY_REG6 = 0x0c;          //left TX DQ DLL
+        pPHY_Reg->PHY_REG7 = 0x00;          //left TX DQS DLL
+        pPHY_Reg->PHY_REG9 = 0x0c;          //right TX DQ DLL
+        pPHY_Reg->PHY_REG10 = 0x00;         //right TX DQS DLL                
+    }
+    dsb();
+    //ÆäËûÓëdllÏà¹ØµÄ¼Ä´æÆ÷ÓÐ:REG8(RX DQS),REG11(RX DQS),REG18(CMD),REG21(CK) ±£³ÖĬÈÏÖµ
+}
+
+static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id)   //APLL-1;CPLL-2;DPLL-3;GPLL-4
+{
+    uint32 ret = 0; 
+
+    // freq = (fin*fbdiv/(refdiv * postdiv1 * postdiv2))
+    if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&1) == 1)             // DPLL Normal mode
+        ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0xfff))    // NF = 2*(CLKF+1)
+                /((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0x3f)
+                *((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>12)&0x7)*((pCRU_Reg->CRU_PLL_CON[pll_id][1]>>6)&0x7));             // OD = 2^CLKOD
+    else
+        ret = 24;
+
+    return ret;
+}
+
+static __sramdata uint32 clkFbDiv;
+static __sramdata uint32 clkPostDiv1;
+static __sramdata uint32 clkPostDiv2;
+
+/*****************************************
+REFDIV   FBDIV     POSTDIV1/POSTDIV2      FOUTPOSTDIV           freq Step        FOUTPOSRDIV            finally use
+==================================================================================================================
+1        17 - 66   4                      100MHz - 400MHz          6MHz          200MHz  <= 300MHz             <= 150MHz
+1        17 - 66   3                      133MHz - 533MHz          8MHz             
+1        17 - 66   2                      200MHz - 800MHz          12MHz         300MHz  <= 600MHz      150MHz <= 300MHz
+1        17 - 66   1                      400MHz - 1600MHz         24MHz         600MHz  <= 1200MHz     300MHz <= 600MHz
+******************************************/
+//for minimum jitter operation, the highest VCO and FREF frequencies should be used.
+/*----------------------------------------------------------------------
+Name    : uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
+Desc    : ÉèÖÃddr pll
+Params  : nMHZ -> ddr¹¤×÷ƵÂÊ
+          set  ->0»ñÈ¡ÉèÖõÄƵÂÊÐÅÏ¢
+                 1ÉèÖÃddr pll
+Return  : ÉèÖõÄƵÂÊÖµ 
+Notes   : ÔÚ±äƵʱÐèÒªÏÈset=0µ÷ÓÃÒ»´Îddr_set_pll£¬ÔÙset=1 µ÷ÓÃddr_set_pll
+----------------------------------------------------------------------*/
+static uint32 __sramfunc ddr_set_pll(uint32 nMHz, uint32 set)
+{
+    uint32 ret = 0;
+    int delay = 1000;
+    uint32 pll_id=1;  //DPLL     
+    
+    if(nMHz == 24)
+    {
+        ret = 24;
+        goto out;
+    }
+    if(!set)
+    {
+        if(nMHz <= 150) //ʵ¼ÊÊä³öƵÂÊ<300
+        {
+            clkPostDiv1 = 6;
+        }
+        else if(nMHz <=200)
+        {
+            clkPostDiv1 = 4;
+        }
+        else if(nMHz <= 300)
+        {
+            clkPostDiv1 = 3;
+        }
+        else if(nMHz <=450)
+        {
+            clkPostDiv1 = 2;
+        }
+        else
+        {
+            clkPostDiv1 = 1;
+        }
+        clkPostDiv2 = 1;
+        clkFbDiv = (nMHz * 2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2)/24;//×îºóËÍÈëddrµÄÊÇÔÙ¾­¹ý2·ÖƵ
+        ret = (24 * clkFbDiv)/(2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2);
+    }
+    else
+    {
+        pCRU_Reg->CRU_MODE_CON = (0x1<<((pll_id*4) +  16)) | (0x0<<(pll_id*4));            //PLL slow-mode
+    
+        pCRU_Reg->CRU_PLL_CON[pll_id][0] = FBDIV(clkFbDiv) | POSTDIV1(clkPostDiv1);
+        pCRU_Reg->CRU_PLL_CON[pll_id][1] = REFDIV(DDR_PLL_REFDIV) | POSTDIV2(clkPostDiv2) | (0x10001<<12);//interger mode
+
+        ddr_delayus(1);
+
+        while (delay > 0) 
+        {
+           ddr_delayus(1);
+               if (pCRU_Reg->CRU_PLL_CON[pll_id][1] & (PLL_LOCK_STATUS))        // wait for pll locked
+                       break;
+               delay--;
+       }
+        
+        pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3<<16) | 0x0);           //clk_ddr_src:clk_ddrphy = 1:1       
+        pCRU_Reg->CRU_MODE_CON = (0x1<<((pll_id*4) +  16))  | (0x1<<(pll_id*4));            //PLL normal
+    }
+out:
+    return ret;
+}
+
+uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
+{
+    return ddr_set_pll(nMHz,set);
+}
+EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
+
+/*----------------------------------------------------------------------
+Name    : uint32_t ddr_get_parameter(uint32_t nMHz)
+Desc    : »ñÈ¡ÅäÖòÎÊý
+Params  : nMHZ -> ddr¹¤×÷ƵÂÊ     
+Return  : 0 ³É¹¦
+          -1 ʧ°Ü
+          -4 ƵÂÊÖµ³¬¹ý¿ÅÁ£×î´óƵÂÊ
+Notes   : 
+----------------------------------------------------------------------*/
+static uint32 ddr_get_parameter(uint32 nMHz)
+{
+    uint32_t tmp;
+    uint32_t ret = 0;
+    uint32_t al;
+    uint32_t bl;
+    uint32_t cl;
+    uint32_t cwl;    
+    PCTL_TIMING_T *p_pctl_timing = &(p_ddr_reg->pctl_timing);
+    NOC_TIMING_T  *p_noc_timing=&(p_ddr_reg->noc_timing);
+
+    p_pctl_timing->togcnt1u = nMHz;
+    p_pctl_timing->togcnt100n = nMHz/10;
+    p_pctl_timing->tinit = 200;
+    p_pctl_timing->trsth = 500;
+
+    if(p_ddr_reg->mem_type == DDR3)
+    {
+        if(p_ddr_reg->ddr_speed_bin > DDR3_DEFAULT)
+        {
+            ret = -1;
+            goto out;
+        }
+
+        #define DDR3_tREFI_7_8_us    (78)
+        #define DDR3_tMRD            (4)
+        #define DDR3_tRFC_512Mb      (90)
+        #define DDR3_tRFC_1Gb        (110)
+        #define DDR3_tRFC_2Gb        (160)
+        #define DDR3_tRFC_4Gb        (300)
+        #define DDR3_tRFC_8Gb        (350)
+        #define DDR3_tRTW            (2)   //register min valid value
+        #define DDR3_tRAS            (37)
+        #define DDR3_tRRD            (10)
+        #define DDR3_tRTP            (7)
+        #define DDR3_tWR             (15)
+        #define DDR3_tWTR            (7)
+        #define DDR3_tXP             (7)
+        #define DDR3_tXPDLL          (24)
+        #define DDR3_tZQCS           (80)
+        #define DDR3_tZQCSI          (10000)
+        #define DDR3_tDQS            (1)
+        #define DDR3_tCKSRE          (10)
+        #define DDR3_tCKE_400MHz     (7)
+        #define DDR3_tCKE_533MHz     (6)
+        #define DDR3_tMOD            (15)
+        #define DDR3_tRSTL           (100)
+        #define DDR3_tZQCL           (320)
+        #define DDR3_tDLLK           (512)
+
+        al = 0;
+        bl = 8;
+        if(nMHz <= 330)
+        {
+            tmp = 0;
+        }
+        else if(nMHz<=400)
+        {
+            tmp = 1;
+        }
+        else if(nMHz<=533)
+        {
+            tmp = 2;
+        }
+        else //666MHz
+        {
+            tmp = 3;
+        }
+        if(nMHz < DDR3_DDR2_DLL_DISABLE_FREQ)       //when dll bypss cl = cwl = 6;
+        {
+            cl = 6;
+            cwl = 6;
+        }
+        else
+        {
+            cl = ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] >> 16;
+            cwl = ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] & 0x0ff;
+        }
+        if(cl == 0)
+        {
+            ret = -4; //³¬¹ý¿ÅÁ£µÄ×î´óƵÂÊ
+        }
+        if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)     
+        {
+            p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
+        }
+        else
+        {
+            p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
+        }
+        p_ddr_reg->ddrMR[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
+        p_ddr_reg->ddrMR[3] = 0;
+        /**************************************************
+         * PCTL Timing
+         **************************************************/
+        /*
+         * tREFI, average periodic refresh interval, 7.8us
+         */
+        p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
+        /*
+         * tMRD, 4 tCK
+         */
+        p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
+        /*
+         * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
+         */
+        if(p_ddr_reg->ddr_capability_per_die <= 0x4000000)         // 512Mb 90ns
+        {
+            tmp = DDR3_tRFC_512Mb;
+        }
+        else if(p_ddr_reg->ddr_capability_per_die <= 0x8000000)    // 1Gb 110ns
+        {
+            tmp = DDR3_tRFC_1Gb;
+        }
+        else if(p_ddr_reg->ddr_capability_per_die <= 0x10000000)   // 2Gb 160ns
+        {
+            tmp = DDR3_tRFC_2Gb;
+        }
+        else if(p_ddr_reg->ddr_capability_per_die <= 0x20000000)   // 4Gb 300ns
+        {
+            tmp = DDR3_tRFC_4Gb;
+        }
+        else    // 8Gb  350ns
+        {
+            tmp = DDR3_tRFC_8Gb;
+        }
+        p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
+        /*
+         * tXSR, =tDLLK=512 tCK
+         */
+        p_pctl_timing->texsr = DDR3_tDLLK;
+        /*
+         * tRP=CL
+         */
+        p_pctl_timing->trp = cl;
+        /*
+         * WrToMiss=WL*tCK + tWR + tRP + tRCD
+         */
+        p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
+        /*
+         * tRC=tRAS+tRP
+         */
+        p_pctl_timing->trc = ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
+        p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
+
+        p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
+        p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
+        p_pctl_timing->tal = al;
+        p_pctl_timing->tcl = cl;
+        p_pctl_timing->tcwl = cwl;
+        /*
+         * tRAS, 37.5ns(400MHz)     37.5ns(533MHz)
+         */
+        p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
+        /*
+         * tRCD=CL
+         */
+        p_pctl_timing->trcd = cl;
+        /*
+         * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
+         *        max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
+         *        max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
+         *
+         */
+        tmp = ((DDR3_tRRD*nMHz+999)/1000);
+        if(tmp < 4)
+        {
+            tmp = 4;
+        }
+        p_pctl_timing->trrd = (tmp&0xF);
+        /*
+         * tRTP, max(4 tCK,7.5ns)
+         */
+        tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
+        if(tmp < 4)
+        {
+            tmp = 4;
+        }
+        p_pctl_timing->trtp = tmp&0xF;
+        /*
+         * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
+         */
+        p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
+        /*
+         * tWR, 15ns
+         */
+        tmp = ((DDR3_tWR*nMHz+999)/1000);
+        p_pctl_timing->twr = tmp&0x1F;
+        if(tmp<9)
+            tmp = tmp - 4;
+        else
+            tmp = tmp>>1;
+        p_ddr_reg->ddrMR[0] = DDR3_BL8 | DDR3_CL(cl) | DDR3_WR(tmp);
+
+        /*
+         * tWTR, max(4 tCK,7.5ns)
+         */
+        tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
+        if(tmp < 4)
+        {
+            tmp = 4;
+        }
+        p_pctl_timing->twtr = tmp&0xF;
+        p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
+        /*
+         * tXP, max(3 tCK, 7.5ns)(<933MHz)
+         */
+        tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
+        if(tmp < 3)
+        {
+            tmp = 3;
+        }
+        p_pctl_timing->txp = tmp&0x7;
+        /*
+         * tXPDLL, max(10 tCK,24ns)
+         */
+        tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
+        if(tmp < 10)
+        {
+            tmp = 10;
+        }
+        p_pctl_timing->txpdll = tmp & 0x3F;
+        /*
+         * tZQCS, max(64 tCK, 80ns)
+         */
+        tmp = ((DDR3_tZQCS*nMHz+999)/1000);
+        if(tmp < 64)
+        {
+            tmp = 64;
+        }
+        p_pctl_timing->tzqcs = tmp&0x7F;
+        /*
+         * tZQCSI,
+         */
+        p_pctl_timing->tzqcsi = DDR3_tZQCSI;
+        /*
+         * tDQS,
+         */
+        p_pctl_timing->tdqs = DDR3_tDQS;
+        /*
+         * tCKSRE, max(5 tCK, 10ns)
+         */
+        tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
+        if(tmp < 5)
+        {
+            tmp = 5;
+        }
+        p_pctl_timing->tcksre = tmp & 0x1F;
+        /*
+         * tCKSRX, max(5 tCK, 10ns)
+         */
+        p_pctl_timing->tcksrx = tmp & 0x1F;
+        /*
+         * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
+         */
+        if(nMHz>=533)
+        {
+            tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
+        }
+        else
+        {
+            tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
+        }
+        if(tmp < 3)
+        {
+            tmp = 3;
+        }
+        p_pctl_timing->tcke = tmp & 0x7;
+        /*
+         * tCKESR, =tCKE + 1tCK
+         */
+        p_pctl_timing->tckesr = (tmp+1)&0xF;
+        /*
+         * tMOD, max(12 tCK,15ns)
+         */
+        tmp = ((DDR3_tMOD*nMHz+999)/1000);
+        if(tmp < 12)
+        {
+            tmp = 12;
+        }
+        p_pctl_timing->tmod = tmp&0x1F;
+        /*
+         * tRSTL, 100ns
+         */
+        p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
+        /*
+         * tZQCL, max(256 tCK, 320ns)
+         */
+        tmp = ((DDR3_tZQCL*nMHz+999)/1000);
+        if(tmp < 256)
+        {
+            tmp = 256;
+        }
+        p_pctl_timing->tzqcl = tmp&0x3FF;
+        /*
+         * tMRR, 0 tCK
+         */
+        p_pctl_timing->tmrr = 0;
+        /*
+         * tDPD, 0
+         */
+        p_pctl_timing->tdpd = 0;
+
+        /**************************************************
+         * NOC Timing
+         **************************************************/
+        p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
+    }
+    else
+    {
+        ret = -1;
+    }
+        
+out:
+    return ret;
+}
+
+/*----------------------------------------------------------------------
+Name    : uint32_t __sramlocalfunc ddr_update_timing(void)
+Desc    : ¸üÐÂpctl phy Ïà¹Øtiming¼Ä´æÆ÷
+Params  : void  
+Return  : 0 ³É¹¦
+Notes   : 
+----------------------------------------------------------------------*/
+static uint32 __sramfunc ddr_update_timing(void)
+{
+    PCTL_TIMING_T *p_pctl_timing = &(DATA(ddr_reg).pctl_timing);
+    NOC_TIMING_T  *p_noc_timing = &(DATA(ddr_reg).noc_timing);
+
+    ddr_copy((uint32 *)&(pDDR_Reg->TOGCNT1U), (uint32*)&(p_pctl_timing->togcnt1u), 34);
+    pPHY_Reg->PHY_REG3 = (0x12 << 1) | (ddr2_ddr3_bl_8);   //0x12Ϊ±£ÁôλµÄĬÈÏÖµ£¬ÒÔĬÈÏÖµ»Øд
+    pPHY_Reg->PHY_REG4a = ((p_pctl_timing->tcl << 4) | (p_pctl_timing->tal));
+    *(volatile uint32 *)SysSrv_DdrTiming = p_noc_timing->d32;
+    // Update PCTL BL
+//    if(DATA(ddr_reg).mem_type == DDR3)
+    {
+        pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | ddr2_ddr3_bl_8 | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
+        pDDR_Reg->DFITRDDATAEN   = (pDDR_Reg->TAL + pDDR_Reg->TCL)-3;  //trdata_en = rl-3
+        pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL-1;
+    }
+    return 0;
+}
+
+/*----------------------------------------------------------------------
+Name    : uint32_t __sramlocalfunc ddr_update_mr(void)
+Desc    : ¸üпÅÁ£MR¼Ä´æÆ÷
+Params  : void  
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+static uint32 __sramfunc ddr_update_mr(void)
+{
+    uint32 cs;
+
+    cs = READ_CS_INFO();
+    cs = cs + (1 << cs);                               //case 0:1rank cs=1; case 1:2rank cs =3;
+    if(DATA(ddr_freq) > DDR3_DDR2_DLL_DISABLE_FREQ)
+    {
+        if(DATA(ddr_dll_status) == DDR3_DLL_DISABLE)  // off -> on
+        {
+            ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((DATA(ddr_reg).ddrMR[1])));  //DLL enable
+            ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((DATA(ddr_reg).ddrMR[0]))| DDR3_DLL_RESET));  //DLL reset
+            ddr_delayus(2);  //at least 200 DDR cycle
+            ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((DATA(ddr_reg).ddrMR[0])));
+            DATA(ddr_dll_status) = DDR3_DLL_ENABLE;
+        }
+        else // on -> on
+        {
+            ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((DATA(ddr_reg).ddrMR[1])));
+            ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((DATA(ddr_reg).ddrMR[0])));
+        }
+    }
+    else
+    {
+        ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((DATA(ddr_reg).ddrMR[1])) | DDR3_DLL_DISABLE));  //DLL disable
+        ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((DATA(ddr_reg).ddrMR[0])));
+        DATA(ddr_dll_status) = DDR3_DLL_DISABLE;
+    }
+    ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((DATA(ddr_reg).ddrMR[2])));
+
+    return 0;
+}
+
+/*----------------------------------------------------------------------
+Name    : void __sramlocalfunc ddr_update_odt(void)
+Desc    : update PHY odt & PHY driver impedance
+Params  : void  
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+static void __sramfunc ddr_update_odt(void)
+{
+    uint32 tmp;
+    
+    //adjust DRV and ODT
+    if(DATA(ddr_freq) <= PHY_ODT_DISABLE_FREQ)
+    {
+        pPHY_Reg->PHY_REG27 = PHY_RTT_DISABLE;  //dynamic RTT disable, Left 8bit ODT
+        pPHY_Reg->PHY_REG28 = PHY_RTT_DISABLE;  //Right 8bit ODT
+        pPHY_Reg->PHY_REG0e4 = (0x0E & 0xc)|0x1;//off DQS ODT  bit[1:0]=2'b01 
+        pPHY_Reg->PHY_REG124 = (0x0E & 0xc)|0x1;//off DQS ODT  bit[1:0]=2'b01 
+    }
+    else
+    {
+        pPHY_Reg->PHY_REG27 = ((PHY_RTT_215ohm<<4) | PHY_RTT_215ohm);       
+        pPHY_Reg->PHY_REG28 = ((PHY_RTT_215ohm<<4) | PHY_RTT_215ohm);    
+        pPHY_Reg->PHY_REG0e4 = 0x0E;           //on DQS ODT default:0x0E
+        pPHY_Reg->PHY_REG124 = 0x0E;           //on DQS ODT default:0x0E
+    }
+
+    tmp = ((PHY_RON_45ohm<<4) | PHY_RON_45ohm);     
+    pPHY_Reg->PHY_REG16 = tmp;  //CMD driver strength
+    pPHY_Reg->PHY_REG22 = tmp;  //CK driver strength    
+    pPHY_Reg->PHY_REG25 = tmp;  //Left 8bit DQ driver strength
+    pPHY_Reg->PHY_REG26 = tmp;  //Right 8bit DQ driver strength
+    dsb();
+}
+
+/*----------------------------------------------------------------------
+Name    : __sramfunc void ddr_adjust_config(uint32_t dram_type)
+Desc    : 
+Params  : dram_type ->¿ÅÁ£ÀàÐÍ
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+#if 0
+__sramfunc void ddr_adjust_config(uint32_t dram_type)
+{
+//    uint32 value;
+    unsigned long save_sp;
+    uint32 i;
+    volatile uint32 n; 
+    volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
+
+    //get data training address before idle port
+//    value = ddr_get_datatraing_addr();    //Inno PHY ²»ÐèÒªtraining address
+
+    /** 1. Make sure there is no host access */
+    flush_cache_all();
+    outer_flush_all();
+    flush_tlb_all();
+    DDR_SAVE_SP(save_sp);
+
+    for(i=0;i<2;i++)        //8KB SRAM
+    {
+        n=temp[1024*i];
+        barrier();
+    }
+    n= pDDR_Reg->SCFG.d32;
+    n= pPHY_Reg->PHY_REG1;
+    n= pCRU_Reg->CRU_PLL_CON[0][0];
+    n= *(volatile uint32_t *)SysSrv_DdrTiming;
+    dsb();
+    
+    //enter config state
+    ddr_move_to_Config_state();
+//    pDDR_Reg->DFIODTCFG = ((1<<3) | (1<<11));  //loaderÖЩÁ˳õʼ»¯
+    pPHY_Reg->PHY_REG5d = 0X77;
+    pPHY_Reg->PHY_REG5e = 0X77;
+    //set auto power down idle
+    pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
+
+    //enable the hardware low-power interface
+    pDDR_Reg->SCFG.b.hw_low_power_en = 1;
+
+    ddr_update_odt();
+
+    //enter access state
+    ddr_move_to_Access_state();
+
+    DDR_RESTORE_SP(save_sp);
+}
+#endif 
+
+static void __sramfunc idle_port(void)
+{
+    int i;
+    uint32 clk_gate[10];
+
+    //save clock gate status
+    for(i=0;i<10;i++)
+    {
+        clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
+    }
+    //enable all clock gate for request idle
+    for(i=0;i<10;i++)
+    {
+        pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
+    }
+
+    pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+peri_pwr_idlereq))+(1 << peri_pwr_idlereq);         //peri   bit 12
+    dsb();
+    while( (pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) == 0);//   bit 23
+
+    pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vio_pwr_idlereq))+(1 << vio_pwr_idlereq);          //vio
+    dsb();
+    while( (pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) == 0);
+  
+    pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vpu_pwr_idlereq))+(1 << vpu_pwr_idlereq);          //vpu
+    dsb();
+    while( (pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) == 0);
+      
+    pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+gpu_pwr_idlereq))+(1 << gpu_pwr_idlereq);          //gpu
+    dsb();
+    while( (pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) == 0);
+    
+       //resume clock gate status
+    for(i=0;i<10;i++)
+        pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
+}
+
+
+static void __sramfunc deidle_port(void)
+{
+    int i;
+    uint32 clk_gate[10];
+
+    //save clock gate status
+    for(i=0;i<10;i++)
+    {
+        clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
+    }
+    //enable all clock gate for request idle
+    for(i=0;i<10;i++)
+    {
+        pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
+    }
+   
+    pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+peri_pwr_idlereq))+(0 << peri_pwr_idlereq);         //peri   bit 12
+    dsb();
+    while( (pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) != 0);
+
+    pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vio_pwr_idlereq))+(0 << vio_pwr_idlereq);          //vio
+    dsb();
+    while( (pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) != 0);
+      
+    pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vpu_pwr_idlereq))+(0 << vpu_pwr_idlereq);          //vpu
+    dsb();
+    while( (pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) != 0);
+        
+    pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+gpu_pwr_idlereq))+(0 << gpu_pwr_idlereq);          //gpu
+    dsb();
+    while( (pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) != 0);
+    
+    //resume clock gate status
+    for(i=0;i<10;i++)
+        pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
+
+}
+
+
+
+/*----------------------------------------------------------------------
+Name    : void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
+Desc    : ½øÈë×ÔË¢ÐÂ
+Params  : nMHz ->ddrƵÂÊ
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+/*
+static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
+{    
+    ddr_move_to_Config_state();
+    ddr_move_to_Lowpower_state();
+       pPHY_Reg->PHY_REG264 &= ~(1<<1);
+    pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2)));     //phy soft reset
+    dsb();
+    pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2);  //disable DDR PHY clock
+    ddr_delayus(1);
+}
+*/
+static uint32 dtt_buffer[8];
+
+/*----------------------------------------------------------------------
+Name    : void ddr_dtt_check(void)
+Desc    : data training check
+Params  : void
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+static void ddr_dtt_check(void)
+{
+    uint32 i;
+    for(i=0;i<8;i++)
+    {
+        dtt_buffer[i] = p_copy_data[i];
+    }
+    dsb();
+    flush_cache_all();
+    outer_flush_all();
+    for(i=0;i<8;i++)
+    {
+        if(dtt_buffer[i] != p_copy_data[i])
+        {
+//            sram_printascii("DTT failed!\n");
+            break;
+        }
+        dtt_buffer[i] = 0;
+    }
+
+}
+
+/*----------------------------------------------------------------------
+Name    : void __sramlocalfunc ddr_selfrefresh_exit(void)
+Desc    : Í˳ö×ÔË¢ÐÂ
+Params  : void
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+#if 0
+static void __sramfunc ddr_selfrefresh_exit(void)
+{
+    pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2);  //enable DDR PHY clock
+    dsb();
+    ddr_delayus(1);
+       pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
+       pPHY_Reg->PHY_REG264 |= (1<<1);
+       dsb();
+    ddr_move_to_Config_state();    
+    ddr_data_training(); 
+    ddr_move_to_Access_state();
+//    ddr_dtt_check();
+}
+#endif
+/*----------------------------------------------------------------------
+Name    : void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
+Desc    : ÉèÖÃddr pllÇ°µÄtiming¼°mr²ÎÊýµ÷Õû
+Params  : freq_slew :±äƵбÂÊ 1Éýƽ  0½µÆµ
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+static void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
+{
+    uint32 value_100n, value_1u;
+    
+    if(freq_slew == 1)
+    {
+        value_100n = DATA(ddr_reg).pctl_timing.togcnt100n;
+        value_1u = DATA(ddr_reg).pctl_timing.togcnt1u;
+        DATA(ddr_reg).pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
+        DATA(ddr_reg).pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
+        ddr_update_timing();                
+        ddr_update_mr();
+        DATA(ddr_reg).pctl_timing.togcnt100n = value_100n;
+        DATA(ddr_reg).pctl_timing.togcnt1u = value_1u;
+    }
+    else
+    {
+        pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
+        pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
+    }
+
+    pDDR_Reg->TZQCSI = 0;    
+
+}
+
+
+
+/*----------------------------------------------------------------------
+Name    : void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
+Desc    : ÉèÖÃddr pllºóµÄtiming¼°mr²ÎÊýµ÷Õû
+Params  : freq_slew :±äƵбÂÊ 1Éýƽ  0½µÆµ
+Return  : void
+Notes   : 
+----------------------------------------------------------------------*/
+static void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
+{
+    if(freq_slew == 1)
+    {
+        pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
+        pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
+        pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl_timing.tzqcsi;
+    }
+    else
+    {
+        ddr_update_timing();
+        ddr_update_mr();
+    }
+    ddr_data_training();
+}
+
+static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew)
+{
+    idle_port();
+
+    ddr_move_to_Config_state(); 
+    DATA(ddr_freq) = freq;
+    ddr_change_freq_in(freq_slew);
+    ddr_move_to_Lowpower_state();
+    pPHY_Reg->PHY_REG264 &= ~(1<<1);
+    pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2)));     //phy soft reset
+    dsb();    
+    /** 3. change frequence  */
+    FUNC(ddr_set_pll)(freq,1);
+    ddr_set_dll_bypass(freq);    //set phy dll mode;
+       pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
+       pPHY_Reg->PHY_REG264 |= (1<<1);
+       dsb();
+       ddr_update_odt();
+    ddr_move_to_Config_state();
+    ddr_change_freq_out(freq_slew);
+    ddr_move_to_Access_state();
+
+    deidle_port();
+}
+
+void PIE_FUNC(ddr_change_freq_sram)(void *arg)
+{
+    struct ddr_change_freq_sram_param *param = arg;  
+    /* Make sure ddr_SRE_2_SRX paramter less than 4 */
+    ddr_SRE_2_SRX(param->freq, param->freq_slew);
+}
+EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
+
+/*----------------------------------------------------------------------
+Name    : uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
+Desc    : ddr±äƵ
+Params  : nMHz -> ±äƵµÄƵÂÊÖµ
+Return  : ƵÂÊÖµ
+Notes   :
+----------------------------------------------------------------------*/
+static uint32 ddr_change_freq_sram(uint32 nMHz, struct ddr_freq_t ddr_freq_t)
+{
+    uint32 ret;
+    uint32 i;
+    volatile uint32 n; 
+    unsigned long flags;
+    volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
+
+    struct ddr_change_freq_sram_param param;
+    //uint32 freq;
+       uint32 freq_slew;
+       uint32 arm_freq;
+       
+    arm_freq= ddr_get_pll_freq(APLL);   
+    *kern_to_pie(rockchip_pie_chunk, &DATA(loops_per_us)) = LPJ_100MHZ*arm_freq/1000000;  
+    ret =(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll)))(nMHz,0);
+    if(ret == *p_ddr_freq)
+    {
+        goto out;
+    }
+    else 
+    {
+        freq_slew = (ret > *p_ddr_freq)? 1 : -1;
+    }    
+    ddr_get_parameter(ret);
+    //*kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq))= ret;
+    /** 1. Make sure there is no host access */
+    local_irq_save(flags);
+       local_fiq_disable();
+    flush_cache_all();
+       outer_flush_all();
+       flush_tlb_all();
+       //DDR_SAVE_SP(save_sp);
+       
+#if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)  
+        n = ddr_freq_t.screen_ft_us;
+        n = ddr_freq_t.t0;
+        dsb();
+    
+        if(ddr_freq_t.screen_ft_us > 0){
+    
+            ddr_freq_t.t1 = cpu_clock(0);
+            ddr_freq_t.t2 = (u32)(ddr_freq_t.t1 - ddr_freq_t.t0);   //ns
+    
+    
+            if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe)){
+            
+            //DDR_RESTORE_SP(save_sp);
+            local_fiq_enable();
+            local_irq_restore(flags);
+            return 0;
+            }else{                      
+                rk_fb_poll_wait_frame_complete();
+            }
+        }
+#endif
+
+       for(i=0;i<2;i++)    //8KB SRAM
+       {
+           n=temp[1024*i];
+        barrier();
+       }
+    n= pDDR_Reg->SCFG.d32;
+    n= pPHY_Reg->PHY_REG1;
+    n= pCRU_Reg->CRU_PLL_CON[0][0];
+    n= *(volatile uint32_t *)SysSrv_DdrTiming;
+    n= pGRF_Reg->GRF_SOC_STATUS0;
+    dsb();
+    param.freq = ret;
+    param.freq_slew = freq_slew;
+    call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
+                    &param,
+                    rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
+    /** 5. Issues a Mode Exit command   */
+   // DDR_RESTORE_SP(save_sp);
+    ddr_dtt_check();
+    local_fiq_enable();
+    local_irq_restore(flags);
+//    clk_set_rate(clk_get(NULL, "ddr_pll"), 0);    
+out:
+    return ret;
+}
+
+static uint32 _ddr_change_freq_3036(uint32_t nMHz)
+{
+       struct ddr_freq_t ddr_freq_t;
+       ddr_freq_t.screen_ft_us = 0;
+
+       return ddr_change_freq_sram(nMHz,ddr_freq_t);
+}
+
+EXPORT_SYMBOL(_ddr_change_freq_3036);
+
+static void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
+{    
+    ddr_move_to_Config_state();
+    ddr_move_to_Lowpower_state();
+       pPHY_Reg->PHY_REG264 &= ~(1<<1);
+    pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2)));     //phy soft reset
+    dsb();
+    pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2);  //disable DDR PHY clock
+    ddr_delayus(1);
+}
+
+static void __sramlocalfunc ddr_selfrefresh_exit(void)
+{
+    pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2);  //enable DDR PHY clock
+    dsb();
+    ddr_delayus(1);
+       pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
+       pPHY_Reg->PHY_REG264 |= (1<<1);
+       dsb();
+    ddr_move_to_Config_state();    
+    ddr_data_training(); 
+    ddr_move_to_Access_state();
+    /*ddr_dtt_check();*/
+}
+
+void PIE_FUNC(ddr_suspend)(void)
+{
+       ddr_selfrefresh_enter(0);
+       pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x0 << (1 * 4));    /*PLL slow-mode*/
+       dsb();
+       ddr_delayus(1);
+       pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x1 << 13);        /*PLL power-down*/
+       dsb();
+       ddr_delayus(1);
+}
+EXPORT_PIE_SYMBOL(FUNC(ddr_suspend));
+
+/*----------------------------------------------------------------------
+Name    : void __sramfunc ddr_suspend(void)
+Desc    : ½øÈëddr suspend
+Params  : void
+Return  : void
+Notes   :  
+----------------------------------------------------------------------*/
+#if 0
+void ddr_suspend(void)
+{
+       uint32 i;
+       volatile uint32 n;
+       volatile unsigned int *temp = (volatile unsigned int *)SRAM_CODE_OFFSET;
+       /** 1. Make sure there is no host access */
+       flush_cache_all();
+       outer_flush_all();
+       flush_tlb_all();
+
+       /*sram size = 8KB*/
+       for (i = 0; i < 2; i++) {
+               n = temp[1024 * i];
+               barrier();
+       }
+       n = pDDR_Reg->SCFG.d32;
+       n = pPHY_Reg->PHY_REG1;
+       n = pCRU_Reg->CRU_PLL_CON[0][0];
+       n = *(volatile uint32_t *)SysSrv_DdrTiming;
+       n = pGRF_Reg->GRF_SOC_STATUS0;
+       dsb();
+
+       fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_suspend)) ();
+}
+EXPORT_SYMBOL(ddr_suspend);
+#endif 
+
+void PIE_FUNC(ddr_resume)(void)
+{
+       uint32 delay = 1000;
+
+       pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x0 << 13);        /*PLL no power-down*/
+       dsb();
+       while (delay > 0) {
+               ddr_delayus(1);
+               if (pCRU_Reg->CRU_PLL_CON[1][1] & (0x1 << 10))
+                       break;
+               delay--;
+       }
+
+       pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x1 << (1 * 4));    /*PLL normal*/
+       dsb();
+
+       ddr_selfrefresh_exit();
+}
+
+EXPORT_PIE_SYMBOL(FUNC(ddr_resume));
+#if 0
+static uint32 ddr_get_cap(void)
+{
+    uint32 cs, bank, row, col,row1;
+
+    bank = READ_BK_INFO();
+    row = READ_CS0_ROW_INFO();
+    col = READ_COL_INFO();
+    cs = READ_CS_INFO(); 
+    if(cs>1)
+    {
+        row1 = READ_CS1_ROW_INFO();
+        return ((1 << (row + col + bank + 1))+(1 << (row1 + col + bank + 1)));
+    }
+    else
+    {
+        return (1 << (row + col + bank + 1));
+    }
+}
+#endif 
+#if 0
+/*----------------------------------------------------------------------
+Name    : int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
+Desc    : ddr  ³õʼ»¯º¯Êý
+Params  : dram_speed_bin ->ddr¿ÅÁ£ÀàÐÍ
+          freq ->ƵÂÊÖµ
+Return  : 0 ³É¹¦
+Notes   :  
+----------------------------------------------------------------------*/
+static int ddr_init(uint32_t dram_speed_bin, uint32 freq)
+{
+    volatile uint32_t value = 0;
+    uint32_t cs,die=1;
+
+    ddr_print("version 1.00 20140704 \n");
+    cs = READ_CS_INFO();    //case 0:1rank ; case 1:2rank ; 
+
+    p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
+    p_ddr_freq =kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq)); 
+    p_ddr_reg->mem_type = ((pGRF_Reg->GRF_OS_REG[1] >> 13) &0x7);
+    p_ddr_reg->ddr_speed_bin = dram_speed_bin;
+    *p_ddr_freq= 0;
+    *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
+    *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_dll_status)) = DDR3_DLL_DISABLE;
+    p_copy_data = kern_to_pie(rockchip_pie_chunk, &copy_data[0]);
+    if(p_ddr_reg->mem_type != DDR3)
+    {        
+        ddr_print("ddr type error type=%d\n",(p_ddr_reg->mem_type));
+        return -1;
+    }
+    
+    switch(READ_DIE_BW_INFO())
+    {
+        case 0:         //8bit
+            die = 2;
+            break;
+               case 1:         //16bit 
+                       die = 1;
+                       break;
+        default:
+            ddr_print("ddr die BW error=%d\n",READ_DIE_BW_INFO());
+            break;
+    }
+       
+    
+    //get capability per chip, not total size, used for calculate tRFC
+    p_ddr_reg->ddr_capability_per_die = ddr_get_cap()/(cs * die);
+    ddr_print("%d CS, ROW=%d, Bank=%d, COL=%d, Total Capability=%dMB\n", 
+                                                                    cs, \
+                                                                    READ_CS0_ROW_INFO(), \
+                                                                    (0x1<<(READ_BK_INFO())), \
+                                                                    READ_COL_INFO(), \
+                                                                    (ddr_get_cap()>>20));/*
+*/                                                                    
+    //ddr_adjust_config(p_ddr_reg->mem_type);
+
+    if(freq != 0)
+        value=_ddr_change_freq(freq);
+
+    /*clk_set_rate(clk_get(NULL, "ddr"), 0);*/
+    ddr_print("init success!!! freq=%dMHz\n", (int)value);
+    return 0;
+}
+#endif
+

diff --git a/arch/arm/mach-rockchip/pm-rk312x.c b/arch/arm/mach-rockchip/pm-rk312x.c
index 22d4968d15fd5c4903f433041f65bf55c384b0cc..23863a88b21435086386d62321d69566738e2373 100644 (file)
--- a/arch/arm/mach-rockchip/pm-rk312x.c
+++ b/arch/arm/mach-rockchip/pm-rk312x.c
@@ -152,7 +152,7 @@ static inline void plls_resume(u32 pll_id)
 {
        u32 pllcon0, pllcon1, pllcon2;
 
-       cru_writel(RK312X_PLL_MODE_SLOW(pll_id), RK312X_CRU_MODE_CON);
+       /*cru_writel(RK312X_PLL_MODE_SLOW(pll_id), RK312X_CRU_MODE_CON);*/
        /*cru_writel(RK312X_PLL_NOBYPASS, RK312x_PLL_CONS((pll_id), 0));*/
 
        pllcon0 = plls_con0_save[pll_id];
@@ -220,25 +220,20 @@ static void pm_plls_suspend(void)
 
 static void pm_plls_resume(void)
 {
+       plls_resume(APLL_ID);
        cru_writel(clk_sel0 | CRU_W_MSK(0, 0x1f), RK312X_CRU_CLKSELS_CON(0));
        cru_writel(clk_sel1 | CRU_W_MSK(0, 0x7), RK312X_CRU_CLKSELS_CON(1));
-
-       plls_resume(APLL_ID);
        cru_writel(cru_mode_con
                |(RK312X_PLL_MODE_MSK(APLL_ID) << 16), RK312X_CRU_MODE_CON);
 
-
+       /* pmu alive */
+       plls_resume(GPLL_ID);
        /*peri aclk hclk pclk*/
        cru_writel(clk_sel10 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x3)
        | CRU_W_MSK(12, 0x3)), RK312X_CRU_CLKSELS_CON(10));
-
        /* crypto*/
        cru_writel(clk_sel24 | CRU_W_MSK(0, 0x3), RK312X_CRU_CLKSELS_CON(24));
-
        cru_writel(clk_sel29 | CRU_W_MSK(8, 0x1f), RK312X_CRU_CLKSELS_CON(29));
-
-       /* pmu alive */
-       plls_resume(GPLL_ID);
        cru_writel(cru_mode_con | (RK312X_PLL_MODE_MSK(GPLL_ID) << 16)
                , RK312X_CRU_MODE_CON);
 
@@ -903,86 +898,42 @@ static void pmic_sleep_gpio_get_dts_info(struct device_node *parent)
 void PIE_FUNC(ddr_suspend)(void);
 void PIE_FUNC(ddr_resume)(void);
 
+static __sramdata u32 rkpm_pwm_duty0;
+static __sramdata u32 rkpm_pwm_duty1;
+static __sramdata u32 rkpm_pwm_duty2;
+#define PWM_VOLTAGE 0x600
+
 void PIE_FUNC(pwm_regulator_suspend)(void)
 {
-       int gpio0_inout;
-       int gpio0_ddr;
-       int clk_gates8;
-
-       clk_gates8 = cru_readl(0xf0);
-       cru_writel(0x1e000000, 0xf0);
        if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0)) {
-               grf_writel(0x00100000, 0xb4);/*iomux  gpio0d2*/
-               gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
-               gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
-               writel_relaxed(gpio0_inout | 0x04000000
-                       , RK_GPIO_VIRT(0) + 0x04);
-               dsb();
-               writel_relaxed(gpio0_ddr | 0x04000000, RK_GPIO_VIRT(0));
+               rkpm_pwm_duty0 = readl_relaxed(RK_PWM_VIRT + 0x08);
+               writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x08);
        }
 
        if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1)) {
-               grf_writel(0x00400000, 0xb4);/*iomux  gpio0d3*/
-               gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
-               gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
-               writel_relaxed(gpio0_inout | 0x08000000
-                       , RK_GPIO_VIRT(0) + 0x04);
-               dsb();
-               writel_relaxed(gpio0_ddr | 0x08000000, RK_GPIO_VIRT(0));
+               rkpm_pwm_duty1 = readl_relaxed(RK_PWM_VIRT + 0x18);
+               writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x18);
        }
 
        if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2)) {
-               grf_writel(0x01000000, 0xb4);/*iomux  gpio0d2*/
-               gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
-               gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
-               writel_relaxed(gpio0_inout | 0x10000000, RK_GPIO_VIRT(0) + 0x04);
-               dsb();
-               writel_relaxed(gpio0_ddr | 0x10000000, RK_GPIO_VIRT(0));
+               rkpm_pwm_duty2 = readl_relaxed(RK_PWM_VIRT + 0x28);
+               writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x28);
        }
-       cru_writel(0x1e000000 | clk_gates8, 0xf0);
-       sram_udelay(30);
 }
 
 void PIE_FUNC(pwm_regulator_resume)(void)
 {
-       int gpio0_inout;
-       int gpio0_ddr;
-       int clk_gates8;
-
-       clk_gates8 = cru_readl(0xf0);
        cru_writel(0x1e000000, 0xf0);
-       if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0)) {
-               grf_writel(0x00100010, 0xb4);/*iomux  gpio0d2*/
-               gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
-               gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
-               writel_relaxed(gpio0_inout | 0x04000000, RK_GPIO_VIRT(0)
-                       + 0x04);
-               dsb();
-               writel_relaxed(gpio0_ddr &  ~0x04000000, RK_GPIO_VIRT(0));
-       }
+       if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0))
+               writel_relaxed(rkpm_pwm_duty0, RK_PWM_VIRT + 0x08);
 
-       if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1)) {
-               grf_writel(0x00400040, 0xb4);/*iomux  gpio0d3*/
-               gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
-               gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
-               writel_relaxed(gpio0_inout | 0x08000000, RK_GPIO_VIRT(0)
-                       + 0x04);
-               dsb();
-               writel_relaxed(gpio0_ddr | ~0x08000000, RK_GPIO_VIRT(0));
-       }
+       if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1))
+               writel_relaxed(rkpm_pwm_duty1, RK_PWM_VIRT + 0x18);
 
-       if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2)) {
-               grf_writel(0x01001000, 0xb4);/*iomux  gpio0d2*/
-               gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
-               gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
-               writel_relaxed(gpio0_inout | 0x10000000, RK_GPIO_VIRT(0)
-                       + 0x04);
-               dsb();
-               writel_relaxed(gpio0_ddr | ~0x10000000, RK_GPIO_VIRT(0));
-       }
-       cru_writel(0x1e000000 | clk_gates8, 0xf0);
-       sram_udelay(30);
+       if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2))
+               writel_relaxed(rkpm_pwm_duty2, RK_PWM_VIRT + 0x28);
 }
+
 static void reg_pread(void)
 {
        int i;
@@ -1012,6 +963,7 @@ static void reg_pread(void)
        n = readl_relaxed(RK_GRF_VIRT);
        n = readl_relaxed(RK_CRU_VIRT);
        n = readl_relaxed(RK_PMU_VIRT);
+       n = readl_relaxed(RK_PWM_VIRT);
 }
 
 static void __init rk312x_suspend_init(void)

diff --git a/arch/arm/mach-rockchip/rk312x.c b/arch/arm/mach-rockchip/rk312x.c
index f493337b7f10f930917f935f8a23b6572eb75d81..5308c528c2b72ae0c330698f697c79d3d62f3c0c 100755 (executable)
--- a/arch/arm/mach-rockchip/rk312x.c
+++ b/arch/arm/mach-rockchip/rk312x.c
@@ -79,6 +79,7 @@ static struct map_desc rk312x_io_desc[] __initdata = {
        RK_DEVICE(RK_GIC_VIRT, RK312X_GIC_DIST_PHYS, RK312X_GIC_DIST_SIZE),
        RK_DEVICE(RK_GIC_VIRT + RK312X_GIC_DIST_SIZE, RK312X_GIC_CPU_PHYS, RK312X_GIC_CPU_SIZE),
        RK_DEVICE(RK312X_IMEM_VIRT, RK312X_IMEM_PHYS, RK312X_IMEM_SIZE),
+       RK_DEVICE(RK_PWM_VIRT, RK312X_PWM_PHYS, RK312X_PWM_SIZE),
 };
 
 static void __init rk312x_boot_mode_init(void)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9fda3302945728e5bcecdf8b65eaa00972881e12..e2422f44a4c1ffa3e69dd1c2619d143c3b459b48 100755 (executable)
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -205,6 +205,49 @@ config MFD_RT_SHOW_INFO
        help
          Enable the RT5025 PMIC debug log.
 
+config MFD_RT5036
+       bool "Richtek RT5036 PMIC support"
+       select MFD_CORE
+       default n
+       help
+         Enable the RT5036 MFD driver.
+
+config MFD_RT5036_DBGINFO
+       bool "Richtek RT5036 debug message enable."
+       depends on MFD_RT5036
+       default n
+       help
+         Enable the RT5036 debug log.
+
+config MISC_RT5036
+       bool "Richtek RT5036 MISC option driver support"
+       depends on MFD_RT5036
+       default n
+       help
+         Enable the RT5036 Misc option driver support.
+
+config MISC_RT5036_PWRKEY
+       bool "Richtek RT5036 Power key report in Misc module"
+       depends on MISC_RT5036
+       default n
+       help
+         Enable the RT5036 Power Key report in Misc module.
+
+config IRQ_RT5036
+       bool "Richtek RT5036 irq option driver support"
+       depends on MFD_RT5036
+       default n
+       help
+         Enable the Rt5036 IRQ option driver support.
+
+config DEBUG_RT5036
+       bool "Richtek RT5036 PMIC DEBUGFS Support"
+       depends on DEBUG_FS && MFD_RT5036
+       default n
+       help
+         Enable the RT5036 debugfs node that support
+         read/write registers.
+
 config HTC_EGPIO
        bool "HTC EGPIO support"
        depends on GENERIC_HARDIRQS && GPIOLIB && ARM

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 1a69560d8dcbc53377191a265bff1d0db866d307..ff346f12f533e36a05a34a74f91b632c48125eb8 100755 (executable)
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -60,6 +60,11 @@ obj-$(CONFIG_MISC_RT5025)    += rt5025-misc.o
 obj-$(CONFIG_IRQ_RT5025)       += rt5025-irq.o
 obj-$(CONFIG_DEBUG_RT5025)     += rt5025-debug.o
 
+obj-$(CONFIG_MFD_RT5036)       += rt5036-i2c.o rt5036-core.o
+obj-$(CONFIG_MISC_RT5036)      += rt5036-misc.o
+obj-$(CONFIG_IRQ_RT5036)       += rt5036-irq.o
+obj-$(CONFIG_DEBUG_RT5036)     += rt5036-debug.o
+
 obj-$(CONFIG_TPS6105X)         += tps6105x.o
 obj-$(CONFIG_TPS65010)         += tps65010.o
 obj-$(CONFIG_TPS6507X)         += tps6507x.o

diff --git a/drivers/mfd/rt5025-i2c.c b/drivers/mfd/rt5025-i2c.c
index 5690e050403ebac71fb4e78d2655b5a0e0f0c7dd..18ec6e5c4e2410b74ba7867ae334434791a29d5a 100755 (executable)
--- a/drivers/mfd/rt5025-i2c.c
+++ b/drivers/mfd/rt5025-i2c.c
@@ -205,24 +205,31 @@ static int rt5025_i2c_remove(struct i2c_client *client)
        return 0;
 }
 
-static int rt5025_i2c_suspend(struct i2c_client *client, pm_message_t mesg)
+static int rt5025_i2c_suspend(struct device *dev)
 {
-       struct rt5025_chip *chip = i2c_get_clientdata(client);
+       struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
+       struct rt5025_chip *chip = i2c_get_clientdata(i2c);
 
-       chip->suspend = 1;
        RTINFO("\n");
+       chip->suspend = 1;
        return 0;
 }
 
-static int rt5025_i2c_resume(struct i2c_client *client)
+static int rt5025_i2c_resume(struct device *dev)
 {
-       struct rt5025_chip *chip = i2c_get_clientdata(client);
+       struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
+       struct rt5025_chip *chip = i2c_get_clientdata(i2c);
 
-       chip->suspend = 0;
        RTINFO("\n");
+       chip->suspend = 0;
        return 0;
 }
 
+static const struct dev_pm_ops rt5025_pm_ops = {
+       .suspend = rt5025_i2c_suspend,
+       .resume =  rt5025_i2c_resume,
+};
+
 static const struct i2c_device_id rt5025_id_table[] = {
        { RT5025_DEV_NAME, 0 },
        { },
@@ -238,12 +245,11 @@ static struct i2c_driver rt5025_i2c_driver = {
        .driver = {
                .name   = RT5025_DEV_NAME,
                .owner  = THIS_MODULE,
+                .pm = &rt5025_pm_ops,
                .of_match_table = rt_match_table,
        },
        .probe          = rt5025_i2c_probe,
        .remove         = rt5025_i2c_remove,
-       .suspend        = rt5025_i2c_suspend,
-       .resume         = rt5025_i2c_resume,
        .id_table       = rt5025_id_table,
 };
 

diff --git a/drivers/mfd/rt5036-core.c b/drivers/mfd/rt5036-core.c
new file mode 100755 (executable)
index 0000000..2560be6
--- /dev/null
+++ b/drivers/mfd/rt5036-core.c
@@ -0,0 +1,268 @@
+/*
+ *  drivers/mfd/rt5036-core.c
+ *  Driver for Richtek RT5036 Core PMIC
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/mfd/core.h>
+
+#include <linux/mfd/rt5036/rt5036.h>
+
+#ifdef CONFIG_REGULATOR_RT5036
+#ifdef CONFIG_OF
+#define RT5036_BUCKVR_DEVS(_id, _idx)                          \
+{                                                              \
+       .name           = RT5036_DEV_NAME "-regulator",         \
+       .num_resources  = 0,                                    \
+       .of_compatible  = "rt," RT5036_DEV_NAME "-dcdc" #_idx, \
+       .id             = RT5036_ID_##_id,                      \
+}
+
+#define RT5036_LDOVR_DEVS(_id, _idx)                           \
+{                                                              \
+       .name           = RT5036_DEV_NAME "-regulator",         \
+       .num_resources  = 0,                                    \
+       .of_compatible  = "rt," RT5036_DEV_NAME "-ldo" #_idx,   \
+       .id             = RT5036_ID_##_id,                      \
+}
+
+#define RT5036_LSWVR_DEVS(_id, _idx)                           \
+{                                                              \
+       .name = RT5036_DEV_NAME "-regulator",                   \
+       .num_resources = 0,                                     \
+       .of_compatible  = "rt," RT5036_DEV_NAME "-lsw" #_idx,   \
+       .id             = RT5036_ID_##_id,                      \
+}
+#else
+#define RT5036_BUCKVR_DEVS(_id, _idx)                          \
+{                                                              \
+       .name           = RT5036_DEV_NAME "-regulator",         \
+       .num_resources  = 0,                                    \
+       .id             = RT5036_ID_##_id,                      \
+}
+
+#define RT5036_LDOVR_DEVS(_id, _idx)                           \
+{                                                              \
+       .name           = RT5036_DEV_NAME "-regulator",         \
+       .num_resources  = 0,                                    \
+       .id             = RT5036_ID_##_id,                      \
+}
+
+#define RT5036_LSWVR_DEVS(_id, _idx)                           \
+{                                                              \
+       .name = RT5036_DEV_NAME "-regulator",                   \
+       .num_resources = 0,                                     \
+       .id             = RT5036_ID_##_id,                      \
+}
+#endif /* #ifdef CONFIG_OF */
+
+static struct mfd_cell regulator_devs[] = {
+       RT5036_BUCKVR_DEVS(DCDC1, 1),
+       RT5036_BUCKVR_DEVS(DCDC2, 2),
+       RT5036_BUCKVR_DEVS(DCDC3, 3),
+       RT5036_BUCKVR_DEVS(DCDC4, 4),
+       RT5036_LDOVR_DEVS(LDO1, 1),
+       RT5036_LDOVR_DEVS(LDO2, 2),
+       RT5036_LDOVR_DEVS(LDO3, 3),
+       RT5036_LDOVR_DEVS(LDO4, 4),
+       RT5036_LSWVR_DEVS(LSW1, 1),
+       RT5036_LSWVR_DEVS(LSW2, 2),
+};
+#endif /* CONFIG_REGULATOR_RT5036 */
+
+#ifdef CONFIG_CHARGER_RT5036
+static struct mfd_cell chg_devs[] = {
+       {
+        .name = RT5036_DEV_NAME "-charger",
+        .id = -1,
+        .num_resources = 0,
+#ifdef CONFIG_OF
+        .of_compatible = "rt," RT5036_DEV_NAME "-charger",
+#endif /*#ifdef CONFIG_OF */
+        },
+};
+#endif /* CONFIG_CHARGER_RT5036 */
+
+#ifdef CONFIG_RTC_RT5036
+static struct mfd_cell rtc_devs[] = {
+       {
+        .name = RT5036_DEV_NAME "-rtc",
+        .id = -1,
+        .num_resources = 0,
+#ifdef CONFIG_OF
+        .of_compatible = "rt," RT5036_DEV_NAME "-rtc",
+#endif /*#ifdef CONFIG_OF */
+        },
+};
+#endif /* CONFIG_RTC_RT5036 */
+
+#ifdef CONFIG_MISC_RT5036
+static struct mfd_cell misc_devs[] = {
+       {
+        .name = RT5036_DEV_NAME "-misc",
+        .id = -1,
+        .num_resources = 0,
+#ifdef CONFIG_OF
+        .of_compatible = "rt," RT5036_DEV_NAME "-misc",
+#endif /*#ifdef CONFIG_OF */
+        },
+};
+#endif /* CONFIG_MISC_RT5036 */
+
+#ifdef CONFIG_IRQ_RT5036
+static struct mfd_cell irq_devs[] = {
+       {
+        .name = RT5036_DEV_NAME "-irq",
+        .id = -1,
+        .num_resources = 0,
+#ifdef CONFIG_OF
+        .of_compatible = "rt," RT5036_DEV_NAME "-irq",
+#endif /*#ifdef CONFIG_OF */
+        },
+};
+#endif /* CONFIG_IRQ_RT5036 */
+
+#ifdef CONFIG_DEBUG_RT5036
+static struct mfd_cell debug_devs[] = {
+       {
+        .name = RT5036_DEV_NAME "-debug",
+        .id = -1,
+        .num_resources = 0,
+#ifdef CONFIG_OF
+        .of_compatible = "rt," RT5036_DEV_NAME "-debug",
+#endif /*#ifdef CONFIG_OF */
+        },
+};
+#endif /* CONFIG_DEBUG_RT5036 */
+
+int rt5036_core_init(struct device *dev,
+                              struct rt5036_platform_data *pdata)
+{
+       int ret = 0;
+
+       RTINFO("Start to initialize all device\n");
+#ifdef CONFIG_REGULATOR_RT5036
+       if (dev->of_node || (pdata && pdata->regulator[0])) {
+               RTINFO("mfd add regulators dev\n");
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+               ret = mfd_add_devices(dev, 0, &regulator_devs[0],
+                                     ARRAY_SIZE(regulator_devs),
+                                     NULL, 0, NULL);
+#else
+               ret = mfd_add_devices(dev, 0, &regulator_devs[0],
+                                     ARRAY_SIZE(regulator_devs), NULL, 0);
+#endif /* LINUX_VERSION_CODE>=KERNL_VERSION(3,6,0) */
+               if (ret < 0) {
+                       dev_err(dev, "Failed to add regulator subdev\n");
+                       goto out_dev;
+               }
+       }
+#endif /* CONFIG_REGULATOR_RT5036 */
+
+#ifdef CONFIG_CHARGER_RT5036
+       if (dev->of_node || (pdata && pdata->chg_pdata)) {
+               RTINFO("mfd add charger dev\n");
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+               ret = mfd_add_devices(dev, 0, &chg_devs[0],
+                                     ARRAY_SIZE(chg_devs), NULL, 0, NULL);
+#else
+               ret = mfd_add_devices(dev, 0, &chg_devs[0],
+                                     ARRAY_SIZE(chg_devs), NULL, 0);
+#endif /* LINUX_VERSION_CODE>=KERNL_VERSION(3,6,0) */
+               if (ret < 0) {
+                       dev_err(dev, "Failed to add charger subdev\n");
+                       goto out_dev;
+               }
+       }
+#endif /* CONFIG_CHARGER_RT5036 */
+
+#ifdef CONFIG_RTC_RT5036
+       if (dev->of_node || pdata) {
+               RTINFO("mfd add rtc dev\n");
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+               ret = mfd_add_devices(dev, 0, &rtc_devs[0],
+                                     ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
+#else
+               ret = mfd_add_devices(dev, 0, &rtc_devs[0],
+                                     ARRAY_SIZE(rtc_devs), NULL, 0);
+#endif /* LINUX_VERSION_CODE>=KERNL_VERSION(3,6,0) */
+               if (ret < 0) {
+                       dev_err(dev, "Failed to add rtc subdev\n");
+                       goto out_dev;
+               }
+       }
+#endif /* CONFIG_RTC_RT5036 */
+
+#ifdef CONFIG_MISC_RT5036
+       if (dev->of_node || (pdata && pdata->misc_pdata)) {
+               RTINFO("mfd add misc dev\n");
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+               ret = mfd_add_devices(dev, 0, &misc_devs[0],
+                                     ARRAY_SIZE(misc_devs), NULL, 0, NULL);
+#else
+               ret = mfd_add_devices(dev, 0, &misc_devs[0],
+                                     ARRAY_SIZE(misc_devs), NULL, 0);
+#endif /* LINUX_VERSION_CODE>=KERNL_VERSION(3,6,0) */
+               if (ret < 0) {
+                       dev_err(dev, "Failed to add misc subdev\n");
+                       goto out_dev;
+               }
+       }
+#endif /* CONFIG_MISC_RT5036 */
+
+#ifdef CONFIG_IRQ_RT5036
+       if (dev->of_node || (pdata && pdata->irq_pdata)) {
+               RTINFO("mfd add irq dev\n");
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+               ret = mfd_add_devices(dev, 0, &irq_devs[0],
+                                     ARRAY_SIZE(irq_devs), NULL, 0, NULL);
+#else
+               ret = mfd_add_devices(dev, 0, &irq_devs[0],
+                                     ARRAY_SIZE(irq_devs), NULL, 0);
+#endif /* LINUX_VERSION_CODE>=KERNL_VERSION(3,6,0) */
+               if (ret < 0) {
+                       dev_err(dev, "Failed to add irq subdev\n");
+                       goto out_dev;
+               }
+       }
+#endif /* CONFIG_IRQ_RT5036 */
+
+#ifdef CONFIG_DEBUG_RT5036
+       RTINFO("mfd add debug dev\n");
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+       ret = mfd_add_devices(dev, 0, &debug_devs[0],
+                             ARRAY_SIZE(debug_devs), NULL, 0, NULL);
+#else
+       ret = mfd_add_devices(dev, 0, &debug_devs[0],
+                             ARRAY_SIZE(debug_devs), NULL, 0);
+#endif /* LINUX_VERSION_CODE>=KERNL_VERSION(3,6,0) */
+       if (ret < 0) {
+               dev_err(dev, "Failed to add debug subdev\n");
+               goto out_dev;
+       }
+#endif /* CONFIG_DEBUG_RT5036 */
+
+       RTINFO("Initialize all device successfully\n");
+       return ret;
+out_dev:
+       mfd_remove_devices(dev);
+       return ret;
+}
+EXPORT_SYMBOL(rt5036_core_init);
+
+int rt5036_core_deinit(struct device *dev)
+{
+       mfd_remove_devices(dev);
+       return 0;
+}
+EXPORT_SYMBOL(rt5036_core_deinit);

diff --git a/drivers/mfd/rt5036-debug.c b/drivers/mfd/rt5036-debug.c
new file mode 100755 (executable)
index 0000000..6f81c29
--- /dev/null
+++ b/drivers/mfd/rt5036-debug.c
@@ -0,0 +1,261 @@
+/*
+ *  drivers/mfd/rt5036-debug.c
+ *  Driver for Richtek RT5036 PMIC debug
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+
+#include <linux/mfd/rt5036/rt5036.h>
+
+struct rt5036_debug_info {
+       struct i2c_client *i2c;
+       unsigned char reg_addr;
+       unsigned char reg_data;
+};
+
+struct rt_debug_st {
+       void *info;
+       int id;
+};
+
+enum {
+       RT5036_DBG_REG,
+       RT5036_DBG_DATA,
+       RT5036_DBG_REGS,
+       RT5036_DBG_MAX
+};
+
+static struct dentry *debugfs_rt_dent;
+static struct dentry *debugfs_file[RT5036_DBG_MAX];
+static struct rt_debug_st rtdbg_data[RT5036_DBG_MAX];
+
+static int reg_debug_open(struct inode *inode, struct file *file)
+{
+       file->private_data = inode->i_private;
+       return 0;
+}
+
+static int get_parameters(char *buf, long int *param1, int num_of_par)
+{
+       char *token;
+       int base, cnt;
+
+       token = strsep(&buf, " ");
+
+       for (cnt = 0; cnt < num_of_par; cnt++) {
+               if (token != NULL) {
+                       if ((token[1] == 'x') || (token[1] == 'X'))
+                               base = 16;
+                       else
+                               base = 10;
+
+                       if (kstrtoul(token, base, &param1[cnt]) != 0)
+                               return -EINVAL;
+
+                       token = strsep(&buf, " ");
+               } else {
+                       return -EINVAL;
+               }
+       }
+       return 0;
+}
+
+static ssize_t reg_debug_read(struct file *filp, char __user *ubuf,
+                             size_t count, loff_t *ppos)
+{
+       struct rt_debug_st *st = filp->private_data;
+       struct rt5036_debug_info *di = st->info;
+       char lbuf[1000];
+       int i = 0, j = 0;
+
+       lbuf[0] = '\0';
+       switch (st->id) {
+       case RT5036_DBG_REG:
+               snprintf(lbuf, sizeof(lbuf), "0x%x\n", di->reg_addr);
+               break;
+       case RT5036_DBG_DATA:
+               di->reg_data =
+                   (unsigned char)rt5036_reg_read(di->i2c, di->reg_addr);
+               snprintf(lbuf, sizeof(lbuf), "0x%x\n", di->reg_data);
+               break;
+       case RT5036_DBG_REGS:
+               for (i = RT5036_REG_RANGE1START; i <= RT5036_REG_RANGE1END; i++)
+                       j += sprintf(lbuf + j, "reg_%02x:%02x\n", i,
+                                    rt5036_reg_read(di->i2c, i));
+               for (i = RT5036_REG_RANGE2START; i <= RT5036_REG_RANGE2END; i++)
+                       j += sprintf(lbuf + j, "reg_%02x:%02x\n", i,
+                                    rt5036_reg_read(di->i2c, i));
+               for (i = RT5036_REG_RANGE3START; i <= RT5036_REG_RANGE3END; i++)
+                       j += sprintf(lbuf + j, "reg_%02x:%02x\n", i,
+                                    rt5036_reg_read(di->i2c, i));
+               for (i = RT5036_REG_RANGE4START; i <= RT5036_REG_RANGE4END; i++)
+                       j += sprintf(lbuf + j, "reg_%02x:%02x\n", i,
+                                    rt5036_reg_read(di->i2c, i));
+               for (i = RT5036_REG_RANGE5START; i <= RT5036_REG_RANGE5END; i++)
+                       j += sprintf(lbuf + j, "reg_%02x:%02x\n", i,
+                                    rt5036_reg_read(di->i2c, i));
+               for (i = RT5036_REG_RANGE6START; i <= RT5036_REG_RANGE6END; i++)
+                       j += sprintf(lbuf + j, "reg_%02x:%02x\n", i,
+                                    rt5036_reg_read(di->i2c, i));
+               break;
+       default:
+               return -EINVAL;
+       }
+       return simple_read_from_buffer(ubuf, count, ppos, lbuf, strlen(lbuf));
+}
+
+static ssize_t reg_debug_write(struct file *filp,
+                              const char __user *ubuf, size_t cnt,
+                              loff_t *ppos)
+{
+       struct rt_debug_st *st = filp->private_data;
+       struct rt5036_debug_info *di = st->info;
+       char lbuf[32];
+       int rc;
+       long int param[5];
+
+       if (cnt > sizeof(lbuf) - 1)
+               return -EINVAL;
+
+       rc = copy_from_user(lbuf, ubuf, cnt);
+       if (rc)
+               return -EFAULT;
+
+       lbuf[cnt] = '\0';
+
+       switch (st->id) {
+       case RT5036_DBG_REG:
+               rc = get_parameters(lbuf, param, 1);
+               if ((param[0] < RT5036_REG_MAX) && (rc == 0)) {
+                       if ((param[0] >= RT5036_REG_RANGE1START
+                            && param[0] <= RT5036_REG_RANGE1END)
+                           || (param[0] >= RT5036_REG_RANGE2START
+                               && param[0] <= RT5036_REG_RANGE2END)
+                           || (param[0] >= RT5036_REG_RANGE3START
+                               && param[0] <= RT5036_REG_RANGE3END)
+                           || (param[0] >= RT5036_REG_RANGE4START
+                               && param[0] <= RT5036_REG_RANGE4END)
+                           || (param[0] >= RT5036_REG_RANGE5START
+                               && param[0] <= RT5036_REG_RANGE5END))
+                               di->reg_addr = (unsigned char)param[0];
+                       else
+                               rc = -EINVAL;
+               } else
+                       rc = -EINVAL;
+               break;
+       case RT5036_DBG_DATA:
+               rc = get_parameters(lbuf, param, 1);
+               if ((param[0] <= 0xff) && (rc == 0))
+                       rt5036_reg_write(di->i2c, di->reg_addr, param[0]);
+               else
+                       rc = -EINVAL;
+               break;
+       default:
+               return -EINVAL;
+       }
+       if (rc == 0)
+               rc = cnt;
+       return rc;
+}
+
+static const struct file_operations reg_debug_ops = {
+       .open = reg_debug_open,
+       .write = reg_debug_write,
+       .read = reg_debug_read
+};
+
+static int rt5036_debug_probe(struct platform_device *pdev)
+{
+       struct rt5036_chip *chip = dev_get_drvdata(pdev->dev.parent);
+       struct rt5036_debug_info *di;
+
+       di = devm_kzalloc(&pdev->dev, sizeof(*di), GFP_KERNEL);
+       if (!di)
+               return -ENOMEM;
+
+       di->i2c = chip->i2c;
+
+       RTINFO("add debugfs for RT5036");
+       debugfs_rt_dent = debugfs_create_dir("rt5036_dbg", 0);
+       if (!IS_ERR(debugfs_rt_dent)) {
+               rtdbg_data[0].info = di;
+               rtdbg_data[0].id = RT5036_DBG_REG;
+               debugfs_file[0] = debugfs_create_file("reg",
+                                                     S_IFREG | S_IRUGO,
+                                                     debugfs_rt_dent,
+                                                     (void *)&rtdbg_data[0],
+                                                     &reg_debug_ops);
+
+               rtdbg_data[1].info = di;
+               rtdbg_data[1].id = RT5036_DBG_DATA;
+               debugfs_file[1] = debugfs_create_file("data",
+                                                     S_IFREG | S_IRUGO,
+                                                     debugfs_rt_dent,
+                                                     (void *)&rtdbg_data[1],
+                                                     &reg_debug_ops);
+
+               rtdbg_data[2].info = di;
+               rtdbg_data[2].id = RT5036_DBG_REGS;
+               debugfs_file[2] = debugfs_create_file("regs",
+                                                     S_IFREG | S_IRUGO,
+                                                     debugfs_rt_dent,
+                                                     (void *)&rtdbg_data[2],
+                                                     &reg_debug_ops);
+       }
+       platform_set_drvdata(pdev, di);
+       return 0;
+}
+
+static int rt5036_debug_remove(struct platform_device *pdev)
+{
+       if (!IS_ERR(debugfs_rt_dent))
+               debugfs_remove_recursive(debugfs_rt_dent);
+       return 0;
+}
+
+static const struct of_device_id rt_match_table[] = {
+       {.compatible = "rt,rt5036-debug",},
+       {},
+};
+
+static struct platform_driver rt5036_debug_driver = {
+       .driver = {
+                  .name = RT5036_DEV_NAME "-debug",
+                  .owner = THIS_MODULE,
+                  .of_match_table = rt_match_table,
+                  },
+       .probe = rt5036_debug_probe,
+       .remove = rt5036_debug_remove,
+};
+
+static int __init rt5036_debug_init(void)
+{
+       return platform_driver_register(&rt5036_debug_driver);
+}
+module_init(rt5036_debug_init);
+
+static void __exit rt5036_debug_exit(void)
+{
+       platform_driver_unregister(&rt5036_debug_driver);
+}
+module_exit(rt5036_debug_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("CY Huang <cy_huang@richtek.com");
+MODULE_DESCRIPTION("Debugfs driver for RT5036");
+MODULE_ALIAS("platform:" RT5036_DEV_NAME "-debug");
+MODULE_VERSION(RT5036_DRV_VER);

diff --git a/drivers/mfd/rt5036-i2c.c b/drivers/mfd/rt5036-i2c.c
new file mode 100755 (executable)
index 0000000..1d2d616
--- /dev/null
+++ b/drivers/mfd/rt5036-i2c.c
@@ -0,0 +1,279 @@
+/*
+ *  drivers/mfd/rt5036-i2c.c
+ *  Source file for Richtek RT5036
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+
+#include <linux/mfd/rt5036/rt5036.h>
+
+static inline int rt5036_read_device(struct i2c_client *i2c,
+                                    int reg, int bytes, void *dest)
+{
+       int ret;
+
+       if (bytes > 1) {
+               ret = i2c_smbus_read_i2c_block_data(i2c, reg, bytes, dest);
+       } else {
+               ret = i2c_smbus_read_byte_data(i2c, reg);
+               if (ret < 0)
+                       return ret;
+               *(unsigned char *)dest = (unsigned char)ret;
+       }
+       return ret;
+}
+
+int rt5036_reg_block_read(struct i2c_client *i2c,
+                         int reg, int bytes, void *dest)
+{
+       return rt5036_read_device(i2c, reg, bytes, dest);
+}
+EXPORT_SYMBOL(rt5036_reg_block_read);
+
+static inline int rt5036_write_device(struct i2c_client *i2c,
+                                     int reg, int bytes, void *dest)
+{
+       int ret;
+
+       if (bytes > 1) {
+               ret = i2c_smbus_write_i2c_block_data(i2c, reg, bytes, dest);
+       } else {
+               ret = i2c_smbus_write_byte_data(i2c, reg, *(u8 *) dest);
+               if (ret < 0)
+                       return ret;
+       }
+       return ret;
+}
+
+int rt5036_reg_block_write(struct i2c_client *i2c,
+                          int reg, int bytes, void *dest)
+{
+       return rt5036_write_device(i2c, reg, bytes, dest);
+}
+EXPORT_SYMBOL(rt5036_reg_block_write);
+
+int rt5036_reg_read(struct i2c_client *i2c, int reg)
+{
+       struct rt5036_chip *chip = i2c_get_clientdata(i2c);
+       int ret;
+
+       RTINFO("I2C Read (client : 0x%x) reg = 0x%x\n",
+              (unsigned int)i2c, (unsigned int)reg);
+       mutex_lock(&chip->io_lock);
+       ret = i2c_smbus_read_byte_data(i2c, reg);
+       mutex_unlock(&chip->io_lock);
+       return ret;
+}
+EXPORT_SYMBOL(rt5036_reg_read);
+
+int rt5036_reg_write(struct i2c_client *i2c, int reg, unsigned char data)
+{
+       struct rt5036_chip *chip = i2c_get_clientdata(i2c);
+       int ret;
+
+       RTINFO("I2C Write (client : 0x%x) reg = 0x%x, data = 0x%x\n",
+              (unsigned int)i2c, (unsigned int)reg, (unsigned int)data);
+       mutex_lock(&chip->io_lock);
+       ret = i2c_smbus_write_byte_data(i2c, reg, data);
+       mutex_unlock(&chip->io_lock);
+       return ret;
+}
+EXPORT_SYMBOL(rt5036_reg_write);
+
+int rt5036_assign_bits(struct i2c_client *i2c, int reg,
+                      unsigned char mask, unsigned char data)
+{
+       struct rt5036_chip *chip = i2c_get_clientdata(i2c);
+       unsigned char value;
+       int ret;
+
+       mutex_lock(&chip->io_lock);
+       ret = rt5036_read_device(i2c, reg, 1, &value);
+
+       if (ret < 0)
+               goto out;
+       value &= ~mask;
+       value |= (data & mask);
+       ret = i2c_smbus_write_byte_data(i2c, reg, value);
+out:
+       mutex_unlock(&chip->io_lock);
+       return ret;
+}
+EXPORT_SYMBOL(rt5036_assign_bits);
+
+int rt5036_set_bits(struct i2c_client *i2c, int reg, unsigned char mask)
+{
+       return rt5036_assign_bits(i2c, reg, mask, mask);
+}
+EXPORT_SYMBOL(rt5036_set_bits);
+
+int rt5036_clr_bits(struct i2c_client *i2c, int reg, unsigned char mask)
+{
+       return rt5036_assign_bits(i2c, reg, mask, 0);
+}
+EXPORT_SYMBOL(rt5036_clr_bits);
+
+static int rt_parse_dt(struct rt5036_chip *chip, struct device *dev)
+{
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt_parse_pdata(struct rt5036_chip *chip,
+                                   struct device *dev)
+{
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt5036_i2c_probe(struct i2c_client *client,
+                                     const struct i2c_device_id *id)
+{
+       struct rt5036_platform_data *pdata = client->dev.platform_data;
+       struct rt5036_chip *chip;
+       bool use_dt = client->dev.of_node;
+       int val, ret = 0;
+
+       chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
+       if (!chip)
+               return -ENOMEM;
+
+       chip->i2c = client;
+       mutex_init(&chip->io_lock);
+       i2c_set_clientdata(client, chip);
+
+       val = rt5036_reg_read(client, RT5036_REG_DEVID);
+       if (val < 0) {
+               ret = -EIO;
+               goto out_err;
+       } else {
+               if (val != 0x36) {
+                       dev_err(&client->dev, "id 0x%02x is not correct\n",
+                               val);
+                       ret = ENODEV;
+                       goto out_err;
+               }
+               val = rt5036_reg_read(client, RT5036_REG_ONOFFEVENT);
+               dev_info(&client->dev, "last onoff event %02x\n", val);
+               /*set ldo lsw vrc to default enable*/
+               rt5036_reg_write(client, 0x4D, 0xF0);
+               rt5036_reg_write(client, 0x7D, 0xF0);
+               rt5036_reg_write(client, 0x85, 0xCC);
+       }
+
+       if (use_dt) {
+               rt_parse_dt(chip, &client->dev);
+       } else {
+               if (!pdata) {
+                       dev_err(&client->dev, "no platform data included\n");
+                       ret = -EINVAL;
+                       goto out_err;
+               }
+               rt_parse_pdata(chip, &client->dev);
+       }
+
+       ret = rt5036_core_init(&client->dev, pdata);
+       if (ret < 0) {
+               ret = -EINVAL;
+               goto out_err;
+       }
+
+       if (pdata && pdata->pre_init) {
+               ret = pdata->pre_init(chip);
+               if (ret != 0)
+                       dev_err(&client->dev, "pre_init() failed: %d\n", ret);
+       }
+       if (pdata && pdata->post_init) {
+               ret = pdata->post_init();
+               if (ret != 0)
+                       dev_err(&client->dev, "post_init() failed: %d\n", ret);
+       }
+       dev_info(&client->dev, "driver successfully loaded\n");
+       return 0;
+out_err:
+       return ret;
+}
+
+static int rt5036_i2c_remove(struct i2c_client *client)
+{
+       RTINFO("\n");
+       rt5036_core_deinit(&client->dev);
+       return 0;
+}
+
+static int rt5036_i2c_suspend(struct device *dev)
+{
+       struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
+       struct rt5036_chip *chip = i2c_get_clientdata(i2c);
+
+       RTINFO("\n");
+       chip->suspend = 1;
+       return 0;
+}
+
+static int rt5036_i2c_resume(struct device *dev)
+{
+       struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
+       struct rt5036_chip *chip = i2c_get_clientdata(i2c);
+
+       RTINFO("\n");
+       chip->suspend = 0;
+       return 0;
+}
+
+static const struct dev_pm_ops rt5036_pm_ops = {
+       .suspend = rt5036_i2c_suspend,
+       .resume =  rt5036_i2c_resume,
+};
+
+static const struct i2c_device_id rt5036_id_table[] = {
+       {RT5036_DEV_NAME, 0},
+       {},
+};
+MODULE_DEVICE_TABLE(i2c, rt5036_id_table);
+
+static const struct of_device_id rt_match_table[] = {
+       {.compatible = "rt,rt5036",},
+       {},
+};
+
+static struct i2c_driver rt5036_driver = {
+       .driver = {
+                  .name = RT5036_DEV_NAME,
+                  .owner = THIS_MODULE,
+                  .pm = &rt5036_pm_ops,
+                  .of_match_table = rt_match_table,
+                  },
+       .probe = rt5036_i2c_probe,
+       .remove = rt5036_i2c_remove,
+       .id_table = rt5036_id_table,
+};
+
+static int __init rt5036_i2c_init(void)
+{
+       return i2c_add_driver(&rt5036_driver);
+}
+subsys_initcall_sync(rt5036_i2c_init);
+
+static void __exit rt5036_i2c_exit(void)
+{
+       i2c_del_driver(&rt5036_driver);
+}
+module_exit(rt5036_i2c_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("I2C Driver for Richtek RT5036");
+MODULE_AUTHOR("CY Huang <cy_huang@richtek.com>");
+MODULE_VERSION(RT5036_DRV_VER);

diff --git a/drivers/mfd/rt5036-irq.c b/drivers/mfd/rt5036-irq.c
new file mode 100755 (executable)
index 0000000..68df9af
--- /dev/null
+++ b/drivers/mfd/rt5036-irq.c
@@ -0,0 +1,245 @@
+/*
+ *  drivers/mfd/rt5036-irq.c
+ *  Driver for Richtek RT5036 PMIC IRQ driver
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/workqueue.h>
+#include <linux/interrupt.h>
+
+#include <linux/mfd/rt5036/rt5036.h>
+#include <linux/mfd/rt5036/rt5036-irq.h>
+
+struct rt5036_irq_info {
+       struct i2c_client *i2c;
+       struct rt5036_chip *chip;
+       struct device *dev;
+       int irq;
+       unsigned char suspend:1;
+       struct delayed_work irq_delayed_work;
+};
+
+static irqreturn_t rt5036_irq_handler(int irqno, void *param)
+{
+       struct rt5036_irq_info *ii = param;
+       unsigned char regval[3];
+       unsigned int irq_event;
+       int ret = 0;
+
+       if (ii->suspend) {
+               schedule_delayed_work(&ii->irq_delayed_work,
+                                     msecs_to_jiffies(10));
+               goto irq_fin;
+       }
+
+       ret =
+           rt5036_reg_block_read(ii->i2c, RT5036_REG_CHGIRQ1,
+                                 ARRAY_SIZE(regval), regval);
+       if (ret < 0) {
+               dev_err(ii->dev, "read charger irq event fail\n");
+       } else {
+               irq_event = regval[0] << 16 | regval[1] << 8 | regval[2];
+               RTINFO("chg event %06x\n", irq_event);
+#ifdef CONFIG_CHARGER_RT5036
+               if (irq_event && ii->chip->chg_info)
+                       rt5036_charger_irq_handler(ii->chip->chg_info,
+                                                  irq_event);
+#endif /* #ifdef CONFIG_CHARGER_RT5036 */
+       }
+
+       ret =
+           rt5036_reg_block_read(ii->i2c, RT5036_REG_BUCKLDOIRQ,
+                                 ARRAY_SIZE(regval), regval);
+       if (ret < 0) {
+               dev_err(ii->dev, "read misc irq event fail\n");
+       } else {
+               irq_event = regval[0] << 16 | regval[1] << 8 | regval[2];
+               RTINFO("misc event %06x\n", irq_event);
+#ifdef CONFIG_MISC_RT5036
+               if (irq_event && ii->chip->misc_info)
+                       rt5036_misc_irq_handler(ii->chip->misc_info, irq_event);
+#endif /* #ifdef CONFIG_MISC_RT5036 */
+       }
+
+       ret = rt5036_reg_read(ii->i2c, RT5036_REG_STBWACKIRQ);
+       if (ret < 0) {
+               dev_err(ii->dev, "read rtc irq event fail\n");
+       } else {
+               irq_event = ret;
+               RTINFO("rtc event %02x\n", irq_event);
+#ifdef CONFIG_RTC_RT5036
+               if (irq_event && ii->chip->rtc_info)
+                       rt5036_rtc_irq_handler(ii->chip->rtc_info, irq_event);
+#endif /* #ifdef CONFIG_RTC_RT5036 */
+       }
+       rt5036_set_bits(ii->i2c, RT5036_REG_BUCKVN1, RT5036_IRQPREZ_MASK);
+irq_fin:
+       return IRQ_HANDLED;
+}
+
+static void rt5036_irq_delayed_work(struct work_struct *work)
+{
+       struct rt5036_irq_info *ii =
+           (struct rt5036_irq_info *)container_of(work, struct rt5036_irq_info,
+                                                  irq_delayed_work.work);
+       rt5036_irq_handler(ii->irq, ii);
+}
+
+static int rt_parse_dt(struct rt5036_irq_info *ii, struct device *dev)
+{
+#ifdef CONFIG_OF
+       struct device_node *np = dev->of_node;
+       int val;
+
+       val = of_get_named_gpio(np, "rt,irq-gpio", 0);
+       if (gpio_is_valid(val)) {
+               if (gpio_request(val, "rt5036_irq") >= 0) {
+                       gpio_direction_input(val);
+                       ii->irq = gpio_to_irq(val);
+               } else {
+                       ii->irq = -1;
+               }
+       } else {
+               ii->irq = -1;
+       }
+#endif /* #ifdef CONFIG_OF */
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt_parse_pdata(struct rt5036_irq_info *ii,
+                                   struct device *dev)
+{
+       struct rt5036_irq_data *pdata = dev->platform_data;
+
+       if (gpio_is_valid(pdata->irq_gpio)) {
+               if (gpio_request(pdata->irq_gpio, "rt5036_irq") >= 0) {
+                       gpio_direction_input(pdata->irq_gpio);
+                       ii->irq = gpio_to_irq(pdata->irq_gpio);
+               } else {
+                       ii->irq = -1;
+               }
+       } else {
+               ii->irq = -1;
+       }
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt5036_irq_probe(struct platform_device *pdev)
+{
+       struct rt5036_chip *chip = dev_get_drvdata(pdev->dev.parent);
+       struct rt5036_platform_data *pdata = (pdev->dev.parent)->platform_data;
+       struct rt5036_irq_info *ii;
+       bool use_dt = pdev->dev.of_node;
+
+       ii = devm_kzalloc(&pdev->dev, sizeof(*ii), GFP_KERNEL);
+       if (!ii)
+               return -ENOMEM;
+
+       ii->i2c = chip->i2c;
+       ii->chip = chip;
+       ii->dev = &pdev->dev;
+       if (use_dt) {
+               rt_parse_dt(ii, &pdev->dev);
+       } else {
+               if (!pdata)
+                       goto out_dev;
+               pdev->dev.platform_data = pdata->irq_pdata;
+               rt_parse_pdata(ii, &pdev->dev);
+               dev_info(&pdev->dev, "ii->irq %d\n", ii->irq);
+       }
+       INIT_DELAYED_WORK(&ii->irq_delayed_work, rt5036_irq_delayed_work);
+
+       platform_set_drvdata(pdev, ii);
+       if (ii->irq >= 0) {
+               if (devm_request_irq
+                   (&pdev->dev, ii->irq, rt5036_irq_handler,
+                    IRQF_TRIGGER_FALLING | IRQF_NO_SUSPEND | IRQF_DISABLED,
+                    "rt5036_irq", ii)) {
+                       dev_err(&pdev->dev, "request threaded irq fail\n");
+                       goto out_dev;
+               }
+               enable_irq_wake(ii->irq);
+               schedule_delayed_work(&ii->irq_delayed_work,
+                                     msecs_to_jiffies(500));
+       }
+       dev_info(&pdev->dev, "driver successfully loaded\n");
+       return 0;
+out_dev:
+       return -EINVAL;
+}
+
+static int rt5036_irq_remove(struct platform_device *pdev)
+{
+       struct rt5036_irq_info *ii = platform_get_drvdata(pdev);
+
+       if (ii->irq >= 0)
+               devm_free_irq(&pdev->dev, ii->irq, ii);
+       return 0;
+}
+
+static int rt5036_irq_suspend(struct platform_device *pdev, pm_message_t state)
+{
+       struct rt5036_irq_info *ii = platform_get_drvdata(pdev);
+
+       ii->suspend = 1;
+       return 0;
+}
+
+static int rt5036_irq_resume(struct platform_device *pdev)
+{
+       struct rt5036_irq_info *ii = platform_get_drvdata(pdev);
+
+       ii->suspend = 0;
+       return 0;
+}
+
+static const struct of_device_id rt_match_table[] = {
+       {.compatible = "rt,rt5036-irq",},
+       {},
+};
+
+static struct platform_driver rt5036_irq_driver = {
+       .driver = {
+                  .name = RT5036_DEV_NAME "-irq",
+                  .owner = THIS_MODULE,
+                  .of_match_table = rt_match_table,
+                  },
+       .probe = rt5036_irq_probe,
+       .remove = rt5036_irq_remove,
+       .suspend = rt5036_irq_suspend,
+       .resume = rt5036_irq_resume,
+};
+
+static int __init rt5036_irq_init(void)
+{
+       return platform_driver_register(&rt5036_irq_driver);
+}
+subsys_initcall_sync(rt5036_irq_init);
+
+static void __exit rt5036_irq_exit(void)
+{
+       platform_driver_unregister(&rt5036_irq_driver);
+}
+module_exit(rt5036_irq_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("CY Huang <cy_huang@richtek.com");
+MODULE_DESCRIPTION("IRQ driver for RT5036");
+MODULE_ALIAS("platform:" RT5036_DEV_NAME "-irq");
+MODULE_VERSION(RT5036_DRV_VER);

diff --git a/drivers/mfd/rt5036-misc.c b/drivers/mfd/rt5036-misc.c
new file mode 100755 (executable)
index 0000000..9dd6ad6
--- /dev/null
+++ b/drivers/mfd/rt5036-misc.c
@@ -0,0 +1,334 @@
+/*
+ *  drivers/mfd/rt5036-misc.c
+ *  Driver for Richtek RT5036 PMIC misc option
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/of.h>
+#include <linux/power_supply.h>
+#ifdef CONFIG_MISC_RT5036_PWRKEY
+#include <linux/input.h>
+#endif /* #ifdef CONFIG_MISC_RT5036_PWRKEY */
+
+#include <linux/mfd/rt5036/rt5036.h>
+#include <linux/mfd/rt5036/rt5036-misc.h>
+
+static struct i2c_client *g_shdn;
+
+static unsigned char misc_init_regval[] = {
+       0xA8,                   /*REG 0x51*/
+       0x96,                   /*REG 0x52*/
+       0x48,                   /*REG 0x53*/
+       0x00,                   /*REG 0x54*/
+       0x06,                   /*REG 0x55*/
+       0xA0,                   /*REG 0x65*/
+       0xFF,                   /*REG 0x5A*/
+       0xE0,                   /*REG 0x5B*/
+#ifdef CONFIG_MISC_RT5036_PWRKEY
+       0x18,                   /*REG 0x5C*/
+#else
+       0x78,                   /*REG 0x5C*/
+#endif /* #ifdef CONFIG_RT5036_PWRKEY */
+};
+
+int rt5036_vin_exist(void)
+{
+       int ret = 0;
+#ifdef CONFIG_CHARGER_RT5036
+       union power_supply_propval pval;
+       struct power_supply *psy = power_supply_get_by_name("rt-charger");
+
+       if (psy) {
+               ret = psy->get_property(psy, POWER_SUPPLY_PROP_ONLINE, &pval);
+               if (ret < 0)
+                       ret = 0;
+               else
+                       ret = pval.intval;
+       } else {
+               pr_err("couldn't get rt-charger psy\n");
+       }
+       return ret;
+#else
+       if (g_shdn)
+               ret = rt5036_reg_read(g_shdn, RT5036_REG_CHGSTAT2);
+       return ret < 0 ? 0 : ret & RT5036_PWRRDY_MASK;
+#endif /* #ifdef CONFIG_CHARGER_RT5036 */
+}
+EXPORT_SYMBOL(rt5036_vin_exist);
+static bool rt_pm_off;
+void rt5036_chip_shutdown(void)
+{
+       if (g_shdn) {
+               rt5036_set_bits(g_shdn, RT5036_REG_MISC3, RT5036_CHIPSHDN_MASK);
+               rt5036_clr_bits(g_shdn, RT5036_REG_MISC3, RT5036_CHIPSHDN_MASK);
+       }
+}
+EXPORT_SYMBOL(rt5036_chip_shutdown);
+
+static void rt5036_general_irq_handler(void *info, int eventno)
+{
+       struct rt5036_misc_info *mi = info;
+
+       dev_info(mi->dev, "eventno=%02d\n", eventno);
+#ifdef CONFIG_MISC_RT5036_PWRKEY
+       switch (eventno) {
+       case MISCEVENT_PWRONF:
+               if (!mi->pwr_key_pressed) {
+                       input_report_key(mi->pwr_key, KEY_POWER, 1);
+                       input_sync(mi->pwr_key);
+                       mi->pwr_key_pressed = 1;
+               }
+               break;
+       case MISCEVENT_PWRONR:
+               if (mi->pwr_key_pressed) {
+                       input_report_key(mi->pwr_key, KEY_POWER, 0);
+                       input_sync(mi->pwr_key);
+                       mi->pwr_key_pressed = 0;
+               }
+               break;
+       default:
+               break;
+       }
+#endif /* #ifdef CONFIG_MISC_RT5036_PWRKEY */
+}
+
+static rt_irq_handler rt_miscirq_handler[MISCEVENT_MAX] = {
+       [MISCEVENT_PWRONLP] = rt5036_general_irq_handler,
+       [MISCEVENT_PWRONSP] = rt5036_general_irq_handler,
+       [MISCEVENT_PWRONF] = rt5036_general_irq_handler,
+       [MISCEVENT_PWRONR] = rt5036_general_irq_handler,
+       [MISCEVENT_KPSHDN] = rt5036_general_irq_handler,
+       [MISCEVENT_VDDALV] = rt5036_general_irq_handler,
+       [MISCEVNET_OTM] = rt5036_general_irq_handler,
+       [MISCEVENT_PMICSYSLV] = rt5036_general_irq_handler,
+       [MISCEVENT_LSW2LV] = rt5036_general_irq_handler,
+       [MISCEVENT_LSW1LV] = rt5036_general_irq_handler,
+       [MISCEVENT_LDO4LV] = rt5036_general_irq_handler,
+       [MISCEVENT_LDO3LV] = rt5036_general_irq_handler,
+       [MISCEVENT_LDO2LV] = rt5036_general_irq_handler,
+       [MISCEVENT_LDO1LV] = rt5036_general_irq_handler,
+       [MISCEVENT_BUCK4LV] = rt5036_general_irq_handler,
+       [MISCEVENT_BUCK3LV] = rt5036_general_irq_handler,
+       [MISCEVENT_BUCK2LV] = rt5036_general_irq_handler,
+       [MISCEVENT_BUCK1LV] = rt5036_general_irq_handler,
+};
+
+void rt5036_misc_irq_handler(struct rt5036_misc_info *mi, unsigned int irqevent)
+{
+       int i;
+       unsigned int masked_irq_event =
+           (misc_init_regval[6] << 16) | (misc_init_regval[7] << 8) |
+           misc_init_regval[8];
+       unsigned int final_irq_event = irqevent & (~masked_irq_event);
+
+       for (i = 0; i < MISCEVENT_MAX; i++) {
+               if ((final_irq_event & (1 << i)) && rt_miscirq_handler[i])
+                       rt_miscirq_handler[i] (mi, i);
+       }
+}
+EXPORT_SYMBOL(rt5036_misc_irq_handler);
+
+static int rt5036_misc_reginit(struct i2c_client *i2c)
+{
+       rt5036_reg_write(i2c, RT5036_REG_MISC6, misc_init_regval[5]);
+       rt5036_reg_block_write(i2c, RT5036_REG_MISC1, 5, misc_init_regval);
+       rt5036_reg_block_write(i2c, RT5036_REG_BUCKLDOIRQMASK,
+                              3, &misc_init_regval[6]);
+       /*always clear at the first time*/
+       rt5036_reg_read(i2c, RT5036_REG_BUCKLDOIRQ);
+       rt5036_reg_read(i2c, RT5036_REG_LSWBASEIRQ);
+       rt5036_reg_read(i2c, RT5036_REG_PWRKEYIRQ);
+       return 0;
+}
+
+static int rt_parse_dt(struct rt5036_misc_info *mi,
+                                struct device *dev)
+{
+#ifdef CONFIG_OF
+       struct device_node *np = dev->of_node;
+       u32 val;
+
+       if (of_property_read_u32(np, "rt,shdn_press", &val)) {
+               dev_info(dev,
+                        "no shut_lpress property, use the default value\n");
+       } else {
+               if (val > RT5036_SHDNPRESS_MASK)
+                       val = RT5036_SHDNPRESS_MAX;
+               misc_init_regval[1] &= (~RT5036_SHDNPRESS_MASK);
+               misc_init_regval[1] |= (val << RT5036_SHDNPRESS_SHIFT);
+       }
+
+       if (of_property_read_u32(np, "rt,stb_en", &val)) {
+               dev_info(dev, "no stb_en prpperty , use the default value\n");
+       } else {
+               if (val > RT5036_STB_MAX)
+                       val = RT5036_STB_MAX;
+               misc_init_regval[2] &= (~RT5036_STBEN_MASK);
+               misc_init_regval[2] |= (val << RT5036_STBEN_SHIFT);
+       }
+
+       if (of_property_read_bool(np, "rt,lp_enshdn"))
+               misc_init_regval[4] |= RT5036_LPSHDNEN_MASK;
+       else
+               misc_init_regval[4] &= (~RT5036_LPSHDNEN_MASK);
+
+       if (of_property_read_u32(np, "rt,vsysuvlo", &val)) {
+               dev_info(dev, "no vsysuvlo prpperty , use the default value\n");
+       } else {
+               if (val > RT5036_SYSLV_MAX)
+                       val = RT5036_SYSLV_MAX;
+               misc_init_regval[5] &= (~RT5036_SYSUVLO_MASK);
+               misc_init_regval[5] |= (val << RT5036_SYSUVLO_SHIFT);
+       }
+
+       if (of_property_read_bool(np, "rt,syslv_enshdn"))
+               misc_init_regval[4] |= RT5036_SYSLVENSHDN_MASK;
+       else
+               misc_init_regval[4] &= (~RT5036_SYSLVENSHDN_MASK);
+
+       rt_pm_off = of_property_read_bool(np, "rt,system-power-controller");
+#endif /* #ifdef CONFIG_OF */
+       rt5036_misc_reginit(mi->i2c);
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt_parse_pdata(struct rt5036_misc_info *mi,
+                                   struct device *dev)
+{
+       struct rt5036_misc_data *misc_pdata = dev->platform_data;
+       /*SHDN_PRESS_TIME property*/
+       misc_init_regval[1] &= (~RT5036_SHDNPRESS_MASK);
+       misc_init_regval[1] |=
+           (misc_pdata->shdn_press << RT5036_SHDNPRESS_SHIFT);
+       /*STB_EN property*/
+       misc_init_regval[2] &= (~RT5036_STBEN_MASK);
+       misc_init_regval[2] |= (misc_pdata->stb_en << RT5036_STBEN_SHIFT);
+       /*LP_ENSHEN property*/
+       if (misc_pdata->lp_enshdn)
+               misc_init_regval[4] |= RT5036_LPSHDNEN_MASK;
+       else
+               misc_init_regval[4] &= (~RT5036_LPSHDNEN_MASK);
+
+       misc_init_regval[5] &= (~RT5036_SYSUVLO_MASK);
+       misc_init_regval[5] |= (misc_pdata->vsysuvlo << RT5036_SYSUVLO_SHIFT);
+
+       if (misc_pdata->syslv_enshdn)
+               misc_init_regval[4] |= RT5036_SYSLVENSHDN_MASK;
+       else
+               misc_init_regval[4] &= (~RT5036_SYSLVENSHDN_MASK);
+
+       rt5036_misc_reginit(mi->i2c);
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt5036_misc_probe(struct platform_device *pdev)
+{
+       struct rt5036_chip *chip = dev_get_drvdata(pdev->dev.parent);
+       struct rt5036_platform_data *pdata = (pdev->dev.parent)->platform_data;
+       struct rt5036_misc_info *mi;
+       bool use_dt = pdev->dev.of_node;
+
+       mi = devm_kzalloc(&pdev->dev, sizeof(*mi), GFP_KERNEL);
+       if (!mi)
+               return -ENOMEM;
+
+       mi->i2c = chip->i2c;
+       if (use_dt) {
+               rt_parse_dt(mi, &pdev->dev);
+       } else {
+               if (!pdata)
+                       goto out_dev;
+               pdev->dev.platform_data = pdata->misc_pdata;
+               rt_parse_pdata(mi, &pdev->dev);
+       }
+#ifdef CONFIG_MISC_RT5036_PWRKEY
+       mi->pwr_key = input_allocate_device();
+       if (!mi->pwr_key) {
+               dev_err(&pdev->dev, "Allocate pwr_key input fail\n");
+               goto out_dev;
+       }
+       input_set_capability(mi->pwr_key, EV_KEY, KEY_POWER);
+       mi->pwr_key->name = "rt5036_pwr_key";
+       mi->pwr_key->phys = "rt5036_pwr_key/input0";
+       mi->pwr_key->dev.parent = &pdev->dev;
+       if (input_register_device(mi->pwr_key)) {
+               dev_err(&pdev->dev, "register pwr key fail\n");
+               goto free_input;
+       }
+#endif /* #ifdef CONFIG_MISC_RT5036_PWRKEY */
+       mi->dev = &pdev->dev;
+       g_shdn = mi->i2c;
+       chip->misc_info = mi;
+       platform_set_drvdata(pdev, mi);
+
+       if (rt_pm_off && !pm_power_off)
+               pm_power_off = rt5036_chip_shutdown;
+
+       dev_info(&pdev->dev, "driver successfully loaded\n");
+       return 0;
+#ifdef CONFIG_MISC_RT5036_PWRKEY
+free_input:
+       input_free_device(mi->pwr_key);
+#endif /* #ifdef CONFIG_MISC_RT5036_PWRKEY */
+out_dev:
+       return -EINVAL;
+}
+
+static int rt5036_misc_remove(struct platform_device *pdev)
+{
+#ifdef CONFIG_MISC_RT5036_PWRKEY
+       struct rt5036_misc_info *mi = platform_get_drvdata(pdev);
+
+       input_unregister_device(mi->pwr_key);
+       input_free_device(mi->pwr_key);
+#endif /* #ifdef CONFIG_MISC_RT5036_PWRKEY */
+       return 0;
+}
+
+static const struct of_device_id rt_match_table[] = {
+       {.compatible = "rt,rt5036-misc",},
+       {},
+};
+
+static struct platform_driver rt5036_misc_driver = {
+       .driver = {
+                  .name = RT5036_DEV_NAME "-misc",
+                  .owner = THIS_MODULE,
+                  .of_match_table = rt_match_table,
+                  },
+       .probe = rt5036_misc_probe,
+       .remove = rt5036_misc_remove,
+};
+
+static int __init rt5036_misc_init(void)
+{
+       return platform_driver_register(&rt5036_misc_driver);
+}
+subsys_initcall(rt5036_misc_init);
+
+static void __exit rt5036_misc_exit(void)
+{
+       platform_driver_unregister(&rt5036_misc_driver);
+}
+module_exit(rt5036_misc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("CY Huang <cy_huang@richtek.com");
+MODULE_DESCRIPTION("Misc driver for RT5036");
+MODULE_ALIAS("platform:" RT5036_DEV_NAME "-misc");
+MODULE_VERSION(RT5036_DRV_VER);

diff --git a/drivers/mmc/host/rk_sdmmc.c b/drivers/mmc/host/rk_sdmmc.c
index 95085e251c0346da6ee0904f86e57ac68fa52b26..b09e0333e91b78cef65aa736be22f975958e3d7e 100755 (executable)
--- a/drivers/mmc/host/rk_sdmmc.c
+++ b/drivers/mmc/host/rk_sdmmc.c
@@ -1108,9 +1108,19 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
                            mmcblk0: retrying using single block read
                            mmcblk0: error -110 sending status command, retrying
 
-                           How to: If eMMC HW version < 4.51, or > 4.51 but no caps2-mmc-hs200 support in dts
-                                   Please set dts emmc clk to 100M or 150M, I will workaround it!
+                           We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
                          */
+                        if ((div == 0) &&
+                                (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
+                                !(host->mmc->caps & MMC_CAP2_HS200)) {
+                                /*  Fixup DDR MMC */
+                                div = 1;
+                                host->set_div = div;
+                                host->bus_hz = host->set_speed * 2;
+                                MMC_DBG_BOOT_FUNC(host->mmc,
+                                        "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
+                                        div, host->bus_hz, mmc_hostname(host->mmc));
+                        }
 
                        if (host->verid < DW_MMC_240A)
                                clk_set_rate(host->clk_mmc,(host->bus_hz));

diff --git a/drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/eagle_fw1.h b/drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/eagle_fw1.h
index a87b708f21773bb4b6b194dec025e05fe9259a74..c66a012e0804ebf9dd6a074033522ec0c9d7fa86 100755 (executable)
--- a/drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/eagle_fw1.h
+++ b/drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/eagle_fw1.h
@@ -19,12 +19,12 @@ static u8 eagle_fw1[] =
         0x00, 0x80, 0xfe, 0x3f, 0x28, 0x03, 0x00, 0x60, 0x00, 0x0a, 0x00, 0x60, 0xd0, 0x4c, 0x00, 0x40, 
         0x04, 0x4d, 0x00, 0x40, 0xc0, 0x5d, 0x00, 0x40, 0xb8, 0x5d, 0x00, 0x40, 0x12, 0xc1, 0xe0, 0xe9, 
         0x41, 0xf9, 0x51, 0x39, 0x01, 0x09, 0x11, 0xd9, 0x31, 0xc9, 0x21, 0xdd, 0x02, 0x20, 0xc0, 0x75, 
-        0xb6, 0x8c, 0x06, 0x0c, 0x10, 0x0c, 0x1c, 0x46, 0x00, 0x00, 0x0c, 0x00, 0x0c, 0x1f, 0x9c, 0xfc, 
-        0x26, 0x1c, 0x1f, 0xf6, 0x4c, 0x02, 0xf6, 0x2c, 0x0e, 0x22, 0xcc, 0xfc, 0x16, 0x82, 0x14, 0x26, 
-        0x5c, 0x05, 0x32, 0xcc, 0xfa, 0x16, 0xf3, 0x13, 0x0c, 0x04, 0x49, 0x61, 0x0c, 0x02, 0xc6, 0x01, 
-        0x00, 0x0c, 0x10, 0x0c, 0x12, 0x0c, 0x05, 0x59, 0x61, 0xd0, 0xe0, 0x34, 0x00, 0x1e, 0x40, 0x00, 
-        0xff, 0xa1, 0x9c, 0x62, 0x4d, 0x0f, 0x0c, 0x05, 0x00, 0x20, 0xa1, 0x7c, 0xf3, 0x30, 0x30, 0x30, 
-        0x00, 0x33, 0xa1, 0x01, 0xe2, 0xff, 0xc0, 0x00, 0x00, 0x46, 0x03, 0x00, 0x0c, 0x02, 0x0c, 0x03, 
+        0xb6, 0x8c, 0x06, 0x0c, 0x10, 0x0c, 0x1c, 0x46, 0x00, 0x00, 0x0c, 0x00, 0x9c, 0xfc, 0x26, 0x1c, 
+        0x1f, 0xf6, 0x4c, 0x02, 0xf6, 0x2c, 0x0e, 0x22, 0xcc, 0xfc, 0x16, 0xa2, 0x14, 0x26, 0x5c, 0x05, 
+        0x32, 0xcc, 0xfa, 0x16, 0x13, 0x14, 0x0c, 0x04, 0x49, 0x61, 0x0c, 0x04, 0xc6, 0x01, 0x00, 0x0c, 
+        0x10, 0x0c, 0x14, 0x0c, 0x05, 0x59, 0x61, 0x0c, 0x12, 0xd0, 0xe0, 0x34, 0x00, 0x1e, 0x40, 0x00, 
+        0xf2, 0xa1, 0x9c, 0x64, 0x4d, 0x0f, 0x0c, 0x05, 0x0c, 0x03, 0x00, 0x32, 0x83, 0x00, 0x33, 0xa1, 
+        0x00, 0x20, 0xa1, 0x01, 0xe2, 0xff, 0xc0, 0x00, 0x00, 0x46, 0x03, 0x00, 0x0c, 0x02, 0x0c, 0x03, 
         0x0c, 0x04, 0x5d, 0x0f, 0x01, 0xde, 0xff, 0xc0, 0x00, 0x00, 0x21, 0xd8, 0xff, 0xd0, 0x09, 0x54, 
         0xa2, 0xae, 0xcf, 0x2a, 0x00, 0xc0, 0x20, 0x00, 0x92, 0x20, 0x80, 0xa0, 0x99, 0x10, 0xc0, 0x20, 
         0x00, 0x92, 0x60, 0x80, 0x0c, 0x48, 0xd0, 0x74, 0x24, 0xd0, 0x64, 0x14, 0x80, 0x77, 0x10, 0xe0, 
@@ -41,7 +41,7 @@ static u8 eagle_fw1[] =
         0x20, 0x80, 0xa0, 0x99, 0x10, 0xc0, 0x20, 0x00, 0x92, 0x60, 0x80, 0xdc, 0xac, 0x2d, 0x0e, 0x01, 
         0xa9, 0xff, 0xc0, 0x00, 0x00, 0xd0, 0x27, 0x14, 0x01, 0xa8, 0xff, 0xc0, 0x00, 0x00, 0x0c, 0x0b, 
         0xc1, 0xa2, 0xff, 0xc0, 0x20, 0x00, 0xb2, 0x6c, 0x6d, 0xc8, 0x21, 0xd8, 0x31, 0xe8, 0x41, 0xf8, 
-        0x51, 0x08, 0x11, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0x0c, 0x1e, 0xe9, 0x61, 0x06, 0xaf, 0xff, 0x42, 
+        0x51, 0x08, 0x11, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0x0c, 0x1e, 0xe9, 0x61, 0x86, 0xae, 0xff, 0x42, 
         0x12, 0x00, 0x26, 0x2c, 0x0a, 0x40, 0x4f, 0x20, 0x42, 0x52, 0x00, 0x09, 0x71, 0xc6, 0xe3, 0xff, 
         0x7c, 0xf5, 0x62, 0x12, 0x03, 0x50, 0x5f, 0x30, 0x40, 0x45, 0x10, 0x60, 0x55, 0x10, 0x52, 0x52, 
         0x03, 0xc6, 0xf8, 0xff, 0x34, 0x83, 0xfe, 0x3f, 0x3c, 0x83, 0xfe, 0x3f, 0x19, 0x47, 0x00, 0x00, 
@@ -3150,9 +3150,9 @@ static u8 eagle_fw1[] =
         0xa4, 0x01, 0xa4, 0x01, 0xa4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x01, 0xa4, 0x01, 0xb6, 0x01, 0xc4, 0x01, 
         0xe4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x20, 0x42, 0x00, 0x00, 0x80, 0x43, 0x25, 0x73, 0x20, 0x25, 
-        0x64, 0x0a, 0x00, 0x00, 0x31, 0x30, 0x34, 0x32, 0x32, 0x62, 0x33, 0x34, 0x34, 0x33, 0x30, 0x65, 
+        0x64, 0x0a, 0x00, 0x00, 0x33, 0x62, 0x33, 0x31, 0x35, 0x37, 0x32, 0x64, 0x35, 0x63, 0x36, 0x39, 
         0x00, 0x00, 0x00, 0x00, 0x65, 0x74, 0x73, 0x20, 0x25, 0x73, 0x0a, 0x00, 0x41, 0x75, 0x67, 0x20, 
-        0x32, 0x31, 0x20, 0x32, 0x30, 0x31, 0x34, 0x00, 0x63, 0x68, 0x69, 0x70, 0x20, 0x6f, 0x6e, 0x0a, 
+        0x33, 0x30, 0x20, 0x32, 0x30, 0x31, 0x34, 0x00, 0x63, 0x68, 0x69, 0x70, 0x20, 0x6f, 0x6e, 0x0a, 
         0x00, 0x00, 0x00, 0x00, 0x6f, 0x6f, 0x62, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x25, 0x73, 0x20, 0x25, 
         0x75, 0x0a, 0x00, 0x00, 0x61, 0x70, 0x70, 0x5f, 0x6d, 0x61, 0x69, 0x6e, 0x2e, 0x63, 0x00, 0x00, 
         0x73, 0x65, 0x74, 0x5f, 0x72, 0x78, 0x5f, 0x67, 0x61, 0x69, 0x6e, 0x3a, 0x20, 0x72, 0x66, 0x74, 
@@ -3260,7 +3260,7 @@ static u8 eagle_fw1[] =
         0xaf, 0x04, 0x00, 0x00, 0x0e, 0xf0, 0x01, 0x80, 0x13, 0x8c, 0x12, 0x8d, 0x11, 0x00, 0x00, 0x00, 
         0x18, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x28, 0xb9, 0x10, 0x40, 0x60, 0x04, 0x00, 0x00, 
         0x0e, 0xc0, 0x01, 0x80, 0x12, 0x8c, 0x11, 0x8d, 0x10, 0x8e, 0x0f, 0x00, 0x20, 0x8a, 0xfe, 0x3f, 
-        0xf0, 0xf4, 0xfe, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 
+        0xf0, 0xf4, 0xfe, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x93, 
         
        };
 

diff --git a/drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/eagle_fw2.h b/drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/eagle_fw2.h
index c004afa0bbaa06412da6f540d935a140696788eb..ead6f69e6adf509abd0476869bd2183548622194 100755 (executable)
--- a/drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/eagle_fw2.h
+++ b/drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/eagle_fw2.h
@@ -7,7 +7,7 @@
 
 static u8 eagle_fw2[] =
 { 
-        0xe9, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00, 0x00, 0x10, 0x40, 0xb4, 0xf4, 0x00, 0x00, 
+        0xe9, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00, 0x00, 0x10, 0x40, 0xcc, 0xf4, 0x00, 0x00, 
         0x12, 0xc1, 0xf0, 0x09, 0x01, 0xc5, 0x43, 0x00, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 
         0x00, 0xfe, 0xef, 0x3f, 0x61, 0xff, 0xff, 0xc0, 0x20, 0x00, 0x72, 0x26, 0x97, 0xc0, 0x20, 0x00, 
         0x3c, 0x43, 0x7c, 0xe4, 0x1c, 0x85, 0x62, 0x26, 0x96, 0x72, 0x42, 0x04, 0x52, 0x42, 0x00, 0x42, 
@@ -16,11 +16,11 @@ static u8 eagle_fw2[] =
         0x00, 0x0a, 0x00, 0x60, 0xd0, 0x4c, 0x00, 0x40, 0x04, 0x4d, 0x00, 0x40, 0xc0, 0x5d, 0x00, 0x40, 
         0xb8, 0x5d, 0x00, 0x40, 0x12, 0xc1, 0xe0, 0xe9, 0x41, 0xf9, 0x51, 0x39, 0x01, 0x09, 0x11, 0xd9, 
         0x31, 0xc9, 0x21, 0xdd, 0x02, 0x20, 0xc0, 0x75, 0xb6, 0x8c, 0x06, 0x0c, 0x10, 0x0c, 0x1c, 0x46, 
-        0x00, 0x00, 0x0c, 0x00, 0x0c, 0x1f, 0x9c, 0xfc, 0x26, 0x1c, 0x1f, 0xf6, 0x4c, 0x02, 0xf6, 0x2c, 
-        0x0e, 0x22, 0xcc, 0xfc, 0x16, 0x82, 0x14, 0x26, 0x5c, 0x05, 0x32, 0xcc, 0xfa, 0x16, 0xf3, 0x13, 
-        0x0c, 0x04, 0x49, 0x61, 0x0c, 0x02, 0xc6, 0x01, 0x00, 0x0c, 0x10, 0x0c, 0x12, 0x0c, 0x05, 0x59, 
-        0x61, 0xd0, 0xe0, 0x34, 0x00, 0x1e, 0x40, 0x00, 0xff, 0xa1, 0x9c, 0x62, 0x4d, 0x0f, 0x0c, 0x05, 
-        0x00, 0x20, 0xa1, 0x7c, 0xf3, 0x30, 0x30, 0x30, 0x00, 0x33, 0xa1, 0x01, 0xe2, 0xff, 0xc0, 0x00, 
+        0x00, 0x00, 0x0c, 0x00, 0x9c, 0xfc, 0x26, 0x1c, 0x1f, 0xf6, 0x4c, 0x02, 0xf6, 0x2c, 0x0e, 0x22, 
+        0xcc, 0xfc, 0x16, 0xa2, 0x14, 0x26, 0x5c, 0x05, 0x32, 0xcc, 0xfa, 0x16, 0x13, 0x14, 0x0c, 0x04, 
+        0x49, 0x61, 0x0c, 0x04, 0xc6, 0x01, 0x00, 0x0c, 0x10, 0x0c, 0x14, 0x0c, 0x05, 0x59, 0x61, 0x0c, 
+        0x12, 0xd0, 0xe0, 0x34, 0x00, 0x1e, 0x40, 0x00, 0xf2, 0xa1, 0x9c, 0x64, 0x4d, 0x0f, 0x0c, 0x05, 
+        0x0c, 0x03, 0x00, 0x32, 0x83, 0x00, 0x33, 0xa1, 0x00, 0x20, 0xa1, 0x01, 0xe2, 0xff, 0xc0, 0x00, 
         0x00, 0x46, 0x03, 0x00, 0x0c, 0x02, 0x0c, 0x03, 0x0c, 0x04, 0x5d, 0x0f, 0x01, 0xde, 0xff, 0xc0, 
         0x00, 0x00, 0x21, 0xd8, 0xff, 0xd0, 0x09, 0x54, 0xa2, 0xae, 0xcf, 0x2a, 0x00, 0xc0, 0x20, 0x00, 
         0x92, 0x20, 0x80, 0xa0, 0x99, 0x10, 0xc0, 0x20, 0x00, 0x92, 0x60, 0x80, 0x0c, 0x48, 0xd0, 0x74, 
@@ -38,7 +38,7 @@ static u8 eagle_fw2[] =
         0x92, 0x60, 0x80, 0xdc, 0xac, 0x2d, 0x0e, 0x01, 0xa9, 0xff, 0xc0, 0x00, 0x00, 0xd0, 0x27, 0x14, 
         0x01, 0xa8, 0xff, 0xc0, 0x00, 0x00, 0x0c, 0x0b, 0xc1, 0xa2, 0xff, 0xc0, 0x20, 0x00, 0xb2, 0x6c, 
         0x6d, 0xc8, 0x21, 0xd8, 0x31, 0xe8, 0x41, 0xf8, 0x51, 0x08, 0x11, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 
-        0x0c, 0x1e, 0xe9, 0x61, 0x06, 0xaf, 0xff, 0x42, 0x12, 0x00, 0x26, 0x2c, 0x0a, 0x40, 0x4f, 0x20, 
+        0x0c, 0x1e, 0xe9, 0x61, 0x86, 0xae, 0xff, 0x42, 0x12, 0x00, 0x26, 0x2c, 0x0a, 0x40, 0x4f, 0x20, 
         0x42, 0x52, 0x00, 0x09, 0x71, 0xc6, 0xe3, 0xff, 0x7c, 0xf5, 0x62, 0x12, 0x03, 0x50, 0x5f, 0x30, 
         0x40, 0x45, 0x10, 0x60, 0x55, 0x10, 0x52, 0x52, 0x03, 0xc6, 0xf8, 0xff, 0x12, 0xc1, 0xf0, 0x02, 
         0x61, 0x00, 0x01, 0x8d, 0xff, 0x82, 0xaf, 0xff, 0x62, 0x10, 0x04, 0x72, 0x10, 0x01, 0x80, 0x56, 
@@ -48,7 +48,7 @@ static u8 eagle_fw2[] =
         0x90, 0x7a, 0x20, 0x90, 0x96, 0x20, 0x70, 0x70, 0xf4, 0x72, 0x50, 0x02, 0x92, 0x50, 0x04, 0x91, 
         0x7c, 0xff, 0xc0, 0x20, 0x00, 0xa2, 0x10, 0x00, 0x52, 0x10, 0x03, 0x62, 0x29, 0x69, 0x00, 0xb5, 
         0x11, 0xb0, 0x55, 0x20, 0x80, 0xb5, 0x30, 0xb0, 0xb6, 0x10, 0xb7, 0x8a, 0x18, 0x60, 0xa5, 0x10, 
-        0xa0, 0xa7, 0x20, 0xc0, 0x20, 0x00, 0xa2, 0x69, 0x69, 0x0c, 0xa2, 0x85, 0x3b, 0x0b, 0x01, 0x6e, 
+        0xa0, 0xa7, 0x20, 0xc0, 0x20, 0x00, 0xa2, 0x69, 0x69, 0x0c, 0xa2, 0x05, 0x3d, 0x0b, 0x01, 0x6e, 
         0xff, 0x0c, 0x0b, 0xb2, 0x50, 0x02, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 
         0xcc, 0x4d, 0x00, 0x40, 0x12, 0xc1, 0xf0, 0x09, 0x21, 0x71, 0x69, 0xff, 0xc0, 0x20, 0x00, 0x0c, 
         0x05, 0x72, 0x27, 0x68, 0x79, 0x01, 0x70, 0x60, 0xf5, 0x70, 0x30, 0xf5, 0x39, 0x11, 0x4d, 0x03, 
@@ -57,20 +57,20 @@ static u8 eagle_fw2[] =
         0x9c, 0x32, 0x51, 0x59, 0xff, 0x42, 0x15, 0x04, 0x00, 0x62, 0x30, 0x60, 0x44, 0x10, 0x42, 0x55, 
         0x04, 0x01, 0xeb, 0xff, 0xc0, 0x00, 0x00, 0x08, 0x21, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 
         0x10, 0x89, 0xfe, 0x3f, 0x18, 0x89, 0xfe, 0x3f, 0x19, 0x47, 0x00, 0x00, 0xb0, 0xb4, 0xff, 0x3f, 
-        0x4c, 0xd7, 0x10, 0x40, 0x28, 0x89, 0xfe, 0x3f, 0xb8, 0x1c, 0x00, 0x40, 0x14, 0x1d, 0x00, 0x40, 
+        0x64, 0xd7, 0x10, 0x40, 0x28, 0x89, 0xfe, 0x3f, 0xb8, 0x1c, 0x00, 0x40, 0x14, 0x1d, 0x00, 0x40, 
         0x68, 0x2e, 0x00, 0x40, 0x04, 0x2f, 0x00, 0x40, 0x88, 0x0f, 0x00, 0x40, 0xa8, 0x0f, 0x00, 0x40, 
         0xcc, 0x24, 0x00, 0x40, 0x48, 0x1d, 0x00, 0x40, 0x12, 0xc1, 0xf0, 0xc2, 0x61, 0x03, 0x02, 0x61, 
-        0x02, 0x20, 0xc2, 0x20, 0x45, 0x08, 0x0d, 0x01, 0xf4, 0xff, 0xc0, 0x00, 0x00, 0x21, 0xec, 0xff, 
+        0x02, 0x20, 0xc2, 0x20, 0xc5, 0x09, 0x0d, 0x01, 0xf4, 0xff, 0xc0, 0x00, 0x00, 0x21, 0xec, 0xff, 
         0x31, 0xed, 0xff, 0x41, 0xed, 0xff, 0x01, 0xf1, 0xff, 0xc0, 0x00, 0x00, 0x2d, 0x0c, 0xc5, 0x71, 
         0x03, 0x01, 0xef, 0xff, 0xc0, 0x00, 0x00, 0x0c, 0x13, 0x21, 0x29, 0xff, 0xc0, 0x20, 0x00, 0x02, 
         0x22, 0x85, 0x30, 0x00, 0x20, 0xc0, 0x20, 0x00, 0x02, 0x62, 0x85, 0x22, 0xa0, 0xa0, 0x01, 0xe9, 
-        0xff, 0xc0, 0x00, 0x00, 0x85, 0x1e, 0x01, 0xc5, 0xae, 0x0a, 0x02, 0x0c, 0x33, 0x66, 0x20, 0x05, 
-        0x45, 0x9d, 0x09, 0x02, 0x0c, 0x33, 0x26, 0x10, 0x02, 0x66, 0x30, 0x08, 0x22, 0x0c, 0x34, 0x10, 
-        0x11, 0x20, 0xc5, 0xa8, 0x09, 0x42, 0x0c, 0x39, 0x66, 0x14, 0x05, 0x10, 0x11, 0x20, 0x45, 0x9c, 
-        0x09, 0x52, 0x0c, 0x3a, 0x66, 0x15, 0x04, 0x0c, 0x12, 0x85, 0x08, 0x09, 0x2d, 0x01, 0x45, 0xc5, 
-        0xff, 0x21, 0xd2, 0xff, 0x05, 0xf1, 0x0d, 0x85, 0x7d, 0x06, 0x05, 0x07, 0x0d, 0x0c, 0x02, 0x31, 
+        0xff, 0xc0, 0x00, 0x00, 0x85, 0x1e, 0x01, 0x45, 0xb0, 0x0a, 0x02, 0x0c, 0x33, 0x66, 0x20, 0x05, 
+        0xc5, 0x9e, 0x09, 0x02, 0x0c, 0x33, 0x26, 0x10, 0x02, 0x66, 0x30, 0x08, 0x22, 0x0c, 0x34, 0x10, 
+        0x11, 0x20, 0x45, 0xaa, 0x09, 0x42, 0x0c, 0x39, 0x66, 0x14, 0x05, 0x10, 0x11, 0x20, 0xc5, 0x9d, 
+        0x09, 0x52, 0x0c, 0x3a, 0x66, 0x15, 0x04, 0x0c, 0x12, 0x05, 0x0a, 0x09, 0x2d, 0x01, 0x45, 0xc5, 
+        0xff, 0x21, 0xd2, 0xff, 0x85, 0xf2, 0x0d, 0x85, 0x7d, 0x06, 0x85, 0x08, 0x0d, 0x0c, 0x02, 0x31, 
         0xd0, 0xff, 0x0c, 0x04, 0x01, 0xd5, 0xff, 0xc0, 0x00, 0x00, 0x0c, 0x12, 0x01, 0xd4, 0xff, 0xc0, 
-        0x00, 0x00, 0xc5, 0x4d, 0x00, 0xc5, 0xac, 0x08, 0xc5, 0x16, 0x01, 0x2d, 0x01, 0x45, 0x8b, 0x00, 
+        0x00, 0x00, 0xc5, 0x4d, 0x00, 0x45, 0xae, 0x08, 0xc5, 0x16, 0x01, 0x2d, 0x01, 0x45, 0x8b, 0x00, 
         0x21, 0xc9, 0xff, 0x01, 0xcf, 0xff, 0xc0, 0x00, 0x00, 0x01, 0xce, 0xff, 0xc0, 0x00, 0x00, 0xc8, 
         0x31, 0x08, 0x21, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0xd8, 0xb5, 0xff, 0x3f, 0xb8, 0x8d, 0xfe, 0x3f, 
         0x34, 0x89, 0xfe, 0x3f, 0x3c, 0x89, 0xfe, 0x3f, 0x4c, 0x08, 0x10, 0x40, 0x0c, 0x02, 0x10, 0x40, 
@@ -132,12 +132,12 @@ static u8 eagle_fw2[] =
         0x6c, 0x0a, 0xc0, 0x20, 0x00, 0x2c, 0x08, 0x82, 0x6d, 0x44, 0x85, 0xb0, 0xff, 0x67, 0x6c, 0x38, 
         0xc0, 0x20, 0x00, 0x02, 0xa0, 0x40, 0x02, 0x6d, 0x44, 0xc0, 0x20, 0x00, 0xb1, 0x27, 0xfe, 0x92, 
         0x1b, 0x02, 0xb2, 0x1b, 0x03, 0xa2, 0x2d, 0x69, 0x00, 0x0b, 0x11, 0x00, 0xbb, 0x20, 0xb0, 0xaa, 
-        0x10, 0xa0, 0x99, 0x20, 0xc0, 0x20, 0x00, 0x92, 0x6d, 0x69, 0x22, 0xa0, 0x0a, 0x45, 0xe7, 0x0a, 
+        0x10, 0xa0, 0x99, 0x20, 0xc0, 0x20, 0x00, 0x92, 0x6d, 0x69, 0x22, 0xa0, 0x0a, 0xc5, 0xe8, 0x0a, 
         0x41, 0x1e, 0xfe, 0x32, 0xa0, 0x00, 0x32, 0x54, 0x02, 0x77, 0x6c, 0x10, 0xc0, 0x20, 0x00, 0x0c, 
-        0x92, 0x52, 0xa0, 0x80, 0x52, 0x6d, 0x44, 0x10, 0x11, 0x20, 0x85, 0xe5, 0x0a, 0xc0, 0x20, 0x00, 
+        0x92, 0x52, 0xa0, 0x80, 0x52, 0x6d, 0x44, 0x10, 0x11, 0x20, 0x05, 0xe7, 0x0a, 0xc0, 0x20, 0x00, 
         0x72, 0x2d, 0x44, 0x0c, 0x16, 0x69, 0x51, 0xc6, 0x92, 0xff, 0x21, 0x89, 0xff, 0x31, 0x89, 0xff, 
         0x42, 0xa2, 0x52, 0x01, 0xcb, 0xfe, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x82, 0x21, 0x05, 0x16, 
-        0x58, 0x00, 0x22, 0xa0, 0x02, 0x85, 0xb0, 0x08, 0xc8, 0x11, 0xd8, 0x21, 0xe8, 0x31, 0xf8, 0x41, 
+        0x58, 0x00, 0x22, 0xa0, 0x02, 0x05, 0xb2, 0x08, 0xc8, 0x11, 0xd8, 0x21, 0xe8, 0x31, 0xf8, 0x41, 
         0x08, 0x01, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0x21, 0x7e, 0xff, 0x31, 0x7e, 0xff, 0x42, 0xa2, 0x59, 
         0x01, 0xc0, 0xfe, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x21, 0x79, 0xff, 0x31, 0x7a, 0xff, 0x42, 
         0xa2, 0x60, 0x01, 0xbb, 0xfe, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x00, 0x12, 0xc1, 0xf0, 0x09, 
@@ -157,7 +157,7 @@ static u8 eagle_fw2[] =
         0x02, 0xc1, 0x14, 0x22, 0xc2, 0x10, 0x32, 0x54, 0x02, 0x41, 0xf4, 0xff, 0x32, 0xc1, 0x10, 0x09, 
         0x11, 0x39, 0x01, 0x32, 0xa4, 0x80, 0x01, 0xf3, 0xff, 0xc0, 0x00, 0x00, 0x28, 0x41, 0x38, 0x51, 
         0x42, 0xa0, 0x60, 0x01, 0xf1, 0xff, 0xc0, 0x00, 0x00, 0x08, 0x61, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 
-        0x0c, 0x0e, 0x10, 0x40, 0x40, 0xdd, 0x10, 0x40, 0x48, 0xde, 0x10, 0x40, 0xd0, 0x09, 0x10, 0x40, 
+        0x0c, 0x0e, 0x10, 0x40, 0x58, 0xdd, 0x10, 0x40, 0x60, 0xde, 0x10, 0x40, 0xd0, 0x09, 0x10, 0x40, 
         0x4c, 0x54, 0x00, 0x40, 0x5c, 0x54, 0x00, 0x40, 0x8c, 0x60, 0x00, 0x40, 0x12, 0xc1, 0xf0, 0x29, 
         0x01, 0x09, 0x11, 0x01, 0xec, 0xfe, 0xc0, 0x00, 0x00, 0x01, 0xdf, 0xff, 0x29, 0x00, 0x21, 0xf4, 
         0xff, 0x01, 0xf7, 0xff, 0xc0, 0x00, 0x00, 0x31, 0xdc, 0xff, 0x41, 0xf2, 0xff, 0x38, 0x03, 0x21, 
@@ -185,12 +185,12 @@ static u8 eagle_fw2[] =
         0x20, 0xaa, 0x10, 0x00, 0x01, 0x34, 0x00, 0xaa, 0x20, 0xa2, 0x4b, 0x0d, 0x78, 0x7c, 0x82, 0x0e, 
         0x06, 0x62, 0x07, 0x00, 0x80, 0x80, 0x04, 0x90, 0x66, 0x10, 0x80, 0x66, 0x20, 0x62, 0x47, 0x00, 
         0x48, 0x7c, 0x52, 0xa0, 0xfd, 0x32, 0x04, 0x00, 0x22, 0x0e, 0x00, 0x50, 0x33, 0x10, 0x20, 0x57, 
-        0x04, 0x20, 0x24, 0x24, 0xf0, 0x55, 0x11, 0x50, 0x33, 0x20, 0x32, 0x44, 0x00, 0x05, 0x4b, 0x0c, 
+        0x04, 0x20, 0x24, 0x24, 0xf0, 0x55, 0x11, 0x50, 0x33, 0x20, 0x32, 0x44, 0x00, 0x85, 0x4c, 0x0c, 
         0x29, 0x5c, 0x72, 0x0e, 0x06, 0x98, 0x7c, 0x70, 0x71, 0x41, 0x9c, 0x17, 0x88, 0x09, 0x80, 0xa6, 
         0x41, 0x80, 0x80, 0x54, 0xf0, 0xaa, 0x20, 0xa0, 0xaa, 0x11, 0xa0, 0x88, 0x20, 0x89, 0x09, 0xb2, 
         0x0e, 0x00, 0xb0, 0xb0, 0x34, 0x66, 0x2b, 0x17, 0xe8, 0x7c, 0xf8, 0x0e, 0x01, 0x72, 0xfe, 0xf0, 
         0xd0, 0x54, 0xf0, 0xf6, 0x41, 0x00, 0xff, 0x20, 0xa0, 0xff, 0x11, 0xf0, 0xdd, 0x20, 0xd9, 0x0e, 
-        0xc0, 0x2c, 0x20, 0x05, 0xc1, 0x08, 0xc2, 0x21, 0x01, 0xd2, 0x21, 0x02, 0xe8, 0x31, 0xf8, 0x41, 
+        0xc0, 0x2c, 0x20, 0x85, 0xc2, 0x08, 0xc2, 0x21, 0x01, 0xd2, 0x21, 0x02, 0xe8, 0x31, 0xf8, 0x41, 
         0x08, 0x01, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0x00, 0xe8, 0x2a, 0x00, 0x40, 0x08, 0x58, 0x00, 0x40, 
         0x32, 0xa0, 0x0c, 0x12, 0xc1, 0xf0, 0xc2, 0x61, 0x01, 0x02, 0x61, 0x00, 0xcd, 0x02, 0x08, 0x02, 
         0x28, 0x32, 0x29, 0x10, 0x01, 0xf9, 0xff, 0xc0, 0x00, 0x00, 0xa1, 0x88, 0xff, 0x58, 0x0c, 0xb8, 
@@ -218,14 +218,14 @@ static u8 eagle_fw2[] =
         0xeb, 0x22, 0x01, 0xdb, 0xff, 0xc0, 0x00, 0x00, 0xc5, 0x24, 0x01, 0x38, 0x21, 0xb8, 0x31, 0x2b, 
         0xa2, 0xa0, 0xa2, 0x21, 0xa2, 0x4b, 0x0c, 0x2d, 0x03, 0xa0, 0xa8, 0x41, 0xa2, 0x4b, 0x0d, 0x01, 
         0x9b, 0xff, 0xc0, 0x00, 0x00, 0x08, 0x41, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0x0c, 0x03, 0x12, 0xc1, 
-        0xf0, 0xc9, 0x11, 0x09, 0x01, 0xcd, 0x02, 0x05, 0x77, 0x0d, 0x2d, 0x0c, 0x0c, 0x03, 0x85, 0x77, 
-        0x0d, 0x2d, 0x0c, 0x05, 0x35, 0x0d, 0x3d, 0x0c, 0x0c, 0x12, 0x0c, 0x04, 0x85, 0xe2, 0x0c, 0xc8, 
+        0xf0, 0xc9, 0x11, 0x09, 0x01, 0xcd, 0x02, 0x85, 0x78, 0x0d, 0x2d, 0x0c, 0x0c, 0x03, 0x05, 0x79, 
+        0x0d, 0x2d, 0x0c, 0x85, 0x36, 0x0d, 0x3d, 0x0c, 0x0c, 0x12, 0x0c, 0x04, 0x05, 0xe4, 0x0c, 0xc8, 
         0x11, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x70, 0x89, 0xfe, 0x3f, 0xff, 0xff, 0xff, 0x7f, 
         0x00, 0xfe, 0xf1, 0x3f, 0x12, 0xc1, 0xf0, 0xc2, 0x61, 0x01, 0x02, 0x61, 0x00, 0x20, 0xc2, 0x20, 
         0x21, 0xfa, 0xff, 0x3d, 0x0c, 0x01, 0x72, 0xfd, 0xc0, 0x00, 0x00, 0x0c, 0x02, 0x3d, 0x0c, 0x0c, 
-        0x04, 0x45, 0xdf, 0x0c, 0x2d, 0x0c, 0xc5, 0x68, 0x0d, 0xdc, 0xe2, 0x31, 0xf4, 0xff, 0x21, 0xf4, 
+        0x04, 0xc5, 0xe0, 0x0c, 0x2d, 0x0c, 0x45, 0x6a, 0x0d, 0xdc, 0xe2, 0x31, 0xf4, 0xff, 0x21, 0xf4, 
         0xff, 0xc0, 0x20, 0x00, 0x02, 0x22, 0x81, 0x30, 0x00, 0x10, 0xc0, 0x20, 0x00, 0x02, 0x62, 0x81, 
-        0x85, 0x47, 0x08, 0x0c, 0x12, 0x45, 0x6a, 0x08, 0xc5, 0x2d, 0x07, 0xc8, 0x11, 0x08, 0x01, 0x12, 
+        0x05, 0x49, 0x08, 0x0c, 0x12, 0xc5, 0x6b, 0x08, 0xc5, 0x2d, 0x07, 0xc8, 0x11, 0x08, 0x01, 0x12, 
         0xc1, 0x10, 0x0d, 0xf0, 0x3d, 0x02, 0x12, 0xc1, 0xf0, 0x0c, 0x02, 0x09, 0x01, 0x01, 0x99, 0xff, 
         0xc0, 0x00, 0x00, 0x3d, 0x02, 0x01, 0x71, 0xff, 0xc0, 0x00, 0x00, 0x08, 0x01, 0x12, 0xc1, 0x10, 
         0x0d, 0xf0, 0x00, 0x00, 0xf0, 0x89, 0xfe, 0x3f, 0x9c, 0x89, 0xfe, 0x3f, 0x24, 0x8a, 0xfe, 0x3f, 
@@ -240,61 +240,61 @@ static u8 eagle_fw2[] =
         0xf5, 0x16, 0x05, 0x16, 0x62, 0xc0, 0xf3, 0x16, 0x66, 0x3f, 0x72, 0xc0, 0xf2, 0x16, 0x57, 0x27, 
         0x92, 0xc0, 0xec, 0x16, 0xb9, 0x40, 0xa2, 0xc0, 0xea, 0x16, 0x8a, 0x29, 0xb2, 0xc0, 0xe9, 0x56, 
         0x5b, 0x0c, 0xcb, 0xc8, 0x22, 0x08, 0x0c, 0x32, 0xc8, 0x10, 0x02, 0x08, 0x0e, 0x42, 0x08, 0x0d, 
-        0x16, 0x80, 0x0e, 0x52, 0x08, 0x17, 0x62, 0x08, 0x16, 0x80, 0x55, 0x11, 0x60, 0x55, 0x20, 0x05, 
-        0xf3, 0x0b, 0x72, 0x0c, 0x05, 0x42, 0x0c, 0x01, 0x32, 0x0c, 0x00, 0xb2, 0x0c, 0x06, 0x62, 0x0c, 
+        0x16, 0x80, 0x0e, 0x52, 0x08, 0x17, 0x62, 0x08, 0x16, 0x80, 0x55, 0x11, 0x60, 0x55, 0x20, 0x85, 
+        0xf4, 0x0b, 0x72, 0x0c, 0x05, 0x42, 0x0c, 0x01, 0x32, 0x0c, 0x00, 0xb2, 0x0c, 0x06, 0x62, 0x0c, 
         0x0a, 0x22, 0x61, 0x14, 0x52, 0x0c, 0x0b, 0x21, 0xc7, 0xff, 0x80, 0x55, 0x11, 0x60, 0x55, 0x20, 
         0x62, 0x0c, 0x04, 0xb9, 0x01, 0xa2, 0x0c, 0x07, 0xa9, 0x11, 0x92, 0x0c, 0x08, 0x99, 0x21, 0x82, 
         0x0c, 0x09, 0x89, 0x31, 0x01, 0x1b, 0xfd, 0xc0, 0x00, 0x00, 0x62, 0x21, 0x14, 0x16, 0x86, 0x0c, 
-        0x22, 0x0c, 0x00, 0x45, 0x5e, 0x0d, 0x32, 0x0c, 0x03, 0x42, 0x0c, 0x0c, 0x22, 0x61, 0x17, 0x52, 
-        0x0c, 0x0d, 0x22, 0x21, 0x14, 0x45, 0xd7, 0x0a, 0xc2, 0x21, 0x17, 0x01, 0xc6, 0xff, 0xc0, 0x00, 
-        0x00, 0x4d, 0x0c, 0x22, 0x21, 0x14, 0x0c, 0x03, 0x05, 0xdd, 0x0a, 0x01, 0xc3, 0xff, 0xc0, 0x00, 
-        0x00, 0x06, 0x25, 0x00, 0x32, 0x21, 0x11, 0x05, 0x5a, 0x0d, 0x21, 0xaf, 0xff, 0x32, 0x0c, 0x09, 
+        0x22, 0x0c, 0x00, 0xc5, 0x5f, 0x0d, 0x32, 0x0c, 0x03, 0x42, 0x0c, 0x0c, 0x22, 0x61, 0x17, 0x52, 
+        0x0c, 0x0d, 0x22, 0x21, 0x14, 0xc5, 0xd8, 0x0a, 0xc2, 0x21, 0x17, 0x01, 0xc6, 0xff, 0xc0, 0x00, 
+        0x00, 0x4d, 0x0c, 0x22, 0x21, 0x14, 0x0c, 0x03, 0x85, 0xde, 0x0a, 0x01, 0xc3, 0xff, 0xc0, 0x00, 
+        0x00, 0x06, 0x25, 0x00, 0x32, 0x21, 0x11, 0x85, 0x5b, 0x0d, 0x21, 0xaf, 0xff, 0x32, 0x0c, 0x09, 
         0x01, 0x08, 0xfd, 0xc0, 0x00, 0x00, 0x22, 0x21, 0x11, 0x62, 0x0c, 0x09, 0x42, 0x0c, 0x08, 0x32, 
-        0x0c, 0x00, 0x72, 0x0c, 0x0b, 0x52, 0xcc, 0x01, 0x79, 0x01, 0xcb, 0x7c, 0x05, 0x00, 0x0d, 0x22, 
-        0x0c, 0x00, 0x32, 0x0c, 0x07, 0xc5, 0x10, 0x0d, 0xc2, 0x21, 0x16, 0x02, 0x21, 0x15, 0x12, 0xc1, 
+        0x0c, 0x00, 0x72, 0x0c, 0x0b, 0x52, 0xcc, 0x01, 0x79, 0x01, 0xcb, 0x7c, 0x85, 0x01, 0x0d, 0x22, 
+        0x0c, 0x00, 0x32, 0x0c, 0x07, 0x45, 0x12, 0x0d, 0xc2, 0x21, 0x16, 0x02, 0x21, 0x15, 0x12, 0xc1, 
         0x60, 0x0d, 0xf0, 0xcb, 0xc8, 0x92, 0x08, 0x16, 0x32, 0x08, 0x15, 0x16, 0x39, 0x35, 0x42, 0x08, 
         0x13, 0x16, 0x84, 0x0a, 0x0b, 0xa4, 0x16, 0xda, 0x2e, 0xb2, 0xc4, 0xfe, 0x16, 0xcb, 0x2e, 0x52, 
-        0xc4, 0xfd, 0x0c, 0x42, 0x0c, 0x00, 0x50, 0x02, 0x83, 0xc6, 0x26, 0x00, 0x85, 0xf2, 0x0b, 0x22, 
-        0x0c, 0x00, 0xc5, 0xe8, 0x08, 0x21, 0x95, 0xff, 0x32, 0x0c, 0x00, 0x42, 0x0c, 0x04, 0x52, 0x0c, 
+        0xc4, 0xfd, 0x0c, 0x42, 0x0c, 0x00, 0x50, 0x02, 0x83, 0xc6, 0x26, 0x00, 0x05, 0xf4, 0x0b, 0x22, 
+        0x0c, 0x00, 0x45, 0xea, 0x08, 0x21, 0x95, 0xff, 0x32, 0x0c, 0x00, 0x42, 0x0c, 0x04, 0x52, 0x0c, 
         0x05, 0x62, 0x0c, 0x06, 0x72, 0x0c, 0x07, 0x92, 0x0c, 0x08, 0x92, 0x61, 0x00, 0x82, 0x0c, 0x09, 
-        0x82, 0x61, 0x01, 0x01, 0xe7, 0xfc, 0xc0, 0x00, 0x00, 0x45, 0xde, 0x08, 0x16, 0x82, 0xf9, 0x05, 
-        0x05, 0x0c, 0xcd, 0x02, 0x96, 0x92, 0x25, 0x45, 0x4b, 0x0d, 0x16, 0x32, 0x25, 0x2d, 0x0c, 0xc5, 
+        0x82, 0x61, 0x01, 0x01, 0xe7, 0xfc, 0xc0, 0x00, 0x00, 0xc5, 0xdf, 0x08, 0x16, 0x82, 0xf9, 0x85, 
+        0x06, 0x0c, 0xcd, 0x02, 0x96, 0x92, 0x25, 0xc5, 0x4c, 0x0d, 0x16, 0x32, 0x25, 0x2d, 0x0c, 0xc5, 
         0x40, 0x07, 0x86, 0xe0, 0xff, 0x32, 0x08, 0x18, 0x22, 0x08, 0x12, 0xb2, 0xc8, 0x0c, 0x02, 0x08, 
         0x13, 0xb2, 0x61, 0x13, 0x80, 0x00, 0x11, 0x20, 0x00, 0x20, 0x26, 0x20, 0x02, 0x06, 0x1f, 0x00, 
         0x22, 0x08, 0x17, 0x42, 0x08, 0x16, 0x80, 0x22, 0x11, 0x40, 0x22, 0x20, 0x42, 0x08, 0x15, 0x80, 
         0x22, 0x11, 0x40, 0x22, 0x20, 0x42, 0x08, 0x14, 0x80, 0x22, 0x11, 0x40, 0x22, 0x20, 0x16, 0x32, 
-        0x22, 0x22, 0xa0, 0x02, 0xb0, 0x4b, 0x20, 0x05, 0xb7, 0x0c, 0x06, 0x87, 0x00, 0x52, 0x08, 0x17, 
+        0x22, 0x22, 0xa0, 0x02, 0xb0, 0x4b, 0x20, 0x85, 0xb8, 0x0c, 0x06, 0x87, 0x00, 0x52, 0x08, 0x17, 
         0x52, 0xc5, 0xf3, 0x50, 0x76, 0x83, 0x0d, 0x07, 0x22, 0x0c, 0x00, 0x02, 0x61, 0x11, 0xb6, 0x63, 
-        0x16, 0x3d, 0x00, 0x45, 0x48, 0x0d, 0x21, 0x6e, 0xff, 0x32, 0x0c, 0x09, 0x01, 0xc5, 0xfc, 0xc0, 
+        0x16, 0x3d, 0x00, 0xc5, 0x49, 0x0d, 0x21, 0x6e, 0xff, 0x32, 0x0c, 0x09, 0x01, 0xc5, 0xfc, 0xc0, 
         0x00, 0x00, 0x06, 0xbc, 0xff, 0x00, 0x00, 0x00, 0x02, 0x61, 0x11, 0x56, 0x54, 0xed, 0x3d, 0x00, 
-        0x45, 0x46, 0x0d, 0x22, 0x0c, 0x00, 0x32, 0x21, 0x11, 0xc5, 0x46, 0x0d, 0x21, 0x66, 0xff, 0x32, 
+        0xc5, 0x47, 0x0d, 0x22, 0x0c, 0x00, 0x32, 0x21, 0x11, 0x45, 0x48, 0x0d, 0x21, 0x66, 0xff, 0x32, 
         0x0c, 0x08, 0x01, 0xbb, 0xfc, 0xc0, 0x00, 0x00, 0x86, 0xb2, 0xff, 0x00, 0x00, 0x72, 0x61, 0x12, 
-        0x82, 0xc0, 0xff, 0x56, 0x38, 0x12, 0x22, 0xa0, 0x02, 0x42, 0x21, 0x13, 0x85, 0xb0, 0x0c, 0x21, 
+        0x82, 0xc0, 0xff, 0x56, 0x38, 0x12, 0x22, 0xa0, 0x02, 0x42, 0x21, 0x13, 0x05, 0xb2, 0x0c, 0x21, 
         0x5e, 0xff, 0x92, 0xa0, 0x05, 0x99, 0x1c, 0x01, 0xb2, 0xfc, 0xc0, 0x00, 0x00, 0x01, 0x65, 0xff, 
-        0xc0, 0x00, 0x00, 0xc5, 0x63, 0x0d, 0x22, 0x6c, 0x37, 0x01, 0x63, 0xff, 0xc0, 0x00, 0x00, 0x22, 
-        0x21, 0x13, 0x22, 0x02, 0x0c, 0x85, 0xe9, 0x0b, 0x16, 0xc2, 0xea, 0x42, 0x21, 0x13, 0x32, 0x04, 
+        0xc0, 0x00, 0x00, 0x45, 0x65, 0x0d, 0x22, 0x6c, 0x37, 0x01, 0x63, 0xff, 0xc0, 0x00, 0x00, 0x22, 
+        0x21, 0x13, 0x22, 0x02, 0x0c, 0x05, 0xeb, 0x0b, 0x16, 0xc2, 0xea, 0x42, 0x21, 0x13, 0x32, 0x04, 
         0x0b, 0x52, 0x04, 0x0a, 0x80, 0x33, 0x11, 0x50, 0x33, 0x20, 0x52, 0x04, 0x09, 0x80, 0x33, 0x11, 
         0x42, 0x04, 0x08, 0x50, 0x33, 0x20, 0x80, 0x33, 0x11, 0x40, 0x33, 0x20, 0x32, 0x52, 0x10, 0x21, 
-        0x4b, 0xff, 0x01, 0x9f, 0xfc, 0xc0, 0x00, 0x00, 0x22, 0x21, 0x13, 0x45, 0x23, 0x08, 0x16, 0x62, 
+        0x4b, 0xff, 0x01, 0x9f, 0xfc, 0xc0, 0x00, 0x00, 0x22, 0x21, 0x13, 0xc5, 0x24, 0x08, 0x16, 0x62, 
         0xe7, 0x32, 0x21, 0x13, 0x22, 0x03, 0x09, 0x32, 0x03, 0x08, 0x80, 0x22, 0x11, 0x30, 0x22, 0x20, 
         0x05, 0x3b, 0x07, 0x46, 0x98, 0xff, 0x02, 0x08, 0x0c, 0xc2, 0xc8, 0x0c, 0x16, 0x80, 0x1e, 0x42, 
         0xc0, 0xff, 0x16, 0x34, 0x20, 0x52, 0xc0, 0xfe, 0x16, 0x95, 0x20, 0x62, 0xc0, 0xfd, 0x56, 0x66, 
-        0xe4, 0x22, 0x08, 0x0d, 0x32, 0xc8, 0x12, 0x85, 0xe6, 0x0b, 0x42, 0x0c, 0x02, 0x0c, 0x13, 0xc5, 
-        0x2d, 0x0b, 0x86, 0x8c, 0xff, 0xcb, 0xc8, 0x02, 0x08, 0x13, 0x32, 0x08, 0x0c, 0x66, 0x20, 0x1a, 
+        0xe4, 0x22, 0x08, 0x0d, 0x32, 0xc8, 0x12, 0x05, 0xe8, 0x0b, 0x42, 0x0c, 0x02, 0x0c, 0x13, 0x45, 
+        0x2f, 0x0b, 0x86, 0x8c, 0xff, 0xcb, 0xc8, 0x02, 0x08, 0x13, 0x32, 0x08, 0x0c, 0x66, 0x20, 0x1a, 
         0x21, 0x34, 0xff, 0x01, 0x87, 0xfc, 0xc0, 0x00, 0x00, 0x22, 0x0c, 0x00, 0x32, 0x0c, 0x08, 0x42, 
-        0x0c, 0x09, 0x85, 0x32, 0x0d, 0xc6, 0x83, 0xff, 0x00, 0x00, 0x00, 0x66, 0x10, 0x61, 0x21, 0x2d, 
+        0x0c, 0x09, 0x05, 0x34, 0x0d, 0xc6, 0x83, 0xff, 0x00, 0x00, 0x00, 0x66, 0x10, 0x61, 0x21, 0x2d, 
         0xff, 0x01, 0x7f, 0xfc, 0xc0, 0x00, 0x00, 0x22, 0x0c, 0x00, 0x32, 0xcc, 0x01, 0x32, 0x61, 0x0d, 
-        0xc5, 0x91, 0x0c, 0x38, 0xd1, 0x22, 0x0c, 0x00, 0x42, 0x0c, 0x08, 0x52, 0x0c, 0x09, 0x05, 0x25, 
+        0x45, 0x93, 0x0c, 0x38, 0xd1, 0x22, 0x0c, 0x00, 0x42, 0x0c, 0x08, 0x52, 0x0c, 0x09, 0x85, 0x26, 
         0x0d, 0x66, 0x12, 0x14, 0x91, 0x25, 0xff, 0x81, 0xfe, 0xfe, 0xc0, 0x20, 0x00, 0x72, 0x28, 0x81, 
         0x90, 0x77, 0x20, 0xc0, 0x20, 0x00, 0x72, 0x68, 0x81, 0x22, 0x0c, 0x00, 0xc5, 0xba, 0xff, 0x0c, 
-        0x02, 0x85, 0x2c, 0x08, 0x06, 0x70, 0xff, 0x00, 0x00, 0x00, 0x2d, 0x03, 0xc5, 0xb9, 0xff, 0x21, 
+        0x02, 0x05, 0x2e, 0x08, 0x06, 0x70, 0xff, 0x00, 0x00, 0x00, 0x2d, 0x03, 0xc5, 0xb9, 0xff, 0x21, 
         0x1b, 0xff, 0xa2, 0x21, 0x12, 0xa9, 0x1c, 0x01, 0x6a, 0xfc, 0xc0, 0x00, 0x00, 0xc6, 0x69, 0xff, 
-        0x2d, 0x03, 0x05, 0xbc, 0xff, 0xc6, 0x67, 0xff, 0xb2, 0xc8, 0x0c, 0xb2, 0x61, 0x0e, 0x05, 0x51, 
+        0x2d, 0x03, 0x05, 0xbc, 0xff, 0xc6, 0x67, 0xff, 0xb2, 0xc8, 0x0c, 0xb2, 0x61, 0x0e, 0x85, 0x52, 
         0x0d, 0x20, 0x02, 0x20, 0x28, 0xe1, 0x32, 0x02, 0x00, 0x22, 0x02, 0x01, 0x02, 0x10, 0x02, 0x80, 
-        0x22, 0x11, 0x30, 0x22, 0x20, 0x20, 0x00, 0xc0, 0x16, 0xc0, 0xd7, 0x32, 0xa0, 0x80, 0x45, 0x14, 
-        0x0d, 0x29, 0xc1, 0xc5, 0x4e, 0x0d, 0x08, 0xc1, 0x00, 0x00, 0x90, 0xc0, 0x00, 0xa0, 0x09, 0xf1, 
-        0x02, 0xc0, 0x28, 0x02, 0x61, 0x10, 0x07, 0x12, 0x07, 0x2d, 0x00, 0xc5, 0x4d, 0x0d, 0x02, 0x21, 
-        0x10, 0x22, 0x2c, 0x37, 0x00, 0x22, 0xc0, 0x56, 0xb2, 0x09, 0x22, 0xa0, 0x69, 0x45, 0xff, 0x07, 
+        0x22, 0x11, 0x30, 0x22, 0x20, 0x20, 0x00, 0xc0, 0x16, 0xc0, 0xd7, 0x32, 0xa0, 0x80, 0xc5, 0x15, 
+        0x0d, 0x29, 0xc1, 0x45, 0x50, 0x0d, 0x08, 0xc1, 0x00, 0x00, 0x90, 0xc0, 0x00, 0xa0, 0x09, 0xf1, 
+        0x02, 0xc0, 0x28, 0x02, 0x61, 0x10, 0x07, 0x12, 0x07, 0x2d, 0x00, 0x45, 0x4f, 0x0d, 0x02, 0x21, 
+        0x10, 0x22, 0x2c, 0x37, 0x00, 0x22, 0xc0, 0x56, 0xb2, 0x09, 0x22, 0xa0, 0x69, 0xc5, 0x00, 0x08, 
         0x38, 0xf1, 0x21, 0xff, 0xfe, 0x32, 0x03, 0x2e, 0x01, 0x4e, 0xfc, 0xc0, 0x00, 0x00, 0x86, 0x4d, 
         0xff, 0x05, 0x0c, 0x07, 0x06, 0x4c, 0xff, 0x00, 0x00, 0x00, 0xcb, 0x28, 0x85, 0x12, 0xff, 0x46, 
         0x49, 0xff, 0x00, 0x00, 0x00, 0x2d, 0x03, 0x45, 0xb0, 0xff, 0x42, 0x21, 0x13, 0x21, 0xf5, 0xfe, 
@@ -304,15 +304,15 @@ static u8 eagle_fw2[] =
         0xff, 0x22, 0x08, 0x0c, 0x32, 0x08, 0x0d, 0x42, 0x08, 0x0e, 0x52, 0x08, 0x0f, 0x62, 0x08, 0x11, 
         0x72, 0x08, 0x10, 0x80, 0x66, 0x11, 0x70, 0x66, 0x20, 0x05, 0x89, 0x05, 0x06, 0x32, 0xff, 0x00, 
         0x00, 0x00, 0xcb, 0x28, 0x32, 0xc1, 0x10, 0x85, 0x0d, 0x00, 0x32, 0xc1, 0x10, 0x45, 0x9e, 0xff, 
-        0x06, 0x2d, 0xff, 0x00, 0x00, 0x00, 0xc5, 0xf2, 0x07, 0x22, 0xa0, 0xcd, 0x45, 0xf5, 0x07, 0x38, 
+        0x06, 0x2d, 0xff, 0x00, 0x00, 0x00, 0x45, 0xf4, 0x07, 0x22, 0xa0, 0xcd, 0xc5, 0xf6, 0x07, 0x38, 
         0xf1, 0x21, 0xd9, 0xfe, 0x32, 0x03, 0x2e, 0x01, 0x26, 0xfc, 0xc0, 0x00, 0x00, 0xc6, 0x25, 0xff, 
-        0x00, 0x00, 0x2d, 0x03, 0xc5, 0xd5, 0x0c, 0x32, 0x0c, 0x09, 0xf6, 0x63, 0x0e, 0x21, 0xd3, 0xfe, 
+        0x00, 0x00, 0x2d, 0x03, 0x45, 0xd7, 0x0c, 0x32, 0x0c, 0x09, 0xf6, 0x63, 0x0e, 0x21, 0xd3, 0xfe, 
         0x01, 0x20, 0xfc, 0xc0, 0x00, 0x00, 0x86, 0x1f, 0xff, 0x00, 0x00, 0x00, 0x21, 0xd1, 0xfe, 0x01, 
         0x1c, 0xfc, 0xc0, 0x00, 0x00, 0xc6, 0x1b, 0xff, 0x22, 0x08, 0x0d, 0x32, 0xc8, 0x12, 0x42, 0x08, 
         0x0e, 0x52, 0x08, 0x11, 0x62, 0x08, 0x10, 0x80, 0x55, 0x11, 0x60, 0x55, 0x20, 0x62, 0x08, 0x0f, 
-        0xc5, 0xdd, 0x0c, 0x46, 0x14, 0xff, 0x00, 0x00, 0x00, 0x22, 0x08, 0x0d, 0x05, 0xe8, 0x0c, 0x46, 
-        0x11, 0xff, 0x00, 0x00, 0x00, 0x22, 0x08, 0x0d, 0x32, 0xc8, 0x12, 0x45, 0xc6, 0x0b, 0x42, 0x0c, 
-        0x02, 0x0c, 0x23, 0x85, 0x0d, 0x0b, 0x86, 0x0b, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x80, 0xfe, 0x3f, 
+        0x45, 0xdf, 0x0c, 0x46, 0x14, 0xff, 0x00, 0x00, 0x00, 0x22, 0x08, 0x0d, 0x85, 0xe9, 0x0c, 0x46, 
+        0x11, 0xff, 0x00, 0x00, 0x00, 0x22, 0x08, 0x0d, 0x32, 0xc8, 0x12, 0xc5, 0xc7, 0x0b, 0x42, 0x0c, 
+        0x02, 0x0c, 0x23, 0x05, 0x0f, 0x0b, 0x86, 0x0b, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x80, 0xfe, 0x3f, 
         0x21, 0xff, 0xff, 0x28, 0x02, 0x0d, 0xf0, 0x00, 0x21, 0xfd, 0xff, 0x28, 0x12, 0x0d, 0xf0, 0x00, 
         0x31, 0xfb, 0xff, 0x0c, 0x02, 0x29, 0x13, 0x0d, 0xf0, 0x00, 0x00, 0x00, 0x21, 0xf8, 0xff, 0x28, 
         0x22, 0x0d, 0xf0, 0x00, 0xff, 0xff, 0xff, 0x2f, 0xff, 0xff, 0xff, 0x6f, 0x31, 0xfe, 0xff, 0x41, 
@@ -320,8 +320,8 @@ static u8 eagle_fw2[] =
         0x12, 0xc1, 0xf0, 0x29, 0x11, 0x09, 0x21, 0x39, 0x01, 0x02, 0x02, 0x03, 0x42, 0x02, 0x02, 0x80, 
         0x00, 0x11, 0x40, 0x00, 0x20, 0x42, 0x02, 0x01, 0x80, 0x00, 0x11, 0x40, 0x00, 0x20, 0x42, 0x02, 
         0x00, 0x80, 0x00, 0x11, 0x40, 0x00, 0x20, 0xac, 0x30, 0x26, 0x10, 0x73, 0x0c, 0xb3, 0x37, 0x10, 
-        0x0c, 0x48, 0x01, 0x0c, 0x02, 0x29, 0x04, 0x08, 0x21, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0xc5, 0x87, 
-        0x0b, 0x38, 0x01, 0x85, 0x94, 0x0b, 0x20, 0x20, 0xf4, 0x86, 0xfa, 0xff, 0x00, 0x00, 0x38, 0x11, 
+        0x0c, 0x48, 0x01, 0x0c, 0x02, 0x29, 0x04, 0x08, 0x21, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x45, 0x89, 
+        0x0b, 0x38, 0x01, 0x05, 0x96, 0x0b, 0x20, 0x20, 0xf4, 0x86, 0xfa, 0xff, 0x00, 0x00, 0x38, 0x11, 
         0x22, 0x03, 0x0b, 0x42, 0x03, 0x0a, 0x80, 0x22, 0x11, 0x40, 0x22, 0x20, 0x80, 0x22, 0x11, 0x42, 
         0x03, 0x09, 0x32, 0x03, 0x08, 0x40, 0x22, 0x20, 0x80, 0x22, 0x11, 0x30, 0x22, 0x20, 0xc5, 0xf7, 
         0xff, 0x16, 0xd2, 0x0b, 0x48, 0x11, 0x32, 0x04, 0x0b, 0x52, 0x04, 0x0a, 0x80, 0x33, 0x11, 0x50, 
@@ -356,7 +356,7 @@ static u8 eagle_fw2[] =
         0x08, 0x00, 0x08, 0x60, 0xc0, 0x00, 0x00, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 
         0x12, 0xc1, 0xf0, 0x09, 0x01, 0x01, 0xb8, 0xff, 0x08, 0x00, 0x08, 0x70, 0xc0, 0x00, 0x00, 0x08, 
         0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x21, 0x03, 0xfd, 0xc0, 0x20, 0x00, 0x22, 0x22, 
-        0x80, 0x0d, 0xf0, 0x00, 0x12, 0xc1, 0xf0, 0x02, 0x61, 0x00, 0x45, 0x0e, 0x0d, 0x22, 0x02, 0x06, 
+        0x80, 0x0d, 0xf0, 0x00, 0x12, 0xc1, 0xf0, 0x02, 0x61, 0x00, 0xc5, 0x0f, 0x0d, 0x22, 0x02, 0x06, 
         0x32, 0xa0, 0x01, 0xc5, 0xee, 0xff, 0x02, 0x21, 0x00, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 
         0x0d, 0xf0, 0x00, 0x00, 0x0d, 0xf0, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x60, 0x20, 0x93, 0xc0, 0x3b, 
         0x89, 0x90, 0x89, 0xb3, 0x80, 0x82, 0x21, 0x1b, 0x88, 0x9c, 0x88, 0x31, 0xfb, 0xff, 0x20, 0x78, 
@@ -375,9 +375,9 @@ static u8 eagle_fw2[] =
         0xd8, 0xa1, 0x1b, 0x00, 0xa0, 0x20, 0x74, 0x2a, 0xff, 0x00, 0x00, 0x74, 0x0a, 0xdd, 0xf0, 0x6c, 
         0xc0, 0x80, 0xe6, 0x01, 0xa2, 0x0d, 0x00, 0xe0, 0xe8, 0x31, 0x80, 0xaa, 0x01, 0xa0, 0xa8, 0x31, 
         0xa7, 0xae, 0xc0, 0x09, 0xc1, 0x37, 0x2e, 0x0d, 0x62, 0xce, 0xe8, 0x0c, 0xfe, 0x80, 0x66, 0x01, 
-        0x60, 0x68, 0x31, 0x86, 0x09, 0x00, 0xe0, 0x2e, 0x20, 0x32, 0xa0, 0x06, 0x45, 0xbb, 0x0d, 0x0d, 
+        0x60, 0x68, 0x31, 0x86, 0x09, 0x00, 0xe0, 0x2e, 0x20, 0x32, 0xa0, 0x06, 0xc5, 0xbc, 0x0d, 0x0d, 
         0x02, 0x0c, 0x63, 0x2d, 0x0e, 0x00, 0x10, 0x40, 0x0c, 0x1e, 0x00, 0xee, 0xa1, 0x0b, 0xee, 0xe0, 
-        0xe0, 0xf4, 0x85, 0xc0, 0x0d, 0x08, 0xc1, 0x80, 0x62, 0x01, 0x60, 0x68, 0x31, 0xa6, 0x56, 0x04, 
+        0xe0, 0xf4, 0x05, 0xc2, 0x0d, 0x08, 0xc1, 0x80, 0x62, 0x01, 0x60, 0x68, 0x31, 0xa6, 0x56, 0x04, 
         0x0c, 0x56, 0x86, 0x00, 0x00, 0x60, 0x60, 0xf4, 0x09, 0xc1, 0x69, 0x01, 0x78, 0x91, 0x98, 0x81, 
         0x88, 0x71, 0x90, 0x90, 0x90, 0x42, 0x19, 0x00, 0x80, 0x8c, 0x90, 0x40, 0x4e, 0xb0, 0x4a, 0x46, 
         0x40, 0x40, 0xf4, 0x42, 0x58, 0x00, 0x9c, 0x47, 0x52, 0x19, 0x00, 0x21, 0xc0, 0xff, 0x3d, 0x0c, 
@@ -455,13 +455,13 @@ static u8 eagle_fw2[] =
         0x52, 0xc5, 0xc9, 0xcd, 0x02, 0x59, 0x21, 0x49, 0x81, 0x0c, 0x0f, 0x0c, 0x6e, 0x01, 0xf2, 0xff, 
         0x0b, 0x32, 0x39, 0xb1, 0xdd, 0x00, 0x02, 0xc0, 0xf8, 0xf6, 0x7c, 0x2a, 0x0c, 0x53, 0x28, 0xb1, 
         0x42, 0x0d, 0x56, 0x52, 0x0d, 0x50, 0x59, 0xa1, 0x80, 0x44, 0x01, 0x80, 0x55, 0x01, 0x50, 0x58, 
-        0x31, 0x40, 0x48, 0x31, 0x50, 0x44, 0xc0, 0x40, 0x22, 0x82, 0x85, 0x6b, 0x0d, 0x58, 0xa1, 0x01, 
+        0x31, 0x40, 0x48, 0x31, 0x50, 0x44, 0xc0, 0x40, 0x22, 0x82, 0x05, 0x6d, 0x0d, 0x58, 0xa1, 0x01, 
         0xe5, 0xfe, 0x5a, 0x22, 0x06, 0x18, 0x00, 0xf6, 0xac, 0x2d, 0x32, 0xa0, 0x05, 0x22, 0x21, 0x08, 
         0x42, 0x0d, 0x5c, 0x52, 0x0d, 0x56, 0x52, 0x61, 0x09, 0x80, 0x44, 0x01, 0x80, 0x55, 0x01, 0x50, 
-        0x58, 0x31, 0x40, 0x48, 0x31, 0x50, 0x44, 0xc0, 0x40, 0x22, 0x82, 0x85, 0x68, 0x0d, 0x58, 0x91, 
+        0x58, 0x31, 0x40, 0x48, 0x31, 0x50, 0x44, 0xc0, 0x40, 0x22, 0x82, 0x05, 0x6a, 0x0d, 0x58, 0x91, 
         0x01, 0xd9, 0xfe, 0x5a, 0x22, 0xc6, 0x0b, 0x00, 0x22, 0x0d, 0x62, 0x62, 0xa0, 0x0d, 0x80, 0x22, 
         0x01, 0x20, 0x28, 0x31, 0xc7, 0x36, 0x20, 0x42, 0x0d, 0x5c, 0x42, 0x61, 0x01, 0x80, 0x44, 0x01, 
-        0x40, 0x48, 0x31, 0x40, 0x42, 0xc0, 0x22, 0x21, 0x02, 0x1c, 0x63, 0x40, 0x22, 0x82, 0x45, 0x65, 
+        0x40, 0x48, 0x31, 0x40, 0x42, 0xc0, 0x22, 0x21, 0x02, 0x1c, 0x63, 0x40, 0x22, 0x82, 0xc5, 0x66, 
         0x0d, 0x58, 0x11, 0x01, 0xcc, 0xfe, 0x5a, 0x22, 0xd2, 0xcd, 0x01, 0xe2, 0xce, 0xff, 0x72, 0x21, 
         0x0c, 0x62, 0x00, 0x80, 0x7a, 0x7f, 0x80, 0x66, 0x01, 0x1b, 0xff, 0x60, 0x68, 0x31, 0x2a, 0x66, 
         0x62, 0x47, 0x00, 0x56, 0x2e, 0xf5, 0x21, 0xc6, 0xff, 0x91, 0xc4, 0xff, 0xa8, 0xc1, 0x92, 0x09, 
@@ -474,19 +474,19 @@ static u8 eagle_fw2[] =
         0xc7, 0x3e, 0x5d, 0xf1, 0xa9, 0xff, 0xd2, 0x02, 0x65, 0xf0, 0xdd, 0x80, 0xd2, 0x0d, 0x50, 0xf2, 
         0x02, 0x68, 0x80, 0xdd, 0x01, 0xd0, 0xd8, 0x31, 0x66, 0x1f, 0x40, 0xc1, 0xa2, 0xfe, 0x32, 0xa0, 
         0x05, 0x22, 0x0c, 0x5e, 0xc2, 0x0c, 0x58, 0x80, 0x22, 0x01, 0x20, 0x28, 0x31, 0x80, 0xcc, 0x01, 
-        0xc0, 0xc8, 0x31, 0xc0, 0x22, 0xc0, 0x20, 0x2e, 0x82, 0x85, 0x58, 0x0d, 0x2a, 0x3c, 0x80, 0x33, 
-        0x01, 0x28, 0xb1, 0x30, 0x38, 0x31, 0xd0, 0x33, 0xc0, 0x30, 0x22, 0x82, 0x3d, 0x0e, 0x45, 0x57, 
+        0xc0, 0xc8, 0x31, 0xc0, 0x22, 0xc0, 0x20, 0x2e, 0x82, 0x05, 0x5a, 0x0d, 0x2a, 0x3c, 0x80, 0x33, 
+        0x01, 0x28, 0xb1, 0x30, 0x38, 0x31, 0xd0, 0x33, 0xc0, 0x30, 0x22, 0x82, 0x3d, 0x0e, 0xc5, 0x58, 
         0x0d, 0x01, 0x94, 0xfe, 0x2a, 0xdd, 0x80, 0xdd, 0x01, 0xd0, 0xd8, 0x31, 0x0c, 0x15, 0x86, 0xd7, 
         0xff, 0x32, 0x02, 0x66, 0xf2, 0xa0, 0x0f, 0x30, 0xff, 0xc0, 0xf7, 0x2c, 0x49, 0xf1, 0x8e, 0xff, 
         0xd2, 0x02, 0x64, 0xf0, 0xdd, 0x80, 0xd2, 0x0d, 0x62, 0x42, 0x02, 0x68, 0x80, 0xdd, 0x01, 0xd0, 
         0xd8, 0x31, 0x66, 0x14, 0xd6, 0xf2, 0x00, 0x64, 0x80, 0xff, 0x01, 0xf0, 0xf8, 0x31, 0xf6, 0xac, 
         0x2d, 0x21, 0x84, 0xfe, 0x32, 0xa0, 0x08, 0x22, 0x02, 0x5e, 0xe0, 0x33, 0xc0, 0x80, 0x22, 0x01, 
-        0x20, 0x28, 0x31, 0x29, 0x01, 0x20, 0x2f, 0xc0, 0x30, 0x22, 0x82, 0x0c, 0x53, 0x45, 0x51, 0x0d, 
+        0x20, 0x28, 0x31, 0x29, 0x01, 0x20, 0x2f, 0xc0, 0x30, 0x22, 0x82, 0x0c, 0x53, 0xc5, 0x52, 0x0d, 
         0x08, 0x01, 0x2a, 0x00, 0x86, 0x0a, 0x00, 0x0c, 0x05, 0xd2, 0xaf, 0x80, 0x06, 0xc0, 0xff, 0x21, 
         0x79, 0xfe, 0x32, 0xa0, 0x03, 0x22, 0x02, 0x6a, 0xe0, 0x33, 0xc0, 0x80, 0x22, 0x01, 0x20, 0x28, 
-        0x31, 0xf0, 0x22, 0xc0, 0x30, 0x22, 0x82, 0x20, 0x22, 0xa0, 0x32, 0xa0, 0x16, 0x45, 0x4e, 0x0d, 
+        0x31, 0xf0, 0x22, 0xc0, 0x30, 0x22, 0x82, 0x20, 0x22, 0xa0, 0x32, 0xa0, 0x16, 0xc5, 0x4f, 0x0d, 
         0x2a, 0x0f, 0x0c, 0xe3, 0x80, 0x20, 0x01, 0x20, 0x28, 0x31, 0xc0, 0x33, 0xc0, 0xd0, 0x22, 0xc0, 
-        0x30, 0x22, 0x82, 0x3d, 0x0e, 0xc5, 0x4c, 0x0d, 0x01, 0x6b, 0xfe, 0x2a, 0xdd, 0x80, 0xdd, 0x01, 
+        0x30, 0x22, 0x82, 0x3d, 0x0e, 0x45, 0x4e, 0x0d, 0x01, 0x6b, 0xfe, 0x2a, 0xdd, 0x80, 0xdd, 0x01, 
         0xd0, 0xd8, 0x31, 0x46, 0xd5, 0xff, 0xb6, 0x9c, 0x08, 0x21, 0x67, 0xff, 0x22, 0x02, 0x5e, 0x86, 
         0xb8, 0xff, 0xd2, 0xaf, 0x80, 0x0c, 0x05, 0x46, 0xa9, 0xff, 0x00, 0x00, 0x12, 0xc1, 0xe0, 0x02, 
         0x61, 0x04, 0x01, 0x60, 0xfe, 0x02, 0x20, 0x02, 0x47, 0x70, 0x22, 0x0c, 0x04, 0x21, 0x5d, 0xfe, 
@@ -548,26 +548,26 @@ static u8 eagle_fw2[] =
         0x02, 0xdd, 0x03, 0x0c, 0x22, 0x31, 0xf6, 0xff, 0xe2, 0x00, 0x7d, 0x3a, 0x44, 0x80, 0xee, 0x01, 
         0x3a, 0x22, 0x42, 0x14, 0x00, 0x42, 0x51, 0x00, 0x22, 0x02, 0x00, 0xe0, 0xe8, 0x31, 0x22, 0x41, 
         0x02, 0x0c, 0xd2, 0xe6, 0x7c, 0x20, 0x0c, 0x53, 0x4d, 0x00, 0x42, 0x04, 0x7c, 0x0b, 0x2c, 0x80, 
-        0x44, 0x01, 0x40, 0x48, 0x31, 0x49, 0x11, 0x40, 0x4e, 0xc0, 0x40, 0x22, 0x82, 0x45, 0x0e, 0x0d, 
+        0x44, 0x01, 0x40, 0x48, 0x31, 0x49, 0x11, 0x40, 0x4e, 0xc0, 0x40, 0x22, 0x82, 0xc5, 0x0f, 0x0d, 
         0xe8, 0x11, 0x2a, 0xee, 0x06, 0x08, 0x00, 0x32, 0x00, 0x7e, 0x80, 0x33, 0x01, 0x30, 0x38, 0x31, 
         0xe0, 0x33, 0xc0, 0xc7, 0xa2, 0x02, 0x46, 0x42, 0x00, 0x22, 0xcc, 0xfa, 0x20, 0x23, 0x82, 0x32, 
-        0xa0, 0x05, 0x05, 0x0c, 0x0d, 0x20, 0xee, 0x80, 0x66, 0x1d, 0x0b, 0xd2, 0xaf, 0xfa, 0xd2, 0x41, 
+        0xa0, 0x05, 0x85, 0x0d, 0x0d, 0x20, 0xee, 0x80, 0x66, 0x1d, 0x0b, 0xd2, 0xaf, 0xfa, 0xd2, 0x41, 
         0x00, 0xd2, 0x41, 0x02, 0xc6, 0x08, 0x00, 0x32, 0xcd, 0xfe, 0x56, 0x93, 0x0b, 0x01, 0xd9, 0xff, 
         0x32, 0x00, 0x7f, 0x32, 0x41, 0x00, 0x22, 0x00, 0x80, 0x22, 0x41, 0x01, 0x02, 0x00, 0x81, 0x02, 
         0x41, 0x02, 0xd2, 0x01, 0x01, 0x80, 0xdd, 0x01, 0xd0, 0xd8, 0x31, 0xe6, 0x7c, 0x2c, 0x32, 0x01, 
         0x00, 0x22, 0xcc, 0xff, 0x80, 0x33, 0x01, 0x30, 0x38, 0x31, 0x80, 0x33, 0x01, 0x30, 0x38, 0x31, 
-        0x30, 0x3d, 0xc0, 0x30, 0x22, 0x82, 0x32, 0xa0, 0x05, 0x85, 0x06, 0x0d, 0x02, 0x01, 0x00, 0x80, 
+        0x30, 0x3d, 0xc0, 0x30, 0x22, 0x82, 0x32, 0xa0, 0x05, 0x05, 0x08, 0x0d, 0x02, 0x01, 0x00, 0x80, 
         0x00, 0x01, 0x00, 0x08, 0x31, 0x20, 0x00, 0x80, 0x06, 0x08, 0x00, 0x02, 0x01, 0x02, 0x22, 0xa0, 
         0x0d, 0x80, 0x00, 0x01, 0x00, 0x08, 0x31, 0xd0, 0x00, 0xc0, 0xc7, 0x22, 0x74, 0x32, 0xa0, 0x05, 
-        0x22, 0xcc, 0xfa, 0x20, 0x20, 0x82, 0xc5, 0x03, 0x0d, 0xd0, 0x02, 0x80, 0xa1, 0xbf, 0xff, 0x0a, 
+        0x22, 0xcc, 0xfa, 0x20, 0x20, 0x82, 0x45, 0x05, 0x0d, 0xd0, 0x02, 0x80, 0xa1, 0xbf, 0xff, 0x0a, 
         0x9e, 0x41, 0x43, 0xfd, 0x90, 0x90, 0x74, 0x60, 0x99, 0x11, 0xc0, 0x20, 0x00, 0x82, 0x24, 0xda, 
         0xa0, 0x88, 0x10, 0x90, 0x88, 0x20, 0xc0, 0x20, 0x00, 0x82, 0x64, 0xda, 0x0c, 0x17, 0xc0, 0x20, 
         0x00, 0x68, 0xd4, 0x70, 0x66, 0x20, 0xc0, 0x20, 0x00, 0x69, 0xd4, 0x7c, 0xe5, 0xc0, 0x20, 0x00, 
         0x38, 0xd4, 0x50, 0x33, 0x10, 0xc0, 0x20, 0x00, 0x39, 0xd4, 0xc8, 0x31, 0xd8, 0x41, 0xe8, 0x51, 
         0x08, 0x21, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0xa2, 0xcd, 0xfd, 0x56, 0x4a, 0xf5, 0x01, 0xa9, 0xff, 
         0x32, 0x00, 0x82, 0x32, 0x41, 0x00, 0x22, 0x00, 0x83, 0x22, 0x41, 0x01, 0x02, 0x00, 0x84, 0x06, 
-        0xcf, 0xff, 0x0c, 0x53, 0x22, 0xcc, 0xfe, 0x20, 0x20, 0x82, 0x85, 0xfc, 0x0c, 0x06, 0xe2, 0xff, 
-        0x00, 0x00, 0x00, 0x22, 0xcc, 0xfe, 0x20, 0x23, 0x82, 0x0c, 0x53, 0x85, 0xfb, 0x0c, 0xc6, 0xbc, 
+        0xcf, 0xff, 0x0c, 0x53, 0x22, 0xcc, 0xfe, 0x20, 0x20, 0x82, 0x05, 0xfe, 0x0c, 0x06, 0xe2, 0xff, 
+        0x00, 0x00, 0x00, 0x22, 0xcc, 0xfe, 0x20, 0x23, 0x82, 0x0c, 0x53, 0x05, 0xfd, 0x0c, 0xc6, 0xbc, 
         0xff, 0x00, 0x00, 0x00, 0xcc, 0x2e, 0x00, 0x40, 0x12, 0xc1, 0xf0, 0x02, 0x61, 0x03, 0x01, 0x21, 
         0xfd, 0x08, 0x20, 0x29, 0x21, 0x27, 0x70, 0x0f, 0x31, 0x1f, 0xfd, 0x20, 0x22, 0x90, 0x32, 0xc3, 
         0x25, 0x3a, 0x22, 0x85, 0x4e, 0x03, 0x28, 0x21, 0x41, 0xa7, 0xf9, 0xc0, 0x20, 0x00, 0x42, 0x24, 
@@ -579,26 +579,26 @@ static u8 eagle_fw2[] =
         0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x12, 0xc1, 0xb0, 0xe9, 0xd1, 0xf9, 0xe1, 0x29, 
         0x71, 0xd9, 0xc1, 0xc9, 0xb1, 0xc1, 0xf3, 0xff, 0x09, 0xa1, 0x02, 0x0c, 0x5f, 0xdd, 0x03, 0xcc, 
         0x30, 0x2c, 0x8e, 0xc6, 0x04, 0x00, 0x66, 0x10, 0x04, 0x1c, 0xae, 0xc6, 0x02, 0x00, 0x32, 0xc0, 
-        0xfe, 0x22, 0xa0, 0x18, 0xe2, 0xa0, 0x28, 0x30, 0xe2, 0x83, 0x2d, 0x0d, 0x3d, 0x0e, 0xc5, 0xf5, 
-        0x0c, 0xe6, 0x92, 0x17, 0x2d, 0x0d, 0x3d, 0x0e, 0x85, 0xee, 0x0c, 0x20, 0x0e, 0x82, 0xd0, 0x00, 
+        0xfe, 0x22, 0xa0, 0x18, 0xe2, 0xa0, 0x28, 0x30, 0xe2, 0x83, 0x2d, 0x0d, 0x3d, 0x0e, 0x45, 0xf7, 
+        0x0c, 0xe6, 0x92, 0x17, 0x2d, 0x0d, 0x3d, 0x0e, 0x05, 0xf0, 0x0c, 0x20, 0x0e, 0x82, 0xd0, 0x00, 
         0xc0, 0x00, 0x00, 0xa0, 0xf0, 0x20, 0x11, 0x29, 0x61, 0xc6, 0x08, 0x00, 0x20, 0x4e, 0xc0, 0xe6, 
-        0x94, 0x17, 0xd0, 0x2d, 0x20, 0xe0, 0x3e, 0x20, 0x85, 0xec, 0x0c, 0x02, 0xc2, 0x01, 0x00, 0x0e, 
+        0x94, 0x17, 0xd0, 0x2d, 0x20, 0xe0, 0x3e, 0x20, 0x05, 0xee, 0x0c, 0x02, 0xc2, 0x01, 0x00, 0x0e, 
         0x82, 0xd0, 0x00, 0xc0, 0x00, 0x00, 0xa0, 0x46, 0xf6, 0xff, 0x22, 0xa0, 0x00, 0x22, 0x61, 0x06, 
         0x32, 0x0c, 0x7b, 0x22, 0x0c, 0x9e, 0x16, 0xa3, 0x06, 0x32, 0x61, 0x05, 0xf2, 0x0c, 0x7a, 0x80, 
         0x22, 0x11, 0x2a, 0xff, 0x16, 0xcf, 0x05, 0x2d, 0x03, 0x7c, 0x6e, 0xd0, 0xee, 0x82, 0xd0, 0x22, 
-        0xc1, 0x30, 0x33, 0xa0, 0xf0, 0x33, 0x11, 0x22, 0x61, 0x10, 0x32, 0x61, 0x12, 0x3d, 0x0f, 0xc5, 
-        0xee, 0x0c, 0x02, 0x21, 0x12, 0x42, 0x21, 0x10, 0x07, 0x22, 0x02, 0xc6, 0x48, 0x00, 0x2d, 0x04, 
-        0x3d, 0x0f, 0x05, 0xe7, 0x0c, 0x05, 0xfb, 0x0c, 0x29, 0x21, 0x2d, 0x0f, 0x85, 0xfa, 0x0c, 0xfd, 
-        0x02, 0x28, 0x51, 0xc5, 0xf9, 0x0c, 0x3d, 0x02, 0x2d, 0x0f, 0x85, 0x6e, 0x0c, 0x3d, 0x02, 0x28, 
-        0x21, 0xc5, 0x57, 0x0c, 0xf1, 0xc1, 0xff, 0x38, 0x0f, 0x45, 0x57, 0x0c, 0x05, 0x79, 0x0c, 0x2a, 
+        0xc1, 0x30, 0x33, 0xa0, 0xf0, 0x33, 0x11, 0x22, 0x61, 0x10, 0x32, 0x61, 0x12, 0x3d, 0x0f, 0x45, 
+        0xf0, 0x0c, 0x02, 0x21, 0x12, 0x42, 0x21, 0x10, 0x07, 0x22, 0x02, 0xc6, 0x48, 0x00, 0x2d, 0x04, 
+        0x3d, 0x0f, 0x85, 0xe8, 0x0c, 0x85, 0xfc, 0x0c, 0x29, 0x21, 0x2d, 0x0f, 0x05, 0xfc, 0x0c, 0xfd, 
+        0x02, 0x28, 0x51, 0x45, 0xfb, 0x0c, 0x3d, 0x02, 0x2d, 0x0f, 0x05, 0x70, 0x0c, 0x3d, 0x02, 0x28, 
+        0x21, 0x45, 0x59, 0x0c, 0xf1, 0xc1, 0xff, 0x38, 0x0f, 0xc5, 0x58, 0x0c, 0x85, 0x7a, 0x0c, 0x2a, 
         0xfe, 0x06, 0x02, 0x00, 0xf2, 0xa0, 0x00, 0xe2, 0xaf, 0xf6, 0xd0, 0xee, 0x82, 0x02, 0x0c, 0x9a, 
         0xf2, 0x61, 0x13, 0x16, 0x70, 0x06, 0x02, 0x61, 0x04, 0x22, 0x0c, 0x9f, 0xf2, 0x0c, 0x99, 0x80, 
         0x22, 0x11, 0x2a, 0xff, 0x16, 0x6f, 0x05, 0x3d, 0x0f, 0xd0, 0x20, 0xc1, 0x22, 0x61, 0x11, 0x00, 
-        0xd0, 0xa0, 0xf0, 0xdd, 0x11, 0x45, 0xe7, 0x0c, 0x02, 0x21, 0x11, 0xd7, 0x22, 0x02, 0x46, 0x3c, 
-        0x00, 0x3d, 0x0f, 0x2d, 0x00, 0xc5, 0xdf, 0x0c, 0xc5, 0xf3, 0x0c, 0x29, 0x31, 0xd8, 0x41, 0x2d, 
-        0x0f, 0x45, 0xf3, 0x0c, 0xfd, 0x02, 0x2d, 0x0d, 0x45, 0xf2, 0x0c, 0x3d, 0x02, 0xd8, 0x31, 0x2d, 
-        0x0f, 0x05, 0x67, 0x0c, 0x3d, 0x02, 0x2d, 0x0d, 0x45, 0x50, 0x0c, 0x31, 0xa3, 0xff, 0x38, 0x03, 
-        0xc5, 0x4f, 0x0c, 0xc5, 0x71, 0x0c, 0xf2, 0x21, 0x13, 0x2a, 0x3e, 0x06, 0x01, 0x00, 0xf2, 0x21, 
+        0xd0, 0xa0, 0xf0, 0xdd, 0x11, 0xc5, 0xe8, 0x0c, 0x02, 0x21, 0x11, 0xd7, 0x22, 0x02, 0x46, 0x3c, 
+        0x00, 0x3d, 0x0f, 0x2d, 0x00, 0x45, 0xe1, 0x0c, 0x45, 0xf5, 0x0c, 0x29, 0x31, 0xd8, 0x41, 0x2d, 
+        0x0f, 0xc5, 0xf4, 0x0c, 0xfd, 0x02, 0x2d, 0x0d, 0xc5, 0xf3, 0x0c, 0x3d, 0x02, 0xd8, 0x31, 0x2d, 
+        0x0f, 0x85, 0x68, 0x0c, 0x3d, 0x02, 0x2d, 0x0d, 0xc5, 0x51, 0x0c, 0x31, 0xa3, 0xff, 0x38, 0x03, 
+        0x45, 0x51, 0x0c, 0x45, 0x73, 0x0c, 0xf2, 0x21, 0x13, 0x2a, 0x3e, 0x06, 0x01, 0x00, 0xf2, 0x21, 
         0x13, 0x0c, 0x03, 0x39, 0xf1, 0x21, 0x9d, 0xff, 0xd2, 0x1c, 0x50, 0x01, 0xa6, 0xfc, 0xda, 0xde, 
         0x08, 0x10, 0x2a, 0xdd, 0x08, 0x00, 0x2d, 0x0d, 0xc0, 0x00, 0x00, 0x01, 0x98, 0xff, 0x41, 0xa1, 
         0xfc, 0x0c, 0x03, 0x52, 0xa0, 0x64, 0x57, 0x22, 0x01, 0xdd, 0x03, 0x32, 0x1c, 0x51, 0x28, 0x14, 
@@ -606,27 +606,27 @@ static u8 eagle_fw2[] =
         0x1c, 0x3e, 0x0b, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0xb1, 0x07, 0x64, 0x02, 0x56, 0x6f, 0x11, 
         0x42, 0x1c, 0x4e, 0x00, 0x00, 0x40, 0x40, 0x40, 0xb1, 0x07, 0x64, 0x02, 0x56, 0x93, 0x11, 0x56, 
         0xfd, 0x08, 0x52, 0xa0, 0x64, 0x57, 0x22, 0x01, 0x0c, 0x0e, 0xc8, 0x61, 0xe0, 0xce, 0x93, 0x86, 
-        0x20, 0x00, 0x20, 0x6f, 0xc0, 0x07, 0x26, 0x02, 0x06, 0x3c, 0x00, 0x2d, 0x04, 0x3d, 0x0f, 0x45, 
-        0xd4, 0x0c, 0x1b, 0x22, 0x05, 0xe8, 0x0c, 0x29, 0x01, 0x2d, 0x0f, 0xc5, 0xe7, 0x0c, 0x29, 0x11, 
-        0x28, 0x51, 0xc5, 0xe6, 0x0c, 0x3d, 0x02, 0xf8, 0x01, 0x28, 0x11, 0x85, 0x5b, 0x0c, 0x3d, 0x02, 
-        0x2d, 0x0f, 0xc5, 0x44, 0x0c, 0x31, 0x74, 0xff, 0x38, 0x03, 0x45, 0x44, 0x0c, 0x05, 0x66, 0x0c, 
+        0x20, 0x00, 0x20, 0x6f, 0xc0, 0x07, 0x26, 0x02, 0x06, 0x3c, 0x00, 0x2d, 0x04, 0x3d, 0x0f, 0xc5, 
+        0xd5, 0x0c, 0x1b, 0x22, 0x85, 0xe9, 0x0c, 0x29, 0x01, 0x2d, 0x0f, 0x45, 0xe9, 0x0c, 0x29, 0x11, 
+        0x28, 0x51, 0x45, 0xe8, 0x0c, 0x3d, 0x02, 0xf8, 0x01, 0x28, 0x11, 0x05, 0x5d, 0x0c, 0x3d, 0x02, 
+        0x2d, 0x0f, 0x45, 0x46, 0x0c, 0x31, 0x74, 0xff, 0x38, 0x03, 0xc5, 0x45, 0x0c, 0x85, 0x67, 0x0c, 
         0xc6, 0xb2, 0xff, 0x20, 0x4f, 0xc0, 0xd7, 0x24, 0x02, 0x06, 0x2d, 0x00, 0x3d, 0x0f, 0x2d, 0x00, 
-        0x05, 0xd0, 0x0c, 0x1b, 0x22, 0x05, 0xe4, 0x0c, 0xdd, 0x02, 0x2d, 0x0f, 0x85, 0xe3, 0x0c, 0xfd, 
-        0x02, 0x28, 0x41, 0xc5, 0xe2, 0x0c, 0x3d, 0x02, 0x2d, 0x0f, 0x85, 0x57, 0x0c, 0x3d, 0x02, 0x2d, 
-        0x0d, 0xc5, 0x40, 0x0c, 0x31, 0x65, 0xff, 0x38, 0x03, 0x45, 0x40, 0x0c, 0x05, 0x62, 0x0c, 0xc6, 
-        0xc0, 0xff, 0xd0, 0xcd, 0x20, 0xe1, 0x62, 0xff, 0x0c, 0x0d, 0x2d, 0x0c, 0xc5, 0xe4, 0x0c, 0x29, 
-        0x91, 0x39, 0x81, 0x51, 0x60, 0xff, 0x41, 0x60, 0xff, 0x85, 0x77, 0x0c, 0x5d, 0x0e, 0x4d, 0x0d, 
-        0x45, 0xa1, 0x0c, 0x85, 0xb3, 0x0c, 0x38, 0x81, 0x51, 0x5d, 0xff, 0xfd, 0x02, 0x41, 0x5a, 0xff, 
-        0x28, 0x91, 0x05, 0x76, 0x0c, 0x4d, 0x0d, 0x5d, 0x0e, 0xc5, 0x9f, 0x0c, 0xd1, 0x4a, 0xfe, 0xc5, 
-        0xb1, 0x0c, 0x71, 0x58, 0xff, 0x51, 0x56, 0xff, 0xf0, 0x60, 0x94, 0x50, 0x52, 0x10, 0xc0, 0x66, 
+        0x85, 0xd1, 0x0c, 0x1b, 0x22, 0x85, 0xe5, 0x0c, 0xdd, 0x02, 0x2d, 0x0f, 0x05, 0xe5, 0x0c, 0xfd, 
+        0x02, 0x28, 0x41, 0x45, 0xe4, 0x0c, 0x3d, 0x02, 0x2d, 0x0f, 0x05, 0x59, 0x0c, 0x3d, 0x02, 0x2d, 
+        0x0d, 0x45, 0x42, 0x0c, 0x31, 0x65, 0xff, 0x38, 0x03, 0xc5, 0x41, 0x0c, 0x85, 0x63, 0x0c, 0xc6, 
+        0xc0, 0xff, 0xd0, 0xcd, 0x20, 0xe1, 0x62, 0xff, 0x0c, 0x0d, 0x2d, 0x0c, 0x45, 0xe6, 0x0c, 0x29, 
+        0x91, 0x39, 0x81, 0x51, 0x60, 0xff, 0x41, 0x60, 0xff, 0x05, 0x79, 0x0c, 0x5d, 0x0e, 0x4d, 0x0d, 
+        0xc5, 0xa2, 0x0c, 0x05, 0xb5, 0x0c, 0x38, 0x81, 0x51, 0x5d, 0xff, 0xfd, 0x02, 0x41, 0x5a, 0xff, 
+        0x28, 0x91, 0x85, 0x77, 0x0c, 0x4d, 0x0d, 0x5d, 0x0e, 0x45, 0xa1, 0x0c, 0xd1, 0x4a, 0xfe, 0x45, 
+        0xb3, 0x0c, 0x71, 0x58, 0xff, 0x51, 0x56, 0xff, 0xf0, 0x60, 0x94, 0x50, 0x52, 0x10, 0xc0, 0x66, 
         0x01, 0x2d, 0x0c, 0xc0, 0x20, 0x00, 0x42, 0x2d, 0xa8, 0x70, 0x44, 0x10, 0x60, 0x44, 0x20, 0x50, 
         0x44, 0x20, 0xc0, 0x20, 0x00, 0xc8, 0xb1, 0xe8, 0xd1, 0x42, 0x6d, 0xa8, 0xf8, 0xe1, 0xd8, 0xc1, 
         0x08, 0xa1, 0x12, 0xc1, 0x50, 0x0d, 0xf0, 0xcd, 0x0f, 0x06, 0xe2, 0xff, 0x0c, 0x0f, 0xc6, 0x86, 
         0xff, 0xf2, 0x21, 0x13, 0x0c, 0x03, 0x46, 0xa2, 0xff, 0xcd, 0x03, 0x86, 0xdd, 0xff, 0x00, 0x00, 
         0x12, 0xc1, 0xf0, 0xc9, 0x21, 0x09, 0x11, 0xcc, 0x52, 0x0c, 0x00, 0x0c, 0x0c, 0x86, 0x10, 0x00, 
-        0xe6, 0x12, 0x02, 0xc6, 0x70, 0x00, 0x32, 0xa0, 0x64, 0xb0, 0xc2, 0x11, 0xc0, 0x2c, 0x20, 0x45, 
-        0xc2, 0x0c, 0x0d, 0x02, 0x0c, 0xa3, 0x2d, 0x0c, 0x80, 0xc0, 0x01, 0xc0, 0xc8, 0x31, 0x45, 0xc1, 
-        0x0c, 0x0c, 0xa3, 0x85, 0xc7, 0x0c, 0xa6, 0x22, 0x02, 0x06, 0x73, 0x00, 0x0c, 0x10, 0x46, 0x04, 
+        0xe6, 0x12, 0x02, 0xc6, 0x70, 0x00, 0x32, 0xa0, 0x64, 0xb0, 0xc2, 0x11, 0xc0, 0x2c, 0x20, 0xc5, 
+        0xc3, 0x0c, 0x0d, 0x02, 0x0c, 0xa3, 0x2d, 0x0c, 0x80, 0xc0, 0x01, 0xc0, 0xc8, 0x31, 0xc5, 0xc2, 
+        0x0c, 0x0c, 0xa3, 0x05, 0xc9, 0x0c, 0xa6, 0x22, 0x02, 0x06, 0x73, 0x00, 0x0c, 0x10, 0x46, 0x04, 
         0x00, 0xc2, 0x01, 0x01, 0x02, 0x01, 0x00, 0x80, 0xcc, 0x01, 0x80, 0x00, 0x01, 0x00, 0x08, 0x31, 
         0xc0, 0xc8, 0x31, 0xe6, 0x1c, 0x05, 0x00, 0x41, 0x21, 0xc6, 0x01, 0x00, 0x0b, 0x2c, 0x00, 0x12, 
         0x40, 0x00, 0x40, 0xa1, 0x21, 0x1c, 0xfe, 0xc0, 0x20, 0x00, 0x42, 0x62, 0xb5, 0x62, 0xcc, 0x1e, 
@@ -653,8 +653,8 @@ static u8 eagle_fw2[] =
         0x20, 0x00, 0x52, 0x62, 0xeb, 0xc7, 0xaa, 0x10, 0x97, 0xac, 0x0d, 0x3c, 0xc3, 0x30, 0x3c, 0x90, 
         0x00, 0x13, 0x40, 0x00, 0x00, 0xa1, 0x46, 0x00, 0x00, 0x0c, 0x00, 0xc0, 0x20, 0x00, 0xc8, 0x21, 
         0x02, 0x62, 0xea, 0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0xd6, 0x32, 0xe6, 0x32, 0xa0, 0x64, 
-        0xb0, 0xc2, 0x11, 0xc0, 0x2c, 0x20, 0xc5, 0xa5, 0x0c, 0x0d, 0x02, 0x0c, 0xa3, 0x2d, 0x0c, 0x0b, 
-        0xc0, 0x80, 0xcc, 0x01, 0xc0, 0xc8, 0x31, 0xc5, 0xa4, 0x0c, 0x0c, 0xa3, 0xc5, 0xaa, 0x0c, 0x7c, 
+        0xb0, 0xc2, 0x11, 0xc0, 0x2c, 0x20, 0x45, 0xa7, 0x0c, 0x0d, 0x02, 0x0c, 0xa3, 0x2d, 0x0c, 0x0b, 
+        0xc0, 0x80, 0xcc, 0x01, 0xc0, 0xc8, 0x31, 0x45, 0xa6, 0x0c, 0x0c, 0xa3, 0x45, 0xac, 0x0c, 0x7c, 
         0x83, 0x37, 0xa2, 0x11, 0x0c, 0x10, 0x46, 0x92, 0xff, 0x0c, 0x30, 0xe6, 0x82, 0x02, 0x46, 0x90, 
         0xff, 0x0c, 0x20, 0x06, 0x8f, 0xff, 0x0c, 0x30, 0x7c, 0xe4, 0x47, 0xa2, 0x02, 0x86, 0x8c, 0xff, 
         0x0c, 0x20, 0x46, 0x8b, 0xff, 0x00, 0x00, 0x00, 0x12, 0xc1, 0xf0, 0x09, 0x01, 0x01, 0xe3, 0xf6, 
@@ -1135,7 +1135,7 @@ static u8 eagle_fw2[] =
         0x20, 0x00, 0x62, 0x23, 0xd4, 0x71, 0xf8, 0xfe, 0x60, 0x68, 0x25, 0x56, 0x06, 0x05, 0x72, 0x07, 
         0x04, 0x56, 0xa7, 0x04, 0x32, 0x00, 0x4e, 0x29, 0x51, 0xb6, 0x73, 0x02, 0xc6, 0x23, 0x00, 0x41, 
         0x4e, 0xf5, 0x0b, 0x23, 0x52, 0x94, 0x06, 0x42, 0x94, 0x07, 0x59, 0x41, 0x50, 0x34, 0xc0, 0x30, 
-        0x22, 0x82, 0x0c, 0x53, 0xc5, 0xc3, 0x0a, 0x08, 0x41, 0x2a, 0x00, 0x86, 0x00, 0x00, 0x60, 0x06, 
+        0x22, 0x82, 0x0c, 0x53, 0x45, 0xc5, 0x0a, 0x08, 0x41, 0x2a, 0x00, 0x86, 0x00, 0x00, 0x60, 0x06, 
         0x20, 0x10, 0x21, 0x20, 0x31, 0xe2, 0xff, 0x00, 0x40, 0x11, 0x40, 0x40, 0x31, 0x85, 0x4c, 0xfd, 
         0x2d, 0x01, 0x31, 0x44, 0xf5, 0x41, 0xde, 0xff, 0x58, 0x51, 0x6d, 0x0c, 0x45, 0xba, 0xff, 0x05, 
         0xf0, 0xff, 0x31, 0xe1, 0xfe, 0x0c, 0x02, 0x01, 0x5a, 0xfd, 0x22, 0x43, 0x04, 0x21, 0xe2, 0xfe, 
@@ -1144,10 +1144,10 @@ static u8 eagle_fw2[] =
         0x61, 0x32, 0xf5, 0x32, 0x26, 0x1c, 0x1b, 0x33, 0x32, 0x66, 0x1c, 0x8c, 0x7c, 0x21, 0xcd, 0xff, 
         0x01, 0x14, 0xef, 0xc0, 0x00, 0x00, 0xc8, 0x71, 0x08, 0x61, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0xf6, 
         0xa3, 0x22, 0x41, 0x29, 0xf5, 0x22, 0xc3, 0xfa, 0x52, 0x94, 0x07, 0x42, 0x94, 0x08, 0x52, 0x61, 
-        0x03, 0x50, 0x34, 0xc0, 0x30, 0x22, 0x82, 0x32, 0xa0, 0x05, 0x85, 0xba, 0x0a, 0x02, 0x21, 0x03, 
+        0x03, 0x50, 0x34, 0xc0, 0x30, 0x22, 0x82, 0x32, 0xa0, 0x05, 0x05, 0xbc, 0x0a, 0x02, 0x21, 0x03, 
         0x2a, 0x00, 0xc6, 0xda, 0xff, 0x62, 0x90, 0x09, 0x22, 0xa0, 0x0d, 0x37, 0xb2, 0x02, 0x06, 0xd7, 
         0xff, 0x30, 0x23, 0xa0, 0x31, 0x1d, 0xf5, 0x22, 0xc2, 0xc9, 0x32, 0x93, 0x08, 0x32, 0x61, 0x02, 
-        0x30, 0x36, 0xc0, 0x30, 0x22, 0x82, 0x32, 0xa0, 0x16, 0x85, 0xb7, 0x0a, 0x08, 0x21, 0x2a, 0x00, 
+        0x30, 0x36, 0xc0, 0x30, 0x22, 0x82, 0x32, 0xa0, 0x16, 0x05, 0xb9, 0x0a, 0x08, 0x21, 0x2a, 0x00, 
         0x46, 0xcf, 0xff, 0x00, 0x91, 0x43, 0xee, 0x81, 0x4a, 0xf0, 0x0c, 0x0b, 0x12, 0xc1, 0xf0, 0xc9, 
         0x11, 0x09, 0x01, 0xd9, 0x21, 0x0c, 0x00, 0xd2, 0xa0, 0xff, 0x7c, 0xfc, 0x90, 0x60, 0xa0, 0x20, 
         0x70, 0x90, 0x5d, 0x0d, 0xad, 0x0b, 0xc0, 0x20, 0x00, 0x32, 0xa1, 0x17, 0x62, 0x26, 0xe0, 0x1b, 
@@ -1196,9 +1196,9 @@ static u8 eagle_fw2[] =
         0x0c, 0x03, 0x1c, 0xb4, 0x01, 0x7f, 0xfc, 0x0c, 0x75, 0x08, 0x00, 0x0c, 0x06, 0x02, 0x20, 0x27, 
         0x72, 0xa0, 0xff, 0xc0, 0x00, 0x00, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 
         0x6c, 0x8b, 0xfe, 0x3f, 0x12, 0xc1, 0xf0, 0xc2, 0x61, 0x01, 0x02, 0x61, 0x00, 0x20, 0xc2, 0x20, 
-        0xdc, 0x13, 0x21, 0xfb, 0xff, 0x01, 0x3a, 0xee, 0xc0, 0x00, 0x00, 0x2d, 0x0c, 0x0c, 0x53, 0x85, 
-        0x91, 0x0a, 0xc6, 0x05, 0x00, 0x01, 0x4a, 0xf6, 0x37, 0xb0, 0x0b, 0xc5, 0x90, 0x0a, 0x40, 0x22, 
-        0x11, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x40, 0x22, 0x11, 0xc5, 0x8f, 0x0a, 0xc2, 0x21, 0x01, 
+        0xdc, 0x13, 0x21, 0xfb, 0xff, 0x01, 0x3a, 0xee, 0xc0, 0x00, 0x00, 0x2d, 0x0c, 0x0c, 0x53, 0x05, 
+        0x93, 0x0a, 0xc6, 0x05, 0x00, 0x01, 0x4a, 0xf6, 0x37, 0xb0, 0x0b, 0x45, 0x92, 0x0a, 0x40, 0x22, 
+        0x11, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x40, 0x22, 0x11, 0x45, 0x91, 0x0a, 0xc2, 0x21, 0x01, 
         0x02, 0x21, 0x00, 0x12, 0xc1, 0x10, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x22, 0x82, 0x20, 
         0x2c, 0x41, 0x0d, 0xf0, 0x41, 0x70, 0xed, 0xc0, 0x20, 0x00, 0x32, 0x24, 0x47, 0x3a, 0x32, 0xc0, 
         0x20, 0x00, 0x32, 0x64, 0x41, 0x0d, 0xf0, 0x00, 0x12, 0xc1, 0xf0, 0x39, 0x01, 0x09, 0x11, 0x01, 
@@ -1236,8 +1236,8 @@ static u8 eagle_fw2[] =
         0x6d, 0x5b, 0x01, 0x9c, 0xf5, 0xc0, 0x00, 0x00, 0xc0, 0x20, 0x00, 0x62, 0x2d, 0x5c, 0x96, 0x86, 
         0x00, 0xc0, 0x20, 0x00, 0x72, 0x2d, 0x5c, 0xd6, 0x67, 0xff, 0x31, 0x2f, 0xf7, 0xc0, 0x20, 0x00, 
         0x01, 0x37, 0xfa, 0x22, 0x2d, 0x5c, 0x02, 0x00, 0x01, 0x30, 0x22, 0x10, 0x8c, 0x40, 0x26, 0x10, 
-        0x07, 0x26, 0x20, 0x3f, 0x2c, 0x83, 0x86, 0x00, 0x00, 0x32, 0xa0, 0x1a, 0xc0, 0x22, 0x11, 0x85, 
-        0x69, 0x0a, 0xd2, 0x21, 0x02, 0x16, 0x22, 0x02, 0x08, 0x1c, 0x9c, 0xb0, 0x42, 0xa1, 0xff, 0x27, 
+        0x07, 0x26, 0x20, 0x3f, 0x2c, 0x83, 0x86, 0x00, 0x00, 0x32, 0xa0, 0x1a, 0xc0, 0x22, 0x11, 0x05, 
+        0x6b, 0x0a, 0xd2, 0x21, 0x02, 0x16, 0x22, 0x02, 0x08, 0x1c, 0x9c, 0xb0, 0x42, 0xa1, 0xff, 0x27, 
         0xb0, 0x05, 0x00, 0x32, 0xc0, 0x86, 0x00, 0x00, 0x20, 0x30, 0xc0, 0x37, 0x34, 0x0c, 0x20, 0x32, 
         0xa0, 0x00, 0x20, 0x90, 0x3a, 0x22, 0x20, 0x23, 0x41, 0x29, 0x1c, 0xc8, 0x11, 0x08, 0x01, 0x12, 
         0xc1, 0x10, 0x0d, 0xf0, 0x1c, 0x83, 0x86, 0xf0, 0xff, 0x00, 0x00, 0x00, 0x28, 0xe0, 0x01, 0x00, 
@@ -1396,10 +1396,10 @@ static u8 eagle_fw2[] =
         0x21, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x32, 0xa0, 0x01, 0x42, 0xa0, 0x05, 0x0c, 0x75, 
         0x0c, 0x06, 0x12, 0xc1, 0xe0, 0xd9, 0x21, 0xf9, 0x41, 0xc9, 0x11, 0xe9, 0x31, 0xe1, 0x58, 0xf9, 
         0x09, 0x01, 0x08, 0x0e, 0xcd, 0x02, 0x02, 0x20, 0x25, 0x22, 0xa0, 0x62, 0xc0, 0x00, 0x00, 0x0c, 
-        0x0d, 0xfd, 0x02, 0x32, 0xae, 0xac, 0x20, 0x22, 0x90, 0x30, 0x22, 0xb0, 0x32, 0xa0, 0xe3, 0x45, 
-        0xbe, 0x09, 0x00, 0x52, 0x11, 0x0c, 0xf4, 0x0d, 0x04, 0x50, 0x50, 0x31, 0x2d, 0x0d, 0x50, 0x25, 
+        0x0d, 0xfd, 0x02, 0x32, 0xae, 0xac, 0x20, 0x22, 0x90, 0x30, 0x22, 0xb0, 0x32, 0xa0, 0xe3, 0xc5, 
+        0xbf, 0x09, 0x00, 0x52, 0x11, 0x0c, 0xf4, 0x0d, 0x04, 0x50, 0x50, 0x31, 0x2d, 0x0d, 0x50, 0x25, 
         0xb3, 0xe6, 0xb2, 0x01, 0x0d, 0x02, 0x32, 0xa0, 0xcf, 0xf0, 0x2f, 0x90, 0xf0, 0x22, 0xf0, 0x22, 
-        0xc2, 0x1d, 0x00, 0xf0, 0x11, 0xf0, 0xf0, 0x31, 0x85, 0xbb, 0x09, 0x98, 0x0e, 0x00, 0x42, 0x11, 
+        0xc2, 0x1d, 0x00, 0xf0, 0x11, 0xf0, 0xf0, 0x31, 0x05, 0xbd, 0x09, 0x98, 0x0e, 0x00, 0x42, 0x11, 
         0x0c, 0xf3, 0x0d, 0x03, 0x40, 0x40, 0x31, 0x92, 0x29, 0x27, 0x40, 0xd4, 0xb3, 0xe6, 0xbd, 0x01, 
         0x0d, 0x0d, 0x00, 0xd0, 0x11, 0xd0, 0xd0, 0x31, 0xb6, 0x3c, 0x1c, 0x0c, 0x82, 0xa6, 0x8f, 0x01, 
         0x7c, 0x82, 0x0c, 0x03, 0x0c, 0x44, 0x0c, 0x35, 0x0c, 0x06, 0x2a, 0x7f, 0x70, 0x70, 0x74, 0x22, 
@@ -1441,13 +1441,13 @@ static u8 eagle_fw2[] =
         0x00, 0x00, 0x08, 0x40, 0x00, 0x00, 0x80, 0x44, 0x00, 0x00, 0x00, 0xc2, 0x12, 0xc1, 0xe0, 0xd9, 
         0x31, 0x09, 0x11, 0xc9, 0x21, 0xe9, 0x41, 0xcd, 0x05, 0xe1, 0xf5, 0xff, 0x8c, 0xd3, 0x26, 0x13, 
         0x08, 0x66, 0x23, 0x08, 0xe1, 0xf4, 0xff, 0x86, 0x00, 0x00, 0xe1, 0xf3, 0xff, 0xd1, 0xf3, 0xff, 
-        0x60, 0x22, 0x11, 0x20, 0x24, 0x80, 0xe0, 0x22, 0x11, 0x85, 0xa9, 0x09, 0x51, 0xf1, 0xff, 0x0c, 
-        0x04, 0x45, 0x67, 0x09, 0xc5, 0x7d, 0x09, 0x29, 0x01, 0x31, 0xee, 0xff, 0x2d, 0x0e, 0x05, 0x03, 
-        0x09, 0x3d, 0x02, 0x28, 0x01, 0xc5, 0x18, 0x09, 0x31, 0xec, 0xff, 0x85, 0xdc, 0x08, 0xed, 0x02, 
-        0xc5, 0x27, 0x09, 0x22, 0x4c, 0x00, 0x20, 0x20, 0x74, 0xc5, 0xa2, 0x09, 0x3d, 0x02, 0x2d, 0x0e, 
-        0x85, 0xe9, 0x08, 0x3d, 0x0d, 0x85, 0x00, 0x09, 0xed, 0x02, 0x45, 0x26, 0x09, 0x22, 0x4c, 0x01, 
-        0x20, 0x20, 0x74, 0x45, 0xa1, 0x09, 0x3d, 0x02, 0x2d, 0x0e, 0x05, 0xe8, 0x08, 0x3d, 0x0d, 0x05, 
-        0xff, 0x08, 0xc5, 0x24, 0x09, 0x08, 0x11, 0xd8, 0x31, 0x22, 0x4c, 0x02, 0xe8, 0x41, 0xc8, 0x21, 
+        0x60, 0x22, 0x11, 0x20, 0x24, 0x80, 0xe0, 0x22, 0x11, 0x05, 0xab, 0x09, 0x51, 0xf1, 0xff, 0x0c, 
+        0x04, 0xc5, 0x68, 0x09, 0x45, 0x7f, 0x09, 0x29, 0x01, 0x31, 0xee, 0xff, 0x2d, 0x0e, 0x85, 0x04, 
+        0x09, 0x3d, 0x02, 0x28, 0x01, 0x45, 0x1a, 0x09, 0x31, 0xec, 0xff, 0x05, 0xde, 0x08, 0xed, 0x02, 
+        0x45, 0x29, 0x09, 0x22, 0x4c, 0x00, 0x20, 0x20, 0x74, 0x45, 0xa4, 0x09, 0x3d, 0x02, 0x2d, 0x0e, 
+        0x05, 0xeb, 0x08, 0x3d, 0x0d, 0x05, 0x02, 0x09, 0xed, 0x02, 0xc5, 0x27, 0x09, 0x22, 0x4c, 0x01, 
+        0x20, 0x20, 0x74, 0xc5, 0xa2, 0x09, 0x3d, 0x02, 0x2d, 0x0e, 0x85, 0xe9, 0x08, 0x3d, 0x0d, 0x85, 
+        0x00, 0x09, 0x45, 0x26, 0x09, 0x08, 0x11, 0xd8, 0x31, 0x22, 0x4c, 0x02, 0xe8, 0x41, 0xc8, 0x21, 
         0x12, 0xc1, 0x20, 0x0d, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0xb1, 0x5a, 0x10, 0x40, 
         0xb4, 0x09, 0x00, 0x00, 0x0f, 0x5b, 0x10, 0x40, 0xff, 0xff, 0x0f, 0xff, 0xc8, 0x5b, 0x10, 0x40, 
         0x6c, 0x09, 0x00, 0x00, 0xa8, 0x09, 0x00, 0x00, 0xa3, 0x09, 0x00, 0x00, 0x9e, 0x09, 0x00, 0x00, 
@@ -1647,7 +1647,7 @@ static u8 eagle_fw2[] =
         0x50, 0x44, 0xa0, 0x42, 0x04, 0x11, 0x0c, 0x02, 0x40, 0x23, 0x83, 0x0d, 0xf0, 0x00, 0x00, 0x00, 
         0x5c, 0x89, 0xfe, 0x3f, 0x9c, 0x8b, 0xfe, 0x3f, 0x12, 0xc1, 0xf0, 0x09, 0x11, 0x01, 0xf0, 0xff, 
         0x08, 0x90, 0x29, 0x01, 0xdc, 0x00, 0x21, 0xfa, 0xff, 0x31, 0xfa, 0xff, 0x42, 0xa0, 0xec, 0x01, 
-        0x30, 0xe7, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x30, 0x23, 0x20, 0x32, 0xa0, 0x03, 0x45, 0x66, 
+        0x30, 0xe7, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x30, 0x23, 0x20, 0x32, 0xa0, 0x03, 0xc5, 0x67, 
         0x07, 0xa2, 0x21, 0x00, 0x22, 0x4a, 0x10, 0x7c, 0x09, 0x0c, 0xa8, 0x31, 0xce, 0xe8, 0xc0, 0x20, 
         0x00, 0x72, 0x23, 0xac, 0x90, 0x77, 0x10, 0x80, 0x77, 0x20, 0xc0, 0x20, 0x00, 0x72, 0x63, 0xac, 
         0x61, 0xab, 0xe9, 0xc0, 0x20, 0x00, 0x52, 0x23, 0xb7, 0x60, 0x55, 0x10, 0xc0, 0x20, 0x00, 0x52, 
@@ -1655,7 +1655,7 @@ static u8 eagle_fw2[] =
         0x00, 0x22, 0x63, 0xb7, 0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x12, 0xc1, 0xf0, 0x09, 
         0x01, 0x01, 0xd3, 0xff, 0x08, 0x90, 0x9d, 0x02, 0xdc, 0x00, 0x21, 0xdd, 0xff, 0x31, 0xdd, 0xff, 
         0x42, 0xa0, 0xf7, 0x01, 0x13, 0xe7, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x30, 0x23, 0x20, 0x32, 
-        0x09, 0x10, 0x05, 0x5f, 0x07, 0x41, 0xca, 0xfa, 0x31, 0xb3, 0xe8, 0xc0, 0x20, 0x00, 0x22, 0x23, 
+        0x09, 0x10, 0x85, 0x60, 0x07, 0x41, 0xca, 0xfa, 0x31, 0xb3, 0xe8, 0xc0, 0x20, 0x00, 0x22, 0x23, 
         0xb7, 0x40, 0x22, 0x10, 0xc0, 0x20, 0x00, 0x22, 0x63, 0xb7, 0x02, 0x21, 0x00, 0x12, 0xc1, 0x10, 
         0x80, 0x00, 0x00, 0x00, 0x12, 0xc1, 0xf0, 0x09, 0x01, 0xc5, 0x00, 0x00, 0x08, 0x01, 0x12, 0xc1, 
         0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 0x40, 0x00, 0x81, 0xbe, 0xff, 0x12, 0xc1, 0xd0, 0xf9, 0x81, 
@@ -1673,7 +1673,7 @@ static u8 eagle_fw2[] =
         0x31, 0x02, 0x5c, 0x0b, 0x00, 0x0a, 0xc0, 0x07, 0x29, 0x08, 0x32, 0x5f, 0x01, 0x62, 0x4c, 0x0c, 
         0x86, 0x00, 0x00, 0x02, 0x5f, 0x01, 0x32, 0xa0, 0x00, 0x02, 0x2e, 0x07, 0x52, 0xa0, 0x00, 0x78, 
         0x00, 0x92, 0xa1, 0x00, 0x70, 0x26, 0x41, 0x90, 0x82, 0x10, 0x9c, 0xc5, 0x39, 0xa1, 0x69, 0xb1, 
-        0xe7, 0x67, 0x16, 0x22, 0x00, 0x08, 0x05, 0x1f, 0x05, 0x68, 0xb1, 0x08, 0x7e, 0x38, 0xa1, 0x28, 
+        0xe7, 0x67, 0x16, 0x22, 0x00, 0x08, 0x85, 0x20, 0x05, 0x68, 0xb1, 0x08, 0x7e, 0x38, 0xa1, 0x28, 
         0x00, 0x82, 0xa1, 0x00, 0x20, 0x26, 0x41, 0x80, 0x82, 0x10, 0x42, 0xa4, 0x02, 0x47, 0x82, 0x0b, 
         0x20, 0x56, 0x05, 0x16, 0x35, 0x18, 0x20, 0x73, 0x05, 0x56, 0xd7, 0x17, 0x0c, 0x05, 0x46, 0x02, 
         0x00, 0x20, 0xa3, 0x05, 0x58, 0x91, 0x0c, 0x29, 0xa0, 0x59, 0x93, 0xb1, 0xdb, 0xf7, 0xa8, 0x0e, 
@@ -1706,14 +1706,14 @@ static u8 eagle_fw2[] =
         0xff, 0x0c, 0x03, 0x06, 0xc8, 0xff, 0x0c, 0x08, 0x86, 0xf8, 0xff, 0x42, 0x1c, 0x0c, 0x16, 0xe4, 
         0x05, 0x32, 0x5f, 0x01, 0x08, 0x7e, 0x2d, 0x03, 0x78, 0x00, 0x39, 0x11, 0x07, 0xf7, 0x24, 0x77, 
         0xe7, 0x21, 0x69, 0xb1, 0xc7, 0x77, 0x04, 0x69, 0xb1, 0x97, 0x77, 0x17, 0x32, 0x21, 0x01, 0x22, 
-        0x00, 0x00, 0x42, 0x1c, 0x0c, 0x20, 0x22, 0x34, 0x85, 0xdb, 0x04, 0x62, 0x21, 0x0b, 0x02, 0x2e, 
+        0x00, 0x00, 0x42, 0x1c, 0x0c, 0x20, 0x22, 0x34, 0x05, 0xdd, 0x04, 0x62, 0x21, 0x0b, 0x02, 0x2e, 
         0x07, 0x22, 0x5f, 0x01, 0x48, 0x11, 0x40, 0x40, 0xf4, 0x27, 0xb4, 0x0f, 0x22, 0x5c, 0x0a, 0x58, 
         0x91, 0x62, 0x5c, 0x0b, 0x52, 0x4c, 0x0c, 0x0c, 0x15, 0x86, 0x03, 0x00, 0x62, 0x5c, 0x0a, 0x0c, 
         0x05, 0x86, 0x01, 0x00, 0x62, 0x5c, 0x0a, 0x0c, 0x05, 0x08, 0x7e, 0x0c, 0x13, 0x86, 0x67, 0xff, 
         0x32, 0x61, 0x00, 0x16, 0x99, 0x02, 0x62, 0x61, 0x0b, 0x67, 0xe2, 0x23, 0x22, 0x00, 0x00, 0x20, 
-        0x22, 0x34, 0x05, 0x7a, 0x03, 0x68, 0xb1, 0x38, 0x01, 0x32, 0x5f, 0x01, 0x39, 0x11, 0x16, 0x42, 
+        0x22, 0x34, 0x85, 0x7b, 0x03, 0x68, 0xb1, 0x38, 0x01, 0x32, 0x5f, 0x01, 0x39, 0x11, 0x16, 0x42, 
         0x05, 0x48, 0x72, 0x42, 0x14, 0x05, 0x0c, 0x15, 0x3a, 0x44, 0x42, 0x5f, 0x01, 0x06, 0xf2, 0xff, 
-        0xa7, 0xe2, 0x18, 0x69, 0xb1, 0x17, 0xe2, 0x13, 0x22, 0x00, 0x00, 0x20, 0x22, 0x34, 0x45, 0x77, 
+        0xa7, 0xe2, 0x18, 0x69, 0xb1, 0x17, 0xe2, 0x13, 0x22, 0x00, 0x00, 0x20, 0x22, 0x34, 0xc5, 0x78, 
         0x03, 0x68, 0xb1, 0x81, 0xdf, 0xfe, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x02, 0x08, 0x01, 
         0x02, 0x5f, 0x01, 0x16, 0xd2, 0xf9, 0x48, 0x72, 0x42, 0x14, 0x05, 0x32, 0x18, 0x16, 0x0a, 0x04, 
         0x07, 0x23, 0x90, 0x58, 0x91, 0x02, 0x5f, 0x01, 0x02, 0x5c, 0x0a, 0x62, 0x5c, 0x0b, 0x52, 0x4c, 
@@ -1739,7 +1739,7 @@ static u8 eagle_fw2[] =
         0x24, 0x0c, 0x35, 0x62, 0xa5, 0xe0, 0x45, 0xf6, 0xff, 0x0c, 0x42, 0x0c, 0x23, 0x0c, 0x44, 0x0c, 
         0xa5, 0x0c, 0x06, 0x85, 0xf5, 0xff, 0x0c, 0x72, 0x0c, 0x23, 0x0c, 0x54, 0x0c, 0xa5, 0x0c, 0x06, 
         0x85, 0xf4, 0xff, 0x85, 0xeb, 0xff, 0x4d, 0x02, 0x21, 0x7e, 0xfe, 0x0c, 0x83, 0x32, 0x42, 0x00, 
-        0x42, 0x52, 0x16, 0x0c, 0x13, 0x22, 0x12, 0x0e, 0xc5, 0xda, 0x04, 0x45, 0xf8, 0x05, 0x08, 0x01, 
+        0x42, 0x52, 0x16, 0x0c, 0x13, 0x22, 0x12, 0x0e, 0x45, 0xdc, 0x04, 0xc5, 0xf9, 0x05, 0x08, 0x01, 
         0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 0x32, 0xc2, 0xf6, 0x12, 0xc1, 0xf0, 0x41, 0x74, 
         0xfe, 0x09, 0x11, 0x02, 0x04, 0x00, 0x5d, 0x02, 0x30, 0x50, 0x83, 0x50, 0x00, 0x74, 0xb6, 0x80, 
         0x11, 0x21, 0x7b, 0xfe, 0x31, 0x7c, 0xfe, 0x42, 0xa2, 0x2d, 0x01, 0xb1, 0xe5, 0xc0, 0x00, 0x00, 
@@ -1758,21 +1758,21 @@ static u8 eagle_fw2[] =
         0x58, 0x00, 0x69, 0x0c, 0x50, 0x5c, 0x05, 0x56, 0x85, 0x0e, 0x49, 0x01, 0x72, 0x0c, 0x0b, 0xa2, 
         0x1c, 0x0c, 0xcc, 0x97, 0x82, 0x9c, 0x0a, 0xa6, 0x18, 0x04, 0x0c, 0x19, 0x92, 0x4c, 0x0d, 0x16, 
         0x8a, 0x04, 0xb2, 0x0c, 0x0b, 0x22, 0x0c, 0x0c, 0x8c, 0x0b, 0xcc, 0x32, 0x32, 0x0c, 0x0d, 0xbc, 
-        0x83, 0x22, 0x00, 0x00, 0x20, 0x22, 0x34, 0xc5, 0x4f, 0x03, 0x02, 0x21, 0x00, 0x02, 0x20, 0x07, 
+        0x83, 0x22, 0x00, 0x00, 0x20, 0x22, 0x34, 0x45, 0x51, 0x03, 0x02, 0x21, 0x00, 0x02, 0x20, 0x07, 
         0x16, 0x72, 0x02, 0x48, 0x00, 0x40, 0x56, 0x41, 0x40, 0x30, 0x05, 0x56, 0xd3, 0x0a, 0x40, 0x67, 
         0x04, 0x56, 0x76, 0x0a, 0x71, 0x27, 0xfe, 0x0c, 0x13, 0x29, 0x97, 0x2d, 0x0c, 0x45, 0x98, 0xff, 
         0x2d, 0x0c, 0x32, 0xa0, 0xd4, 0x05, 0x8c, 0xff, 0xc6, 0x21, 0x00, 0x42, 0x20, 0x00, 0xd7, 0x64, 
-        0x26, 0xc7, 0xe4, 0x23, 0x22, 0x00, 0x00, 0x20, 0x22, 0x34, 0x85, 0x4b, 0x03, 0x16, 0x72, 0x01, 
+        0x26, 0xc7, 0xe4, 0x23, 0x22, 0x00, 0x00, 0x20, 0x22, 0x34, 0x05, 0x4d, 0x03, 0x16, 0x72, 0x01, 
         0x31, 0x1c, 0xfe, 0x22, 0x63, 0x09, 0x2d, 0x0c, 0x0c, 0x13, 0x85, 0x95, 0xff, 0x2d, 0x0c, 0x32, 
         0xa0, 0xd4, 0x45, 0x89, 0xff, 0x86, 0x16, 0x00, 0x42, 0x0c, 0x0b, 0x52, 0x0c, 0x0c, 0x8c, 0x04, 
         0xcc, 0x45, 0x62, 0x0c, 0x0d, 0x16, 0xa6, 0x04, 0x22, 0x21, 0x00, 0x22, 0x22, 0x07, 0x22, 0x02, 
-        0x00, 0x20, 0x22, 0x34, 0xc5, 0x47, 0x03, 0x16, 0x82, 0x03, 0x48, 0x01, 0x48, 0x74, 0x48, 0x04, 
+        0x00, 0x20, 0x22, 0x34, 0x45, 0x49, 0x03, 0x16, 0x82, 0x03, 0x48, 0x01, 0x48, 0x74, 0x48, 0x04, 
         0x07, 0xf4, 0x19, 0x77, 0xe4, 0x16, 0x51, 0x0a, 0xfe, 0x0c, 0x13, 0x29, 0x95, 0x2d, 0x0c, 0x45, 
         0x91, 0xff, 0x2d, 0x0c, 0x32, 0xa0, 0xd4, 0x05, 0x85, 0xff, 0x46, 0x05, 0x00, 0x22, 0x6c, 0x00, 
         0x32, 0xa0, 0x00, 0xc0, 0x2c, 0x20, 0xc5, 0x8f, 0xff, 0x22, 0x0c, 0x04, 0x0c, 0x03, 0x0c, 0x04, 
-        0x85, 0xbe, 0x06, 0xc8, 0x21, 0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x57, 0x65, 0x08, 0x62, 
+        0x05, 0xc0, 0x06, 0xc8, 0x21, 0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x57, 0x65, 0x08, 0x62, 
         0x00, 0x04, 0x60, 0x64, 0x41, 0xa6, 0x26, 0xea, 0x22, 0x6c, 0x00, 0x32, 0xa0, 0x00, 0xc0, 0x2c, 
-        0x20, 0x05, 0x8d, 0xff, 0x22, 0x0c, 0x04, 0x0c, 0x03, 0x0c, 0x04, 0x05, 0xbc, 0x06, 0x46, 0xf4, 
+        0x20, 0x05, 0x8d, 0xff, 0x22, 0x0c, 0x04, 0x0c, 0x03, 0x0c, 0x04, 0x85, 0xbd, 0x06, 0x46, 0xf4, 
         0xff, 0x00, 0x00, 0x00, 0x12, 0xc1, 0xf0, 0xc9, 0x11, 0x09, 0x01, 0xcd, 0x03, 0x45, 0x7c, 0xff, 
         0xdc, 0x02, 0x21, 0xfb, 0xfd, 0x31, 0xfb, 0xfd, 0x42, 0xa2, 0x90, 0x01, 0x31, 0xe5, 0xc0, 0x00, 
         0x00, 0x06, 0xff, 0xff, 0x21, 0xeb, 0xfd, 0x08, 0xa2, 0x42, 0x02, 0x00, 0xdc, 0x00, 0x21, 0xf4, 
@@ -1792,7 +1792,7 @@ static u8 eagle_fw2[] =
         0x33, 0x39, 0x8e, 0x08, 0x02, 0xd2, 0x42, 0x0f, 0xd7, 0x60, 0x0c, 0xc7, 0xe0, 0x09, 0x2d, 0x0c, 
         0x0c, 0x03, 0x05, 0xe1, 0x00, 0x06, 0x02, 0x00, 0xf0, 0x3f, 0x20, 0xc0, 0x2c, 0x20, 0x45, 0xe0, 
         0x00, 0x22, 0x2c, 0x07, 0x08, 0x02, 0xd7, 0x60, 0x10, 0xc7, 0xe0, 0x0d, 0x22, 0x02, 0x00, 0x20, 
-        0x22, 0x34, 0x05, 0x32, 0x03, 0xcd, 0x02, 0x56, 0x02, 0xfc, 0xc8, 0x11, 0xd8, 0x21, 0xe8, 0x31, 
+        0x22, 0x34, 0x85, 0x33, 0x03, 0xcd, 0x02, 0x56, 0x02, 0xfc, 0xc8, 0x11, 0xd8, 0x21, 0xe8, 0x31, 
         0xf8, 0x41, 0x08, 0x01, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0x00, 0x00, 0x00, 0x31, 0xa6, 0xfd, 0x20, 
         0x22, 0xb0, 0x30, 0x22, 0xa0, 0x0d, 0xf0, 0x00, 0x5d, 0x04, 0x12, 0xc1, 0xf0, 0x0c, 0x44, 0x09, 
         0x01, 0x05, 0xf8, 0xff, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x6d, 0x02, 0x12, 0xc1, 
@@ -1802,29 +1802,29 @@ static u8 eagle_fw2[] =
         0x11, 0x21, 0x97, 0xfd, 0x31, 0x98, 0xfd, 0x42, 0xa2, 0xda, 0x01, 0xcd, 0xe4, 0xc0, 0x00, 0x00, 
         0x06, 0xff, 0xff, 0x42, 0xa0, 0x00, 0x42, 0x42, 0x11, 0x62, 0x20, 0x07, 0x02, 0x61, 0x00, 0x38, 
         0x06, 0x49, 0x02, 0xb7, 0x73, 0x2a, 0x22, 0x06, 0x00, 0x32, 0x06, 0x04, 0x20, 0x22, 0x34, 0x30, 
-        0x34, 0x41, 0x2b, 0x33, 0x30, 0x30, 0x74, 0x85, 0x98, 0x03, 0x48, 0x01, 0x48, 0x74, 0x2c, 0x02, 
+        0x34, 0x41, 0x2b, 0x33, 0x30, 0x30, 0x74, 0x05, 0x9a, 0x03, 0x48, 0x01, 0x48, 0x74, 0x2c, 0x02, 
         0x42, 0x04, 0x00, 0x0c, 0x63, 0x40, 0x42, 0x34, 0x01, 0xea, 0xff, 0xc0, 0x00, 0x00, 0x46, 0x0d, 
-        0x00, 0x02, 0x21, 0x00, 0xc7, 0x73, 0x0b, 0x32, 0xa0, 0x01, 0x00, 0x20, 0x20, 0x85, 0x87, 0x04, 
+        0x00, 0x02, 0x21, 0x00, 0xc7, 0x73, 0x0b, 0x32, 0xa0, 0x01, 0x00, 0x20, 0x20, 0x05, 0x89, 0x04, 
         0xc6, 0x08, 0x00, 0x71, 0x73, 0xfd, 0x52, 0x06, 0x05, 0x72, 0x07, 0x0d, 0x50, 0x50, 0x54, 0x77, 
         0x35, 0x0b, 0x0c, 0x24, 0x0c, 0x15, 0x3d, 0x00, 0x85, 0xec, 0xff, 0x06, 0x02, 0x00, 0x0c, 0x34, 
         0x0c, 0x15, 0x3d, 0x00, 0xc5, 0xeb, 0xff, 0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 
         0x42, 0x02, 0x0d, 0x0c, 0x05, 0x8c, 0x44, 0x32, 0x42, 0x0b, 0x52, 0x42, 0x0d, 0x0d, 0xf0, 0x00, 
         0x12, 0xc1, 0xf0, 0xc2, 0x61, 0x01, 0x02, 0x61, 0x00, 0x02, 0x02, 0x0b, 0x20, 0xc2, 0x20, 0xac, 
         0xa0, 0x22, 0x02, 0x0c, 0x0c, 0x00, 0x9c, 0x02, 0x28, 0x0c, 0x28, 0x72, 0x22, 0x02, 0x00, 0x20, 
-        0x22, 0x34, 0x05, 0x1b, 0x03, 0x29, 0x0c, 0x46, 0x01, 0x00, 0x00, 0x20, 0x20, 0x22, 0x6c, 0x00, 
+        0x22, 0x34, 0x85, 0x1c, 0x03, 0x29, 0x0c, 0x46, 0x01, 0x00, 0x00, 0x20, 0x20, 0x22, 0x6c, 0x00, 
         0x16, 0xe2, 0x01, 0x2d, 0x0c, 0x0c, 0x03, 0x85, 0x75, 0x00, 0x86, 0x01, 0x00, 0x0c, 0x03, 0x05, 
         0xfb, 0xff, 0x0c, 0x02, 0x0c, 0x93, 0x08, 0x01, 0x32, 0x4c, 0x12, 0xc8, 0x11, 0x12, 0xc1, 0x10, 
         0x0d, 0xf0, 0x0c, 0x02, 0x0c, 0x04, 0x42, 0x4c, 0x0b, 0xc6, 0xf9, 0xff, 0x12, 0xc1, 0xf0, 0xc9, 
         0x11, 0x09, 0x01, 0x02, 0x02, 0x0b, 0xcd, 0x02, 0x8c, 0x60, 0x0c, 0x02, 0x22, 0x4c, 0x0b, 0x46, 
-        0x01, 0x00, 0x32, 0xa0, 0x00, 0x85, 0xf7, 0xff, 0x21, 0x46, 0xfd, 0x22, 0x22, 0x09, 0xc5, 0x1b, 
+        0x01, 0x00, 0x32, 0xa0, 0x00, 0x85, 0xf7, 0xff, 0x21, 0x46, 0xfd, 0x22, 0x22, 0x09, 0x45, 0x1d, 
         0x03, 0x32, 0xa0, 0x0c, 0x08, 0x01, 0x32, 0x4c, 0x12, 0xc8, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 
         0x0c, 0x13, 0x12, 0xc1, 0xf0, 0x09, 0x01, 0xc9, 0x11, 0x01, 0x3d, 0xfd, 0xcd, 0x02, 0x08, 0x90, 
         0x09, 0x02, 0xc5, 0x6e, 0x00, 0x0c, 0xb3, 0x08, 0x01, 0x32, 0x4c, 0x12, 0xc8, 0x11, 0x12, 0xc1, 
         0x10, 0x0d, 0xf0, 0x00, 0x12, 0xc1, 0xf0, 0x02, 0x61, 0x00, 0xc2, 0x61, 0x01, 0xd9, 0x21, 0xcd, 
-        0x03, 0xdd, 0x02, 0x0c, 0x03, 0x32, 0x42, 0x11, 0x45, 0xf2, 0xff, 0x28, 0x5c, 0x45, 0xc3, 0x05, 
-        0xac, 0x02, 0x28, 0x7c, 0x22, 0x02, 0x00, 0x0c, 0x13, 0x20, 0x22, 0x34, 0x05, 0x84, 0x03, 0x48, 
+        0x03, 0xdd, 0x02, 0x0c, 0x03, 0x32, 0x42, 0x11, 0x45, 0xf2, 0xff, 0x28, 0x5c, 0xc5, 0xc4, 0x05, 
+        0xac, 0x02, 0x28, 0x7c, 0x22, 0x02, 0x00, 0x0c, 0x13, 0x20, 0x22, 0x34, 0x85, 0x85, 0x03, 0x48, 
         0x7c, 0x2c, 0x02, 0x42, 0x04, 0x00, 0x0c, 0x63, 0x40, 0x42, 0x34, 0x01, 0x99, 0xff, 0xc0, 0x00, 
-        0x00, 0x06, 0x02, 0x00, 0xc0, 0x2c, 0x20, 0x32, 0xa0, 0x01, 0xc5, 0x7c, 0x04, 0x02, 0x21, 0x00, 
+        0x00, 0x06, 0x02, 0x00, 0xc0, 0x2c, 0x20, 0x32, 0xa0, 0x01, 0x45, 0x7e, 0x04, 0x02, 0x21, 0x00, 
         0x0c, 0x85, 0xc8, 0x11, 0x52, 0x4d, 0x12, 0xd8, 0x21, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 
         0x0c, 0x34, 0x81, 0x60, 0xfd, 0x52, 0xa0, 0x94, 0x12, 0xc1, 0xd0, 0xe9, 0x71, 0x09, 0x41, 0xc9, 
         0x51, 0xf9, 0x81, 0xd9, 0x61, 0x0c, 0x0f, 0xd1, 0x1a, 0xfd, 0xcd, 0x02, 0x02, 0x0c, 0x11, 0x2d, 
@@ -1836,7 +1836,7 @@ static u8 eagle_fw2[] =
         0x50, 0x01, 0x2d, 0x0c, 0x0c, 0x03, 0x0c, 0x34, 0x42, 0x4c, 0x11, 0x45, 0x60, 0x00, 0xed, 0x02, 
         0x0c, 0x50, 0x02, 0x4c, 0x12, 0x86, 0x26, 0x00, 0x16, 0xe6, 0x01, 0x72, 0x20, 0x07, 0x72, 0x27, 
         0x00, 0x2d, 0x0c, 0x70, 0x79, 0x05, 0x70, 0x35, 0x93, 0x05, 0x49, 0xff, 0x82, 0x0c, 0x0e, 0x28, 
-        0x9d, 0x56, 0xe8, 0x0b, 0x45, 0x08, 0x03, 0xc6, 0x2e, 0x00, 0x98, 0x0c, 0xbc, 0x09, 0x21, 0x00, 
+        0x9d, 0x56, 0xe8, 0x0b, 0xc5, 0x09, 0x03, 0xc6, 0x2e, 0x00, 0x98, 0x0c, 0xbc, 0x09, 0x21, 0x00, 
         0xfd, 0x31, 0x00, 0xfd, 0x42, 0xa3, 0xb4, 0x01, 0x36, 0xe4, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 
         0x26, 0x50, 0x02, 0x86, 0x22, 0x00, 0x08, 0xad, 0xf2, 0x4c, 0x11, 0x56, 0x00, 0x0b, 0x21, 0xf8, 
         0xfc, 0x31, 0xf8, 0xfc, 0x42, 0xa3, 0x62, 0x01, 0x2e, 0xe4, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 
@@ -1848,49 +1848,49 @@ static u8 eagle_fw2[] =
         0x8a, 0xe0, 0x9a, 0x83, 0x00, 0xbf, 0x83, 0xb9, 0x9d, 0x92, 0x4d, 0x00, 0x16, 0x68, 0x0d, 0x21, 
         0xdc, 0xfc, 0x31, 0xdc, 0xfc, 0x42, 0xa3, 0xc9, 0x01, 0x12, 0xe4, 0xc0, 0x00, 0x00, 0x06, 0xff, 
         0xff, 0x21, 0xd7, 0xfc, 0x31, 0xd8, 0xfc, 0x42, 0xa3, 0x9b, 0x01, 0x0d, 0xe4, 0xc0, 0x00, 0x00, 
-        0x06, 0xff, 0xff, 0x05, 0x32, 0x04, 0xc0, 0x2c, 0x20, 0x32, 0xa0, 0x00, 0x0c, 0x30, 0xe8, 0xad, 
+        0x06, 0xff, 0xff, 0x85, 0x33, 0x04, 0xc0, 0x2c, 0x20, 0x32, 0xa0, 0x00, 0x0c, 0x30, 0xe8, 0xad, 
         0xe9, 0x0c, 0x02, 0x4c, 0x11, 0x85, 0x50, 0x00, 0xed, 0x02, 0x0c, 0x60, 0x86, 0xc0, 0xff, 0x22, 
         0x2d, 0x09, 0x16, 0x32, 0x05, 0x42, 0x20, 0x07, 0x42, 0x24, 0x00, 0x2d, 0x0c, 0x40, 0x49, 0x05, 
         0x40, 0x35, 0x93, 0x32, 0x4d, 0x2e, 0x3d, 0x0e, 0x45, 0xd4, 0xff, 0x22, 0x0c, 0x04, 0x58, 0x9d, 
-        0x59, 0x0c, 0xc5, 0x7d, 0x06, 0xe2, 0x4c, 0x11, 0xf2, 0x4c, 0x12, 0x2d, 0x0c, 0x38, 0xad, 0x0c, 
+        0x59, 0x0c, 0x45, 0x7f, 0x06, 0xe2, 0x4c, 0x11, 0xf2, 0x4c, 0x12, 0x2d, 0x0c, 0x38, 0xad, 0x0c, 
         0x04, 0x85, 0xc6, 0xff, 0x0c, 0x10, 0x0c, 0x1e, 0x46, 0xda, 0xff, 0x68, 0x9d, 0x09, 0x31, 0x16, 
         0x16, 0x08, 0x09, 0x91, 0x16, 0xa4, 0x1c, 0x21, 0xba, 0xfc, 0x31, 0xba, 0xfc, 0x42, 0xa3, 0x3c, 
         0x01, 0xf0, 0xe3, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x72, 0x2c, 0x00, 0x56, 0x57, 0x04, 0x02, 
         0x20, 0x07, 0x08, 0x00, 0x00, 0x89, 0x05, 0x16, 0xc8, 0x0f, 0x2d, 0x01, 0x2b, 0x31, 0x4b, 0x41, 
-        0x8b, 0x51, 0x05, 0xe3, 0x06, 0x58, 0x21, 0x08, 0xad, 0x48, 0x11, 0x08, 0x70, 0x32, 0x11, 0x01, 
+        0x8b, 0x51, 0x85, 0xe4, 0x06, 0x58, 0x21, 0x08, 0xad, 0x48, 0x11, 0x08, 0x70, 0x32, 0x11, 0x01, 
         0x22, 0x00, 0x00, 0x68, 0x00, 0x20, 0x22, 0x34, 0x60, 0x6b, 0x05, 0x56, 0x16, 0x15, 0x0c, 0x06, 
-        0xc5, 0x60, 0x03, 0x06, 0x56, 0x00, 0xc8, 0x51, 0xd8, 0x61, 0xe8, 0x71, 0xf8, 0x81, 0x08, 0x41, 
+        0x45, 0x62, 0x03, 0x06, 0x56, 0x00, 0xc8, 0x51, 0xd8, 0x61, 0xe8, 0x71, 0xf8, 0x81, 0x08, 0x41, 
         0x12, 0xc1, 0x30, 0x0d, 0xf0, 0x2d, 0x0c, 0x3d, 0x0e, 0x45, 0xcb, 0xff, 0xe2, 0x4c, 0x11, 0x38, 
         0xad, 0x0c, 0x42, 0x0c, 0x04, 0x22, 0x4c, 0x12, 0x2d, 0x0c, 0x05, 0xbe, 0xff, 0x0c, 0x1e, 0x0c, 
         0x00, 0x06, 0xb8, 0xff, 0xdc, 0x74, 0x2d, 0x0c, 0x3d, 0x0f, 0x45, 0xc9, 0xff, 0x32, 0x0c, 0x0b, 
         0x8c, 0x13, 0xf2, 0x4c, 0x0b, 0x0c, 0x0e, 0x0c, 0xa4, 0x42, 0x4c, 0x12, 0x46, 0x05, 0x00, 0xe0, 
         0x3e, 0x20, 0xc0, 0x2c, 0x20, 0x85, 0xc7, 0xff, 0xe2, 0xa0, 0x01, 0x0c, 0xd5, 0x0c, 0x16, 0x62, 
         0x4c, 0x11, 0x52, 0x4c, 0x12, 0x08, 0x31, 0x08, 0x70, 0x48, 0x00, 0xb7, 0x74, 0x2a, 0x22, 0x00, 
-        0x00, 0x32, 0x00, 0x04, 0x20, 0x22, 0x34, 0x30, 0x34, 0x41, 0x2b, 0x33, 0x30, 0x30, 0x74, 0x05, 
-        0x58, 0x03, 0x48, 0x31, 0x48, 0x74, 0x2c, 0x02, 0x42, 0x04, 0x00, 0x0c, 0x63, 0x40, 0x42, 0x34, 
+        0x00, 0x32, 0x00, 0x04, 0x20, 0x22, 0x34, 0x30, 0x34, 0x41, 0x2b, 0x33, 0x30, 0x30, 0x74, 0x85, 
+        0x59, 0x03, 0x48, 0x31, 0x48, 0x74, 0x2c, 0x02, 0x42, 0x04, 0x00, 0x0c, 0x63, 0x40, 0x42, 0x34, 
         0x01, 0xe8, 0xfe, 0xc0, 0x00, 0x00, 0x46, 0xe5, 0xff, 0xc7, 0x74, 0x18, 0x28, 0x31, 0x0c, 0x13, 
-        0x45, 0x47, 0x04, 0x06, 0xe2, 0xff, 0x00, 0x00, 0x00, 0x2d, 0x0c, 0x3d, 0x00, 0x45, 0xce, 0xff, 
+        0xc5, 0x48, 0x04, 0x06, 0xe2, 0xff, 0x00, 0x00, 0x00, 0x2d, 0x0c, 0x3d, 0x00, 0x45, 0xce, 0xff, 
         0x0c, 0x0e, 0x46, 0x97, 0xff, 0x72, 0x0d, 0x0d, 0x92, 0x0c, 0x11, 0x0c, 0x18, 0x42, 0x00, 0x05, 
         0x0c, 0x05, 0x40, 0x60, 0x54, 0x90, 0x58, 0x83, 0x77, 0x36, 0x5a, 0x38, 0x31, 0x2d, 0x0c, 0x0c, 
         0x24, 0x05, 0xab, 0xff, 0xc6, 0xd5, 0xff, 0xc7, 0x70, 0x29, 0xc0, 0x2c, 0x20, 0xf0, 0x3f, 0x20, 
-        0xc5, 0xbe, 0xff, 0x28, 0xad, 0x0c, 0x23, 0x32, 0x4c, 0x12, 0x28, 0x52, 0x45, 0x8f, 0x05, 0x4d, 
-        0x02, 0x28, 0xad, 0x16, 0x64, 0x0c, 0x28, 0x72, 0x22, 0x02, 0x04, 0x20, 0x20, 0x34, 0x85, 0x3f, 
+        0xc5, 0xbe, 0xff, 0x28, 0xad, 0x0c, 0x23, 0x32, 0x4c, 0x12, 0x28, 0x52, 0xc5, 0x90, 0x05, 0x4d, 
+        0x02, 0x28, 0xad, 0x16, 0x64, 0x0c, 0x28, 0x72, 0x22, 0x02, 0x04, 0x20, 0x20, 0x34, 0x05, 0x41, 
         0x03, 0x06, 0x07, 0x00, 0x2d, 0x0c, 0x3d, 0x0f, 0x45, 0xbc, 0xff, 0x32, 0x0c, 0x0b, 0x8c, 0x13, 
         0xf2, 0x4c, 0x0b, 0x2d, 0x0c, 0x0c, 0x34, 0x38, 0xad, 0x42, 0x4c, 0x12, 0x0c, 0x14, 0xc5, 0xae, 
         0xff, 0x0c, 0x0e, 0x06, 0xc2, 0xff, 0x62, 0x00, 0x06, 0x72, 0x0d, 0x0c, 0x80, 0x66, 0x11, 0x40, 
         0x66, 0x20, 0x60, 0x66, 0x54, 0x77, 0x36, 0x0b, 0x38, 0x31, 0x2d, 0x0c, 0x0c, 0x34, 0x45, 0xa4, 
         0xff, 0x86, 0xba, 0xff, 0x38, 0x31, 0x2d, 0x0c, 0x0c, 0x44, 0x85, 0xa3, 0xff, 0x86, 0xb7, 0xff, 
-        0x62, 0x00, 0x04, 0x60, 0x64, 0x41, 0x62, 0xc6, 0x01, 0x60, 0x60, 0x74, 0x05, 0x4b, 0x03, 0x42, 
+        0x62, 0x00, 0x04, 0x60, 0x64, 0x41, 0x62, 0xc6, 0x01, 0x60, 0x60, 0x74, 0x85, 0x4c, 0x03, 0x42, 
         0x2d, 0x0a, 0x42, 0x24, 0x07, 0x2c, 0x02, 0x42, 0x04, 0x00, 0x0c, 0x63, 0x40, 0x42, 0x34, 0x01, 
         0xb0, 0xfe, 0xc0, 0x00, 0x00, 0x2d, 0x0c, 0x0c, 0x03, 0x45, 0xb5, 0xff, 0xe2, 0x4c, 0x12, 0x86, 
         0xe7, 0xff, 0x68, 0x70, 0x2d, 0x0c, 0x68, 0x06, 0xed, 0x00, 0x60, 0x69, 0x05, 0x60, 0x35, 0x93, 
         0x85, 0x18, 0xff, 0x48, 0x7e, 0x48, 0x04, 0xd7, 0x64, 0x18, 0xc7, 0xe4, 0x15, 0x2d, 0x0c, 0xc5, 
         0xb9, 0xff, 0x0c, 0x0e, 0x46, 0xaf, 0xff, 0x49, 0x31, 0x2d, 0x0c, 0x45, 0xb3, 0xff, 0xed, 0x02, 
-        0x46, 0xac, 0xff, 0x2d, 0x0c, 0x85, 0xbb, 0xff, 0xed, 0x02, 0xc6, 0xa9, 0xff, 0x0c, 0x13, 0x85, 
-        0x3e, 0x04, 0xc6, 0xd6, 0xff, 0x00, 0x00, 0x00, 0x12, 0xc1, 0xe0, 0x09, 0x01, 0xf9, 0x41, 0xe9, 
+        0x46, 0xac, 0xff, 0x2d, 0x0c, 0x85, 0xbb, 0xff, 0xed, 0x02, 0xc6, 0xa9, 0xff, 0x0c, 0x13, 0x05, 
+        0x40, 0x04, 0xc6, 0xd6, 0xff, 0x00, 0x00, 0x00, 0x12, 0xc1, 0xe0, 0x09, 0x01, 0xf9, 0x41, 0xe9, 
         0x31, 0xd9, 0x21, 0xc9, 0x11, 0x21, 0x0f, 0xe5, 0xc0, 0x20, 0x00, 0xc2, 0x22, 0xb0, 0x0c, 0x1f, 
-        0xc0, 0xc0, 0xb4, 0x16, 0x7c, 0x04, 0x46, 0x07, 0x00, 0xd0, 0xe0, 0x74, 0xe0, 0x2e, 0x20, 0x05, 
-        0x72, 0x06, 0xe0, 0x2e, 0x20, 0x85, 0x04, 0x00, 0x02, 0xaf, 0xff, 0x00, 0x1d, 0x40, 0x00, 0xef, 
+        0xc0, 0xc0, 0xb4, 0x16, 0x7c, 0x04, 0x46, 0x07, 0x00, 0xd0, 0xe0, 0x74, 0xe0, 0x2e, 0x20, 0x85, 
+        0x73, 0x06, 0xe0, 0x2e, 0x20, 0x85, 0x04, 0x00, 0x02, 0xaf, 0xff, 0x00, 0x1d, 0x40, 0x00, 0xef, 
         0xa1, 0x00, 0xee, 0x30, 0xe0, 0xcc, 0x10, 0xc0, 0xd0, 0x60, 0xc0, 0xdd, 0x10, 0xd0, 0xfd, 0x40, 
         0xd0, 0xd0, 0x60, 0xd2, 0xcd, 0x1f, 0xd6, 0xfd, 0xfc, 0x01, 0x4a, 0xea, 0xc0, 0x20, 0x00, 0xf1, 
         0xfd, 0xe4, 0xe2, 0x2f, 0xb0, 0x00, 0xee, 0x10, 0xc0, 0x20, 0x00, 0xe2, 0x6f, 0xb0, 0xc8, 0x11, 
@@ -1915,7 +1915,7 @@ static u8 eagle_fw2[] =
         0x17, 0x48, 0x02, 0xc7, 0xf4, 0x12, 0x70, 0x50, 0x34, 0x1b, 0x63, 0x60, 0x60, 0x34, 0xc0, 0x66, 
         0x11, 0x60, 0x55, 0x20, 0x52, 0x42, 0x04, 0x28, 0x7d, 0x32, 0x0c, 0x11, 0x26, 0x23, 0x14, 0x26, 
         0x13, 0x11, 0x21, 0xcb, 0xfb, 0x31, 0xcb, 0xfb, 0x42, 0xa4, 0x1a, 0x01, 0x01, 0xe3, 0xc0, 0x00, 
-        0x00, 0x06, 0xff, 0xff, 0x45, 0x46, 0x05, 0x01, 0xba, 0xfb, 0x20, 0x72, 0x20, 0x22, 0x2d, 0x07, 
+        0x00, 0x06, 0xff, 0xff, 0xc5, 0x47, 0x05, 0x01, 0xba, 0xfb, 0x20, 0x72, 0x20, 0x22, 0x2d, 0x07, 
         0x56, 0x87, 0x01, 0x82, 0x02, 0x05, 0x92, 0x00, 0x0d, 0x80, 0x80, 0x54, 0x97, 0xb8, 0x0c, 0x2d, 
         0x0d, 0xc5, 0xf1, 0xff, 0x01, 0xb3, 0xfb, 0x16, 0xe2, 0x05, 0x28, 0x7d, 0x98, 0x02, 0xa1, 0xc5, 
         0xff, 0x90, 0x96, 0x41, 0xa7, 0xc9, 0x2c, 0xb2, 0x1d, 0x08, 0x32, 0x02, 0x04, 0xa2, 0x10, 0x07, 
@@ -1931,18 +1931,18 @@ static u8 eagle_fw2[] =
         0x40, 0x01, 0x2d, 0x0c, 0x0c, 0x13, 0x85, 0x99, 0xff, 0x06, 0xdf, 0xff, 0xc0, 0x2c, 0x20, 0x32, 
         0xa0, 0x00, 0x52, 0xa0, 0x04, 0x52, 0x4c, 0x11, 0x45, 0x00, 0x00, 0x86, 0xda, 0xff, 0x00, 0x00, 
         0x12, 0xc1, 0xf0, 0xc2, 0x61, 0x02, 0x02, 0x61, 0x01, 0x02, 0x02, 0x0e, 0xcd, 0x02, 0xec, 0x70, 
-        0x02, 0x02, 0x0b, 0x16, 0xb3, 0x03, 0x16, 0x80, 0x08, 0x22, 0x02, 0x04, 0x05, 0x2e, 0x06, 0x0c, 
-        0x03, 0x0c, 0x12, 0x0c, 0x04, 0x22, 0x4c, 0x11, 0x22, 0x0c, 0x04, 0x05, 0x1c, 0x06, 0x0c, 0x12, 
+        0x02, 0x02, 0x0b, 0x16, 0xb3, 0x03, 0x16, 0x80, 0x08, 0x22, 0x02, 0x04, 0x85, 0x2f, 0x06, 0x0c, 
+        0x03, 0x0c, 0x12, 0x0c, 0x04, 0x22, 0x4c, 0x11, 0x22, 0x0c, 0x04, 0x85, 0x1d, 0x06, 0x0c, 0x12, 
         0xc8, 0x21, 0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x32, 0xa0, 0x00, 0x32, 0x42, 0x0e, 0x22, 
-        0x22, 0x00, 0x05, 0xdc, 0x03, 0x22, 0xa0, 0x00, 0x0c, 0x04, 0x49, 0x0c, 0x42, 0x4c, 0x11, 0x46, 
+        0x22, 0x00, 0x85, 0xdd, 0x03, 0x22, 0xa0, 0x00, 0x0c, 0x04, 0x49, 0x0c, 0x42, 0x4c, 0x11, 0x46, 
         0xf7, 0xff, 0x16, 0x10, 0x06, 0x22, 0x22, 0x00, 0x32, 0x22, 0x07, 0x28, 0x52, 0x42, 0x13, 0x03, 
-        0x52, 0x03, 0x08, 0x59, 0x01, 0x40, 0x47, 0x41, 0x42, 0x5c, 0x0b, 0x85, 0xe2, 0x04, 0x28, 0x0c, 
-        0x08, 0x72, 0x78, 0x01, 0x62, 0x00, 0x08, 0x77, 0x16, 0x06, 0x45, 0xfc, 0x03, 0x08, 0x0c, 0x08, 
+        0x52, 0x03, 0x08, 0x59, 0x01, 0x40, 0x47, 0x41, 0x42, 0x5c, 0x0b, 0x05, 0xe4, 0x04, 0x28, 0x0c, 
+        0x08, 0x72, 0x78, 0x01, 0x62, 0x00, 0x08, 0x77, 0x16, 0x06, 0xc5, 0xfd, 0x03, 0x08, 0x0c, 0x08, 
         0x70, 0x22, 0x9c, 0x0b, 0x42, 0x10, 0x03, 0x32, 0x10, 0x05, 0x40, 0x47, 0x41, 0x40, 0x33, 0xc0, 
         0x30, 0x22, 0x80, 0x22, 0x5c, 0x0b, 0xc0, 0x2c, 0x20, 0x85, 0x48, 0x00, 0x22, 0xa0, 0x01, 0x46, 
         0xe3, 0xff, 0x32, 0xa0, 0x00, 0x85, 0x7b, 0xff, 0x22, 0x2c, 0x00, 0x32, 0x0c, 0x04, 0x05, 0x33, 
         0x00, 0x22, 0xa0, 0x00, 0x06, 0xde, 0xff, 0x32, 0xa0, 0x00, 0x45, 0x7a, 0xff, 0x32, 0x2c, 0x00, 
-        0x28, 0x53, 0x38, 0x73, 0xc5, 0xdc, 0x04, 0x28, 0x0c, 0x32, 0x0c, 0x04, 0x05, 0x31, 0x00, 0x0c, 
+        0x28, 0x53, 0x38, 0x73, 0x45, 0xde, 0x04, 0x28, 0x0c, 0x32, 0x0c, 0x04, 0x05, 0x31, 0x00, 0x0c, 
         0x02, 0xc6, 0xd6, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x12, 0xc1, 0xf0, 0x52, 0x02, 0x0a, 0x09, 0x01, 
         0xc9, 0x11, 0xd9, 0x21, 0xd1, 0x47, 0xfb, 0xcd, 0x02, 0x02, 0x0d, 0x0c, 0x2d, 0x05, 0x07, 0xb5, 
         0x0a, 0x1b, 0x25, 0x22, 0x4c, 0x0a, 0x02, 0x0d, 0x0c, 0x20, 0x20, 0x74, 0x07, 0xb2, 0x10, 0x02, 
@@ -1954,7 +1954,7 @@ static u8 eagle_fw2[] =
         0x04, 0x30, 0xb0, 0x34, 0x30, 0x34, 0x41, 0x1b, 0x33, 0x30, 0x30, 0x34, 0xc0, 0x33, 0x11, 0x30, 
         0xbb, 0x20, 0xb2, 0x40, 0x04, 0x02, 0x0c, 0x11, 0x26, 0x20, 0x14, 0x26, 0x10, 0x11, 0x21, 0x30, 
         0xfb, 0x31, 0x30, 0xfb, 0x42, 0xa4, 0x8b, 0x01, 0x66, 0xe2, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 
-        0x22, 0x22, 0x07, 0x85, 0x1f, 0x05, 0x56, 0xe2, 0x01, 0x22, 0x2d, 0x0a, 0x68, 0x72, 0x52, 0x0d, 
+        0x22, 0x22, 0x07, 0x05, 0x21, 0x05, 0x56, 0xe2, 0x01, 0x22, 0x2d, 0x0a, 0x68, 0x72, 0x52, 0x0d, 
         0x0c, 0x42, 0x06, 0x06, 0x62, 0x06, 0x05, 0x80, 0x44, 0x11, 0x60, 0x44, 0x20, 0x40, 0x46, 0x54, 
         0x57, 0xb4, 0x04, 0xc5, 0xca, 0xff, 0xac, 0x62, 0x82, 0x0c, 0x04, 0x0c, 0x69, 0x72, 0x0d, 0x00, 
         0x92, 0x4c, 0x11, 0x87, 0x97, 0x09, 0x2d, 0x0c, 0x0c, 0x03, 0x45, 0x7c, 0xff, 0x06, 0x01, 0x00, 
@@ -2008,127 +2008,127 @@ static u8 eagle_fw2[] =
         0x99, 0x20, 0xa2, 0x06, 0x06, 0xa0, 0xbb, 0x11, 0x80, 0xaa, 0x11, 0x50, 0xaa, 0x20, 0x40, 0xaa, 
         0x10, 0xb0, 0xaa, 0x20, 0xa2, 0x46, 0x05, 0xa0, 0xa8, 0x41, 0xa2, 0x46, 0x06, 0x48, 0x72, 0x99, 
         0x06, 0xb2, 0x04, 0x05, 0x52, 0xa0, 0xc0, 0x50, 0xbb, 0x10, 0xb2, 0x44, 0x05, 0x2d, 0x0c, 0x0c, 
-        0x03, 0x45, 0xa2, 0xfe, 0xb2, 0x0c, 0x06, 0xb2, 0x61, 0x00, 0xc5, 0xa0, 0x06, 0x29, 0x11, 0xc5, 
+        0x03, 0x45, 0xa2, 0xfe, 0xb2, 0x0c, 0x06, 0xb2, 0x61, 0x00, 0x45, 0xa2, 0x06, 0x29, 0x11, 0xc5, 
         0x61, 0xf9, 0x32, 0x0c, 0x05, 0x68, 0x01, 0x1c, 0xf5, 0x48, 0x11, 0x60, 0x55, 0xc0, 0x00, 0x05, 
         0x40, 0x0c, 0x15, 0x40, 0x40, 0xb1, 0x40, 0x41, 0x41, 0x52, 0x4c, 0x11, 0x40, 0x42, 0x82, 0x22, 
-        0x0c, 0x04, 0x40, 0x42, 0xf4, 0x45, 0xcd, 0x05, 0xc8, 0x31, 0x08, 0x21, 0x12, 0xc1, 0x10, 0x0d, 
+        0x0c, 0x04, 0x40, 0x42, 0xf4, 0xc5, 0xce, 0x05, 0xc8, 0x31, 0x08, 0x21, 0x12, 0xc1, 0x10, 0x0d, 
         0xf0, 0x00, 0x00, 0x00, 0x32, 0xa0, 0x00, 0x12, 0xc1, 0xf0, 0xc2, 0x61, 0x01, 0x02, 0x61, 0x00, 
         0xcd, 0x02, 0x45, 0x9d, 0xfe, 0x22, 0x0c, 0x04, 0x0c, 0x03, 0x0c, 0x04, 0x0c, 0x10, 0x02, 0x4c, 
-        0x11, 0x85, 0xca, 0x05, 0xc8, 0x11, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 
+        0x11, 0x05, 0xcc, 0x05, 0xc8, 0x11, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 
         0x94, 0x8d, 0xfe, 0x3f, 0x12, 0xc1, 0xf0, 0x02, 0x61, 0x00, 0xd9, 0x21, 0xc9, 0x11, 0xdd, 0x03, 
-        0xcd, 0x02, 0x85, 0x01, 0x03, 0x38, 0x7c, 0x08, 0x03, 0x97, 0x60, 0x07, 0xc7, 0xf0, 0x04, 0x28, 
-        0x5c, 0xc5, 0x22, 0x04, 0x0c, 0x42, 0xc5, 0x8a, 0x03, 0x16, 0xcd, 0x04, 0x28, 0x7c, 0x22, 0x02, 
+        0xcd, 0x02, 0x05, 0x03, 0x03, 0x38, 0x7c, 0x08, 0x03, 0x97, 0x60, 0x07, 0xc7, 0xf0, 0x04, 0x28, 
+        0x5c, 0x45, 0x24, 0x04, 0x0c, 0x42, 0x45, 0x8c, 0x03, 0x16, 0xcd, 0x04, 0x28, 0x7c, 0x22, 0x02, 
         0x06, 0x01, 0x24, 0xfa, 0x20, 0x24, 0x24, 0x20, 0xd2, 0xb0, 0x00, 0xdd, 0xa0, 0x85, 0x88, 0xfe, 
         0xcc, 0xa2, 0x32, 0x0d, 0x12, 0x21, 0xee, 0xff, 0x01, 0x5e, 0xe1, 0xc0, 0x00, 0x00, 0x28, 0x7c, 
         0x22, 0x02, 0x06, 0x20, 0x24, 0x24, 0x05, 0x87, 0xfe, 0xdc, 0x02, 0x21, 0x21, 0xfa, 0x31, 0x21, 
         0xfa, 0x42, 0xa6, 0x4f, 0x01, 0x57, 0xe1, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x22, 0x2c, 0x07, 
-        0x22, 0x02, 0x06, 0x20, 0x24, 0x24, 0x45, 0xe7, 0x01, 0xc2, 0x21, 0x01, 0xd2, 0x21, 0x02, 0x08, 
-        0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x12, 0xc1, 0xf0, 0x02, 0x61, 0x00, 0xc5, 0x00, 
-        0x03, 0x22, 0xa0, 0x05, 0xc5, 0x83, 0x03, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 
+        0x22, 0x02, 0x06, 0x20, 0x24, 0x24, 0xc5, 0xe8, 0x01, 0xc2, 0x21, 0x01, 0xd2, 0x21, 0x02, 0x08, 
+        0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x12, 0xc1, 0xf0, 0x02, 0x61, 0x00, 0x45, 0x02, 
+        0x03, 0x22, 0xa0, 0x05, 0x45, 0x85, 0x03, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 
         0x60, 0x1d, 0xff, 0x3f, 0x22, 0xa0, 0x6a, 0x12, 0xc1, 0xf0, 0x02, 0x61, 0x00, 0x01, 0x7c, 0xef, 
         0x32, 0xa0, 0x02, 0x02, 0x20, 0x00, 0x0c, 0x84, 0x02, 0x20, 0x26, 0x0c, 0x05, 0xc0, 0x00, 0x00, 
         0x21, 0xf8, 0xff, 0x05, 0xe2, 0xfc, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 
         0x12, 0xc1, 0xf0, 0x22, 0x61, 0x00, 0x21, 0xf2, 0xff, 0x02, 0x61, 0x01, 0x28, 0x12, 0x85, 0xec, 
-        0xfc, 0x01, 0xef, 0xff, 0x02, 0x00, 0x2c, 0x0c, 0x02, 0x07, 0x60, 0x0f, 0x28, 0x01, 0x45, 0xc2, 
-        0xfc, 0x01, 0xeb, 0xff, 0x0c, 0x82, 0x02, 0x00, 0x2c, 0xc6, 0xff, 0xff, 0x17, 0x60, 0x04, 0x1c, 
+        0xfc, 0x01, 0xef, 0xff, 0x02, 0x00, 0x30, 0x0c, 0x02, 0x07, 0x60, 0x0f, 0x28, 0x01, 0x45, 0xc2, 
+        0xfc, 0x01, 0xeb, 0xff, 0x0c, 0x82, 0x02, 0x00, 0x30, 0xc6, 0xff, 0xff, 0x17, 0x60, 0x04, 0x1c, 
         0x03, 0x30, 0x22, 0x20, 0x27, 0x60, 0x04, 0x0c, 0x44, 0x40, 0x22, 0x20, 0x00, 0x33, 0x04, 0x85, 
         0xcd, 0xfc, 0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 0x41, 0xe1, 0xff, 0x20, 
-        0x32, 0x20, 0x12, 0xc1, 0xf0, 0x22, 0xa0, 0x01, 0x09, 0x01, 0x42, 0x04, 0x2c, 0x0c, 0x20, 0x40, 
+        0x32, 0x20, 0x12, 0xc1, 0xf0, 0x22, 0xa0, 0x01, 0x09, 0x01, 0x42, 0x04, 0x30, 0x0c, 0x20, 0x40, 
         0x45, 0x04, 0x40, 0x20, 0x93, 0x05, 0x4b, 0xfd, 0x01, 0xd8, 0xe3, 0xc0, 0x00, 0x00, 0x61, 0x58, 
         0xe0, 0xc0, 0x20, 0x00, 0x52, 0x26, 0x85, 0x0c, 0x17, 0x70, 0x55, 0x20, 0xc0, 0x20, 0x00, 0x52, 
-        0x66, 0x85, 0x22, 0xa0, 0xa0, 0x01, 0x17, 0xe1, 0xc0, 0x00, 0x00, 0x05, 0x5f, 0x01, 0x08, 0x01, 
-        0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 0x61, 0xce, 0xff, 0x22, 0x06, 0x2d, 0x51, 0xb9, 
-        0xe2, 0x27, 0x62, 0x21, 0xc0, 0x20, 0x00, 0x42, 0x06, 0x26, 0x52, 0x25, 0x80, 0x28, 0x56, 0x38, 
-        0xa6, 0x50, 0x22, 0xc0, 0x40, 0x33, 0x82, 0x27, 0x33, 0x0b, 0x88, 0xf6, 0x72, 0x16, 0x12, 0x8a, 
-        0x77, 0x27, 0xb7, 0x01, 0x0d, 0xf0, 0x0c, 0x02, 0x0d, 0xf0, 0x00, 0x00, 0x54, 0x1e, 0xff, 0x3f, 
+        0x66, 0x85, 0x22, 0xa0, 0xa0, 0x01, 0x17, 0xe1, 0xc0, 0x00, 0x00, 0x85, 0x60, 0x01, 0x08, 0x01, 
+        0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x00, 0x00, 0x00, 0x61, 0xce, 0xff, 0x22, 0x06, 0x31, 0x51, 0xb9, 
+        0xe2, 0x27, 0x62, 0x22, 0xc0, 0x20, 0x00, 0x42, 0x06, 0x27, 0x52, 0x25, 0x80, 0x28, 0x56, 0x38, 
+        0xb6, 0x50, 0x22, 0xc0, 0x40, 0x33, 0x82, 0x27, 0x33, 0x0c, 0x82, 0x26, 0x10, 0x72, 0x16, 0x12, 
+        0x8a, 0x77, 0x27, 0xb7, 0x01, 0x0d, 0xf0, 0x0c, 0x02, 0x0d, 0xf0, 0x00, 0x54, 0x1e, 0xff, 0x3f, 
         0x5c, 0x89, 0xfe, 0x3f, 0xc8, 0x8b, 0xfe, 0x3f, 0xd0, 0x8b, 0xfe, 0x3f, 0x12, 0xc1, 0xe0, 0xe9, 
         0x41, 0xc9, 0x21, 0xd9, 0x31, 0x09, 0x11, 0x01, 0xf9, 0xff, 0xdd, 0x02, 0x22, 0x00, 0x00, 0x0c, 
-        0x1c, 0xcc, 0x42, 0xc2, 0x40, 0x00, 0xc5, 0xed, 0xff, 0xe1, 0xb5, 0xff, 0x22, 0x2e, 0x0f, 0x38, 
-        0x1e, 0x20, 0x2d, 0xc0, 0xc5, 0xae, 0xfc, 0x41, 0x9f, 0xe2, 0xc0, 0x20, 0x00, 0x32, 0xa1, 0x2c, 
-        0x42, 0x24, 0x80, 0x49, 0x01, 0x27, 0x33, 0x02, 0xc6, 0x22, 0x00, 0x7c, 0xe7, 0x61, 0x2c, 0xe0, 
-        0xc0, 0x20, 0x00, 0x52, 0x26, 0x85, 0x70, 0x55, 0x10, 0xc0, 0x20, 0x00, 0x52, 0x66, 0x85, 0x5c, 
-        0x02, 0x01, 0xec, 0xe0, 0xc0, 0x00, 0x00, 0x0c, 0x28, 0x92, 0x0e, 0x2c, 0x2d, 0x0c, 0x90, 0x95, 
-        0x04, 0x90, 0x28, 0x93, 0x05, 0x2a, 0xfd, 0xc5, 0xe8, 0xff, 0xc0, 0x20, 0x00, 0x38, 0x1e, 0x51, 
-        0x8d, 0xe2, 0x28, 0x01, 0x52, 0x25, 0x80, 0x48, 0xfe, 0x50, 0x22, 0xc0, 0xda, 0x22, 0x40, 0x22, 
-        0xc0, 0x05, 0xa9, 0xfc, 0xdd, 0x02, 0x01, 0x97, 0xe3, 0xc0, 0x00, 0x00, 0x72, 0xa1, 0xff, 0x61, 
-        0x28, 0xe0, 0xc0, 0x20, 0x00, 0x62, 0x26, 0x6a, 0x22, 0xae, 0xd4, 0x77, 0x96, 0x3a, 0x2a, 0x2d, 
-        0x72, 0xa3, 0xe8, 0x27, 0xb7, 0x32, 0x85, 0xe7, 0xff, 0x32, 0x0e, 0x30, 0x42, 0x0e, 0x2c, 0x26, 
-        0x23, 0x3a, 0x07, 0x64, 0x37, 0x21, 0xce, 0xff, 0x31, 0xcf, 0xff, 0x42, 0xa0, 0xe4, 0x01, 0xd4, 
-        0xe0, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x21, 0xcc, 0xff, 0x01, 0xd1, 0xe0, 0xc0, 0x00, 0x00, 
-        0x01, 0x86, 0xe3, 0xc0, 0x00, 0x00, 0x06, 0x01, 0x00, 0x0c, 0x12, 0x05, 0xe9, 0xff, 0x0c, 0x12, 
-        0xc8, 0x21, 0xd8, 0x31, 0xe8, 0x41, 0x08, 0x11, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0x52, 0xa0, 0x03, 
-        0x52, 0x4e, 0x30, 0xc5, 0xd4, 0xfc, 0x2d, 0x0c, 0x81, 0x0b, 0xe0, 0xc0, 0x20, 0x00, 0x82, 0x28, 
-        0x47, 0x89, 0x7e, 0xc0, 0x20, 0x00, 0x0c, 0x2d, 0x62, 0x0e, 0x2c, 0x71, 0x66, 0xe2, 0x60, 0x65, 
-        0x04, 0x72, 0x27, 0x80, 0x79, 0x8e, 0x60, 0x2d, 0x93, 0x85, 0xdc, 0xfc, 0xb2, 0xa0, 0xef, 0x92, 
-        0x0e, 0x2c, 0x20, 0xa0, 0x04, 0xc0, 0xaa, 0x11, 0xb0, 0x99, 0x10, 0xa0, 0x99, 0x20, 0x92, 0x4e, 
-        0x2c, 0x90, 0x95, 0x04, 0x90, 0xcd, 0x93, 0x2d, 0x0c, 0xc5, 0xe0, 0xfc, 0x0c, 0x02, 0x86, 0xe7, 
-        0xff, 0x00, 0x00, 0x00, 0xf4, 0x1d, 0xff, 0x3f, 0xe0, 0x8b, 0xfe, 0x3f, 0xd4, 0x87, 0x10, 0x40, 
+        0x1c, 0xcc, 0x42, 0xc2, 0x40, 0x00, 0xc5, 0xed, 0xff, 0xe1, 0xb5, 0xff, 0x22, 0x2e, 0x10, 0x32, 
+        0x2e, 0x01, 0x20, 0x2d, 0xc0, 0xc5, 0xae, 0xfc, 0x41, 0x9f, 0xe2, 0xc0, 0x20, 0x00, 0x32, 0xa1, 
+        0x2c, 0x42, 0x24, 0x80, 0x49, 0x01, 0x27, 0x33, 0x02, 0x06, 0x23, 0x00, 0x7c, 0xe7, 0x61, 0x2c, 
+        0xe0, 0xc0, 0x20, 0x00, 0x52, 0x26, 0x85, 0x70, 0x55, 0x10, 0xc0, 0x20, 0x00, 0x52, 0x66, 0x85, 
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+        0x92, 0x08, 0x21, 0x24, 0xff, 0xd1, 0x8e, 0xfe, 0x1c, 0x03, 0x02, 0x0d, 0x33, 0x42, 0xa0, 0xef, 
+        0x40, 0x00, 0x10, 0x30, 0x00, 0x20, 0x02, 0x4d, 0x33, 0x01, 0x21, 0xff, 0xc0, 0x00, 0x00, 0x21, 
+        0xf1, 0xff, 0x42, 0x0d, 0x30, 0x32, 0x0d, 0x34, 0x40, 0x47, 0x41, 0x01, 0xcd, 0xdf, 0xc0, 0x00, 
+        0x00, 0x02, 0x0d, 0x34, 0x56, 0xf0, 0x05, 0x0c, 0x75, 0x52, 0x4d, 0x34, 0x22, 0xa0, 0x00, 0x0c, 
         0x03, 0x01, 0x18, 0xff, 0xc0, 0x00, 0x00, 0x38, 0x01, 0x21, 0xe7, 0xff, 0x42, 0x13, 0x10, 0xc2, 
-        0x4d, 0x27, 0x42, 0x5d, 0x1d, 0x32, 0xc3, 0x1a, 0x0c, 0x64, 0x01, 0x0d, 0xe2, 0xc0, 0x00, 0x00, 
-        0x72, 0x0d, 0x2c, 0x82, 0xa0, 0xfe, 0x80, 0x77, 0x10, 0x0c, 0x18, 0x80, 0x77, 0x20, 0x72, 0x4d, 
-        0x2c, 0x61, 0x60, 0xe1, 0xc0, 0x20, 0x00, 0x22, 0xa0, 0x69, 0x0c, 0x05, 0x62, 0x26, 0x80, 0x69, 
-        0x2d, 0x59, 0x3d, 0x05, 0xd9, 0x00, 0xc5, 0x08, 0x01, 0xc5, 0x0a, 0x01, 0xc8, 0x21, 0xd8, 0x31, 
-        0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x26, 0x60, 0xa1, 0x92, 0x0d, 0x2c, 0x07, 0x69, 0x9b, 
+        0x4d, 0x28, 0x42, 0x5d, 0x1f, 0x32, 0xc3, 0x1a, 0x0c, 0x64, 0x01, 0x0d, 0xe2, 0xc0, 0x00, 0x00, 
+        0x72, 0x0d, 0x30, 0x82, 0xa0, 0xfe, 0x80, 0x77, 0x10, 0x0c, 0x18, 0x80, 0x77, 0x20, 0x72, 0x4d, 
+        0x30, 0x61, 0x60, 0xe1, 0xc0, 0x20, 0x00, 0x22, 0xa0, 0x69, 0x0c, 0x05, 0x62, 0x26, 0x80, 0x69, 
+        0x2d, 0x59, 0x3d, 0x85, 0xda, 0x00, 0x45, 0x0a, 0x01, 0x45, 0x0c, 0x01, 0xc8, 0x21, 0xd8, 0x31, 
+        0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x26, 0x60, 0xa1, 0x92, 0x0d, 0x30, 0x07, 0x69, 0x9b, 
         0x21, 0xa8, 0xfe, 0x31, 0xa8, 0xfe, 0x42, 0xa1, 0xec, 0x01, 0xad, 0xdf, 0xc0, 0x00, 0x00, 0x06, 
-        0xff, 0xff, 0x00, 0x00, 0x31, 0x63, 0xfe, 0x22, 0x53, 0x1d, 0x0d, 0xf0, 0x00, 0xa0, 0x0f, 0x00, 
+        0xff, 0xff, 0x00, 0x00, 0x31, 0x63, 0xfe, 0x22, 0x53, 0x1f, 0x0d, 0xf0, 0x00, 0xa0, 0x0f, 0x00, 
         0x3c, 0x8c, 0xfe, 0x3f, 0x12, 0xc1, 0xd0, 0xc9, 0x51, 0xd9, 0x61, 0xf9, 0x81, 0xe9, 0x71, 0x09, 
         0x41, 0xed, 0x03, 0x30, 0x04, 0xc0, 0xa6, 0xa0, 0x70, 0xf2, 0x13, 0x04, 0xcb, 0x03, 0x60, 0xff, 
         0x11, 0x16, 0x5f, 0x06, 0x31, 0xf6, 0xff, 0xf7, 0x33, 0x5f, 0x29, 0x01, 0x00, 0x34, 0xc0, 0xa6, 
@@ -2136,1868 +2136,1869 @@ static u8 eagle_fw2[] =
         0x08, 0x9c, 0x13, 0x66, 0x53, 0x12, 0x32, 0x00, 0x03, 0xdd, 0x00, 0xbc, 0xb3, 0x62, 0x00, 0x02, 
         0x37, 0x36, 0x05, 0xc6, 0x0c, 0x00, 0x77, 0x38, 0x30, 0x0a, 0x07, 0x2b, 0x00, 0x00, 0x34, 0xc0, 
         0xe6, 0x23, 0xd0, 0x46, 0x00, 0x00, 0x0c, 0x0d, 0x9c, 0xed, 0xc1, 0x45, 0xfe, 0x72, 0xa0, 0xf7, 
-        0x02, 0x0c, 0x2d, 0x22, 0x0c, 0x26, 0x37, 0x60, 0x1f, 0x32, 0x0d, 0x03, 0x37, 0x92, 0x04, 0x48, 
-        0xac, 0xf7, 0x14, 0x3c, 0x70, 0x50, 0x10, 0x52, 0x4c, 0x2d, 0xc8, 0x51, 0xd8, 0x61, 0xe8, 0x71, 
-        0xf8, 0x81, 0x08, 0x41, 0x12, 0xc1, 0x30, 0x0d, 0xf0, 0x27, 0x60, 0x1e, 0x32, 0x0c, 0x26, 0x42, 
-        0x0d, 0x03, 0x30, 0x64, 0xc0, 0x56, 0xf6, 0x11, 0x88, 0xac, 0xf0, 0x88, 0xc0, 0x56, 0x78, 0x11, 
-        0x0c, 0x8a, 0x70, 0x90, 0x10, 0xa0, 0x99, 0x20, 0x92, 0x4c, 0x2d, 0x32, 0x0d, 0x03, 0x02, 0x0c, 
-        0x2d, 0xf9, 0xac, 0x32, 0x4c, 0x26, 0xb2, 0xa0, 0xfb, 0x21, 0xed, 0xfe, 0xb0, 0xb0, 0x10, 0x0c, 
-        0x40, 0x00, 0xbb, 0x20, 0xb2, 0x4c, 0x2d, 0x01, 0xc2, 0xfe, 0xc0, 0x00, 0x00, 0x0c, 0x00, 0xf2, 
-        0x1c, 0x5f, 0x02, 0x5c, 0x5e, 0x1b, 0xff, 0xf2, 0x5c, 0x5f, 0x02, 0x0d, 0x02, 0xf8, 0xac, 0xcc, 
-        0x90, 0x22, 0x0d, 0x03, 0x20, 0x2f, 0x82, 0x29, 0x21, 0x06, 0x01, 0x00, 0xf0, 0x30, 0x82, 0x39, 
-        0x21, 0x28, 0x1e, 0xf0, 0x3a, 0x41, 0x39, 0x11, 0x85, 0xe1, 0x06, 0xa0, 0x22, 0x01, 0x38, 0x11, 
-        0x05, 0xe1, 0x06, 0x3d, 0x0f, 0x60, 0x42, 0x11, 0x49, 0x31, 0x28, 0x0e, 0x45, 0xe0, 0x06, 0x08, 
-        0x21, 0x92, 0xa0, 0xfe, 0x38, 0x31, 0xb8, 0x01, 0x2a, 0x33, 0x4d, 0x03, 0xf7, 0x33, 0x02, 0xf0, 
-        0x43, 0xc0, 0x0c, 0x13, 0xb8, 0x7b, 0x22, 0x1c, 0x1d, 0xb8, 0x1b, 0x20, 0x50, 0xd4, 0x40, 0xbb, 
-        0xc0, 0xb9, 0x6c, 0xba, 0xa0, 0xa9, 0x5c, 0xfa, 0xbb, 0xb9, 0x4c, 0x72, 0x0d, 0x04, 0x82, 0x0d, 
-        0x01, 0x90, 0x07, 0x10, 0x0a, 0x88, 0x70, 0x70, 0x04, 0x72, 0x4c, 0x32, 0x82, 0xc8, 0xfc, 0x80, 
-        0x80, 0x74, 0x9c, 0xd5, 0x20, 0x43, 0xa4, 0x07, 0x34, 0x16, 0x47, 0x38, 0x13, 0x20, 0xf0, 0x24, 
-        0x00, 0xed, 0xc0, 0xea, 0xe4, 0xe2, 0x0e, 0x05, 0x00, 0x0f, 0x40, 0xe0, 0xe0, 0xb1, 0x07, 0xee, 
-        0x01, 0x0c, 0x03, 0x0c, 0x12, 0x30, 0x00, 0x74, 0x02, 0x4c, 0x33, 0xcc, 0x37, 0x0c, 0x0f, 0x00, 
-        0x2f, 0x83, 0x02, 0x0c, 0x30, 0x16, 0x10, 0xef, 0x26, 0x10, 0x38, 0x26, 0x20, 0x4d, 0x32, 0xc0, 
-        0xfd, 0x16, 0x53, 0xee, 0x26, 0x40, 0x63, 0x26, 0x50, 0x6b, 0x42, 0xc0, 0xfa, 0x16, 0x94, 0xed, 
-        0x52, 0xc0, 0xf9, 0x56, 0x35, 0xed, 0x20, 0x60, 0x74, 0x56, 0xd6, 0xec, 0xc5, 0xc6, 0x00, 0x16, 
-        0x72, 0xec, 0x45, 0xee, 0x00, 0x46, 0xb0, 0xff, 0x21, 0x8e, 0xff, 0x01, 0x35, 0xdf, 0xc0, 0x00, 
-        0x00, 0x86, 0xb9, 0xff, 0x20, 0x70, 0x74, 0x16, 0xf7, 0xea, 0x02, 0x0c, 0x2d, 0x47, 0xe0, 0x05, 
-        0x00, 0x80, 0x04, 0x16, 0x38, 0xea, 0xc5, 0xb8, 0xff, 0x46, 0xa7, 0xff, 0x20, 0x90, 0x74, 0x16, 
-        0x79, 0xe9, 0x0c, 0x02, 0x0c, 0x03, 0x01, 0x7b, 0xfe, 0xc0, 0x00, 0x00, 0xa2, 0x0c, 0x2d, 0xa0, 
-        0xa4, 0x04, 0x16, 0x4a, 0xe8, 0xc5, 0xb6, 0xff, 0x86, 0x9f, 0xff, 0x20, 0xb0, 0x74, 0xac, 0x1b, 
-        0x05, 0xb6, 0xff, 0xc6, 0x9c, 0xff, 0x20, 0xd0, 0x74, 0xbc, 0x2d, 0x21, 0x97, 0xfe, 0x01, 0x70, 
-        0xfe, 0xc0, 0x00, 0x00, 0xe2, 0x0c, 0x2d, 0xe0, 0xe4, 0x04, 0x16, 0xce, 0xe5, 0x45, 0xb4, 0xff, 
-        0x86, 0x95, 0xff, 0xf2, 0x0c, 0x2d, 0x47, 0xef, 0x0f, 0x0c, 0x12, 0x05, 0x91, 0x00, 0x0c, 0x10, 
-        0x02, 0x4c, 0x30, 0xc6, 0x90, 0xff, 0x00, 0x00, 0x00, 0x05, 0xa0, 0xff, 0x86, 0x8e, 0xff, 0x22, 
-        0x0c, 0x31, 0x22, 0xc2, 0xf8, 0x56, 0x12, 0xe3, 0x05, 0x9f, 0xff, 0xc6, 0x8a, 0xff, 0x00, 0x00, 
-        0x51, 0xc8, 0xfd, 0x48, 0x35, 0x2a, 0x44, 0x49, 0x35, 0x41, 0xb2, 0xe0, 0xc0, 0x20, 0x00, 0x32, 
-        0x24, 0x80, 0x2a, 0x33, 0xc0, 0x20, 0x00, 0x32, 0x64, 0x80, 0x0d, 0xf0, 0x12, 0xc1, 0xe0, 0x09, 
-        0x21, 0xc9, 0x31, 0xd9, 0x41, 0xcd, 0x02, 0xd1, 0xbe, 0xfd, 0x26, 0x22, 0x10, 0x26, 0x42, 0x05, 
-        0x26, 0x82, 0x7b, 0x66, 0xb2, 0x3d, 0x02, 0x2d, 0x30, 0x1b, 0x00, 0x02, 0x6d, 0x30, 0x32, 0x2d, 
-        0x31, 0x22, 0x0d, 0x2f, 0x1b, 0x33, 0x32, 0x6d, 0x31, 0x47, 0x62, 0x27, 0x21, 0x73, 0xfe, 0x29, 
-        0x11, 0x01, 0x4b, 0xfe, 0xc0, 0x00, 0x00, 0x28, 0x11, 0x52, 0xa0, 0xfe, 0x42, 0x0d, 0x2f, 0x0c, 
-        0xa3, 0x50, 0x44, 0x10, 0x0c, 0x15, 0x50, 0x44, 0x20, 0x42, 0x4d, 0x2f, 0x0c, 0x04, 0x01, 0x6d, 
-        0xfe, 0xc0, 0x00, 0x00, 0x0c, 0x02, 0x45, 0x72, 0xff, 0x62, 0x0d, 0x30, 0xc2, 0x4d, 0x31, 0x26, 
-        0x36, 0x11, 0x21, 0xe7, 0xfd, 0x31, 0xe7, 0xfd, 0x42, 0xa3, 0x0f, 0x01, 0xed, 0xde, 0xc0, 0x00, 
-        0x00, 0x06, 0xff, 0xff, 0x08, 0x21, 0xc8, 0x31, 0x0c, 0x58, 0x92, 0x0d, 0x2f, 0x0c, 0x07, 0x90, 
-        0x94, 0x04, 0x90, 0x78, 0x93, 0x72, 0x4d, 0x30, 0xd8, 0x41, 0x12, 0xc1, 0x20, 0x0d, 0xf0, 0x22, 
-        0xcd, 0x44, 0x22, 0x61, 0x00, 0x01, 0x32, 0xfe, 0xc0, 0x00, 0x00, 0x32, 0xa3, 0xe8, 0x22, 0x2d, 
-        0x10, 0x45, 0xbb, 0x06, 0x20, 0x32, 0x20, 0x42, 0xa0, 0x00, 0x28, 0x01, 0x01, 0x56, 0xfe, 0xc0, 
-        0x00, 0x00, 0x86, 0xe7, 0xff, 0x00, 0x00, 0x00, 0x4c, 0x8c, 0xfe, 0x3f, 0xe0, 0x1d, 0xff, 0x3f, 
-        0x40, 0x42, 0x0f, 0x00, 0x12, 0xc1, 0xf0, 0xc2, 0x61, 0x01, 0xd2, 0x61, 0x02, 0x02, 0x61, 0x00, 
-        0x01, 0x8a, 0xe1, 0xc0, 0x00, 0x00, 0xc1, 0x8a, 0xfd, 0xd1, 0x19, 0xde, 0x32, 0x0c, 0x30, 0x02, 
-        0x0c, 0x2f, 0x66, 0x23, 0x0e, 0x42, 0x0c, 0x2d, 0x47, 0x64, 0x08, 0x52, 0x0c, 0x2c, 0x50, 0x57, 
-        0x41, 0x16, 0xf5, 0x04, 0x47, 0x60, 0x4f, 0x21, 0xf0, 0xff, 0x42, 0x0c, 0x2c, 0x52, 0x0c, 0x2d, 
-        0x40, 0x47, 0x41, 0x50, 0x54, 0x04, 0x01, 0xc6, 0xde, 0xc0, 0x00, 0x00, 0x22, 0x0c, 0x27, 0x05, 
-        0xbd, 0x05, 0x56, 0x32, 0x0e, 0x21, 0x38, 0xfe, 0x0c, 0x26, 0x62, 0x4c, 0x30, 0x01, 0x10, 0xfe, 
-        0xc0, 0x00, 0x00, 0x21, 0x37, 0xfe, 0x01, 0x0e, 0xfe, 0xc0, 0x00, 0x00, 0x82, 0x0c, 0x2c, 0x92, 
-        0xa0, 0xfe, 0x90, 0x88, 0x10, 0x82, 0x4c, 0x2c, 0xc0, 0x20, 0x00, 0x72, 0xa1, 0xff, 0x72, 0x6d, 
-        0x6a, 0x06, 0x33, 0x00, 0x02, 0x0c, 0x2f, 0x66, 0x23, 0x0d, 0xa2, 0x0c, 0x2d, 0x47, 0x6a, 0x07, 
-        0xb2, 0x0c, 0x2c, 0xb0, 0xb7, 0x41, 0x9c, 0x3b, 0x47, 0x60, 0x11, 0x21, 0xa9, 0xfd, 0x31, 0xa9, 
-        0xfd, 0x42, 0xa3, 0x28, 0x01, 0xaf, 0xde, 0xc0, 0x00, 0x00, 0x06, 0xff, 0xff, 0x07, 0xe0, 0x60, 
-        0x17, 0xe0, 0x5d, 0x05, 0x3c, 0xf8, 0x16, 0xb2, 0x00, 0x32, 0x0c, 0x2c, 0x67, 0xe3, 0x05, 0x45, 
-        0xbc, 0x00, 0x16, 0xb2, 0x04, 0x22, 0xa0, 0x01, 0x45, 0x09, 0x01, 0x26, 0x12, 0x42, 0x01, 0x59, 
-        0xe1, 0xc0, 0x00, 0x00, 0xc0, 0x20, 0x00, 0x52, 0x2d, 0x6a, 0x62, 0xa1, 0xff, 0x67, 0x15, 0x6a, 
-        0x72, 0x0c, 0x2c, 0x17, 0x67, 0x5b, 0x45, 0xb9, 0x00, 0x56, 0x52, 0x05, 0x22, 0xa0, 0x14, 0x45, 
-        0x4e, 0xf8, 0xc0, 0x20, 0x00, 0x92, 0xa1, 0xff, 0x92, 0x6d, 0x6a, 0x01, 0x4f, 0xe1, 0xc0, 0x00, 
-        0x00, 0x06, 0x03, 0x00, 0x05, 0x84, 0xff, 0x0c, 0x02, 0x0c, 0x03, 0x01, 0xe6, 0xfd, 0xc0, 0x00, 
-        0x00, 0x01, 0x48, 0xe1, 0xc0, 0x00, 0x00, 0xc1, 0xb9, 0xff, 0x2d, 0x0c, 0x01, 0xe1, 0xfd, 0xc0, 
-        0x00, 0x00, 0x2d, 0x0c, 0x0c, 0x03, 0x0c, 0x04, 0x01, 0x07, 0xfe, 0xc0, 0x00, 0x00, 0xc8, 0x11, 
-        0xd8, 0x21, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x32, 0x0c, 0x30, 0x02, 0x0c, 0x2f, 0x06, 
-        0xd1, 0xff, 0xc0, 0x20, 0x00, 0xa2, 0xa1, 0xff, 0xa2, 0x6d, 0x6a, 0x01, 0x3b, 0xe1, 0xc0, 0x00, 
-        0x00, 0x0c, 0x0d, 0xb2, 0x0c, 0x2c, 0x21, 0xaa, 0xff, 0xb0, 0x00, 0x04, 0x00, 0x2d, 0x93, 0x07, 
-        0x6b, 0x05, 0x45, 0x5a, 0xff, 0x16, 0xb2, 0xf9, 0x05, 0x5e, 0xff, 0x8c, 0x42, 0x85, 0x7d, 0xff, 
-        0xc6, 0xe4, 0xff, 0x21, 0xc0, 0xdd, 0x42, 0x2c, 0x07, 0xc0, 0x20, 0x00, 0x22, 0x22, 0x47, 0x32, 
-        0x2c, 0x01, 0x40, 0x22, 0xc0, 0x45, 0x12, 0xfc, 0x31, 0x1b, 0xe0, 0xc0, 0x20, 0x00, 0x42, 0x2c, 
-        0x08, 0x32, 0x23, 0x80, 0x4a, 0x22, 0x30, 0x22, 0xc0, 0x45, 0xd8, 0xff, 0x42, 0x0c, 0x2c, 0x01, 
-        0xb5, 0xdd, 0x47, 0x64, 0x04, 0x0c, 0x22, 0x06, 0x0c, 0x00, 0xc0, 0x20, 0x00, 0x22, 0x20, 0x4a, 
-        0x07, 0x62, 0x0b, 0xc0, 0x20, 0x00, 0x22, 0x20, 0x46, 0x20, 0x28, 0x54, 0x46, 0x02, 0x00, 0x20, 
-        0x41, 0x04, 0x0c, 0x23, 0x40, 0xd3, 0x93, 0x2d, 0x0d, 0x1c, 0x05, 0x20, 0x82, 0x04, 0x0c, 0x47, 
-        0x80, 0x27, 0x93, 0x0b, 0x62, 0x60, 0x62, 0x10, 0x60, 0x25, 0x93, 0x05, 0xd6, 0xff, 0x46, 0xc9, 
-        0xff, 0x00, 0x00, 0x00, 0x58, 0x8c, 0xfe, 0x3f, 0x12, 0xc1, 0xf0, 0x09, 0x01, 0x01, 0x14, 0xfd, 
-        0x32, 0x00, 0x30, 0x22, 0x00, 0x2f, 0x66, 0x63, 0x10, 0x47, 0x62, 0x1d, 0x0c, 0x73, 0x32, 0x40, 
-        0x30, 0x45, 0xeb, 0x00, 0xc6, 0x02, 0x00, 0x00, 0x00, 0x00, 0x21, 0xf6, 0xff, 0x01, 0x54, 0xde, 
-        0xc0, 0x00, 0x00, 0x08, 0x01, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0x45, 0x83, 0xff, 0x86, 0xfc, 0xff, 
-        0xcc, 0x1d, 0xff, 0x3f, 0x55, 0x1e, 0xff, 0x3f, 0x8c, 0x8c, 0xfe, 0x3f, 0x60, 0x8c, 0xfe, 0x3f, 
-        0xaf, 0x36, 0x00, 0x00, 0x68, 0x8c, 0xfe, 0x3f, 0x12, 0xc1, 0xf0, 0xd2, 0x61, 0x03, 0xc2, 0x61, 
-        0x02, 0x02, 0x61, 0x01, 0xcd, 0x02, 0x21, 0xf6, 0xff, 0x01, 0x95, 0xfd, 0xc0, 0x00, 0x00, 0xd1, 
-        0xfc, 0xfc, 0x32, 0xa0, 0xfe, 0x02, 0x0d, 0x30, 0x22, 0x0d, 0x2d, 0x16, 0xf0, 0x03, 0x30, 0x22, 
-        0x10, 0x42, 0x0d, 0x2c, 0x22, 0x4d, 0x2d, 0x40, 0x40, 0x64, 0x42, 0x4d, 0x2c, 0x38, 0x7c, 0x01, 
-        0xed, 0xff, 0x32, 0x03, 0x0f, 0x0c, 0x0c, 0x26, 0x13, 0x2e, 0x45, 0xc6, 0x05, 0x52, 0x0d, 0x2e, 
-        0x02, 0x0d, 0x2f, 0x66, 0x25, 0x08, 0xc2, 0x4d, 0x2e, 0x85, 0x7a, 0xff, 0x86, 0x03, 0x00, 0x0c, 
-        0x13, 0x47, 0x60, 0x06, 0x29, 0x01, 0x17, 0x60, 0x59, 0xcd, 0x03, 0xc2, 0x4d, 0x2e, 0xc8, 0x21, 
-        0xd8, 0x31, 0x08, 0x11, 0x12, 0xc1, 0x10, 0x0d, 0xf0, 0xc2, 0x40, 0x00, 0x62, 0x0d, 0x2e, 0x1c, 
-        0x08, 0x72, 0xa0, 0xef, 0x70, 0x72, 0x10, 0x80, 0x77, 0x20, 0x72, 0x4d, 0x2d, 0x66, 0x26, 0x08, 
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@@ -4049,102 +4050,102 @@ static u8 eagle_fw2[] =
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-        0x61, 0x64, 0x64, 0x20, 0x6d, 0x69, 0x73, 0x6d, 0x61, 0x74, 0x63, 0x68, 0x0a, 0x00, 0x00, 0x00, 
-        0x61, 0x64, 0x64, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x72, 0x6d, 0x20, 0x6d, 0x69, 0x73, 0x0a, 0x00, 
-        0x77, 0x64, 0x65, 0x76, 0x2e, 0x63, 0x00, 0x00, 0x43, 0x00, 0x00, 0x00, 0xb8, 0x8d, 0xfe, 0x3f, 
-        0xd8, 0xb5, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 
+        0x0a, 0x00, 0x00, 0x00, 0x20, 0x30, 0x78, 0x25, 0x30, 0x38, 0x78, 0x20, 0x00, 0x00, 0x00, 0x00, 
+        0x74, 0x78, 0x20, 0x6e, 0x6f, 0x20, 0x62, 0x75, 0x66, 0x0a, 0x00, 0x00, 0x73, 0x75, 0x6c, 0x20, 
+        0x25, 0x64, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x00, 0x70, 0x70, 0x2e, 0x63, 0x00, 0x00, 0x00, 0x00, 
+        0x79, 0x00, 0x00, 0x00, 0x6d, 0x61, 0x70, 0x20, 0x66, 0x61, 0x69, 0x6c, 0x0a, 0x00, 0x00, 0x00, 
+        0x25, 0x73, 0x3a, 0x20, 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x20, 0x66, 0x72, 0x61, 0x6d, 
+        0x65, 0x00, 0x00, 0x00, 0x72, 0x62, 0x6b, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x74, 0x72, 0x63, 0x2e, 
+        0x63, 0x00, 0x00, 0x00, 0x61, 0x6d, 0x20, 0x6f, 0x6e, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x00, 0x00, 
+        0x66, 0x31, 0x73, 0x25, 0x64, 0x0a, 0x00, 0x00, 0x61, 0x6d, 0x20, 0x6f, 0x66, 0x66, 0x20, 0x25, 
+        0x64, 0x0a, 0x00, 0x00, 0x66, 0x32, 0x73, 0x25, 0x64, 0x0a, 0x00, 0x00, 0x4e, 0x61, 0x6d, 0x0a, 
+        0x00, 0x00, 0x00, 0x00, 0x74, 0x20, 0x25, 0x64, 0x20, 0x73, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x00, 
+        0x47, 0x6f, 0x61, 0x6d, 0x0a, 0x00, 0x00, 0x00, 0x61, 0x64, 0x64, 0x20, 0x6d, 0x69, 0x73, 0x6d, 
+        0x61, 0x74, 0x63, 0x68, 0x0a, 0x00, 0x00, 0x00, 0x61, 0x64, 0x64, 0x20, 0x25, 0x64, 0x0a, 0x00, 
+        0x72, 0x6d, 0x20, 0x6d, 0x69, 0x73, 0x0a, 0x00, 0x77, 0x64, 0x65, 0x76, 0x2e, 0x63, 0x00, 0x00, 
+        0x43, 0x00, 0x00, 0x00, 0xb8, 0x8d, 0xfe, 0x3f, 0xd8, 0xb5, 0xff, 0x3f, 0x00, 0x00, 0x00, 0xd3, 
         
        };
 
- // const static int eagle_fw2_size = 66192;
+ // const static int eagle_fw2_size = 66208;

diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index f20a5fc493110b228054133b852708347ef05d78..b4efe9ae988f4de08df51331ec8e91a0e1a366c6 100755 (executable)
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -71,9 +71,30 @@ config CHARGER_RT5025
        help
          Enable RT5025 Charger driver.
 
+config BATTERY_RT5025
+       bool "RT5025 PMIC ADC Type gauge driver"
+       depends on MFD_RT5025
+       default n
+       help
+         Enable the RT5025 ADC Fuelgauge driver.
+
+config RT_JEITA_REMOVE
+       bool "RT Jeita function remobe"
+       depends on CHARGER_RT5025 && BATTERY_RT5025
+       default n
+       help
+         Say Y here to remove Jeita function.
+
+config CHARGER_RT5036
+       bool "RT5036 charger support"
+       depends on MFD_RT5036
+       default n
+       help
+         Say Y here to enable support for RT5036 chip charger subdevice.
+
 config RT_POWER
-       bool "RT5025 PMIC cable report"
-       depends on CHARGER_RT5025
+       bool "RT PMIC cable report"
+       depends on CHARGER_RT5036 || CHARGER_RT5025
        default n
        help
          Enable AC/USB report.
@@ -86,20 +107,12 @@ config RT_SUPPORT_ACUSB_DUALIN
          Say Y here to enable dualin, otherwise
          N is just singlein.
 
-config BATTERY_RT5025
-       bool "RT5025 PMIC ADC Type gauge driver"
-       depends on MFD_RT5025
-       default n
-       help
-         Enable the RT5025 ADC Fuelgauge driver.
-
-config RT_JEITA_REMOVE
-       bool "RT Jeita function remobe"
-       depends on CHARGER_RT5025 && BATTERY_RT5025
+config RT_BATTERY
+       bool "RT Test Battery"
+       depends on CHARGER_RT5036
        default n
        help
-         Say Y here to remove Jeita function.
-
+         Enable Test Battery report.
 
 config BATTERY_RICOH619
        tristate "Ricoh RC5T619 PMIC battery driver"

diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index b2f1409e0e901ca4435842a6a593c39e72c54e03..e29ceac95b8a55fbe97f7c129b5f37a893715e14 100755 (executable)
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -63,3 +63,5 @@ obj-$(CONFIG_BATTERY_RK818)     += rk818_battery.o
 obj-$(CONFIG_CHARGER_RT5025)   += rt5025-charger.o
 obj-$(CONFIG_RT_POWER)         += rt-power.o
 obj-$(CONFIG_BATTERY_RT5025)   += rt5025-battery.o
+obj-$(CONFIG_CHARGER_RT5036)   += rt5036-charger.o
+obj-$(CONFIG_RT_BATTERY)       += rt-battery.o

diff --git a/drivers/power/rt-battery.c b/drivers/power/rt-battery.c
new file mode 100755 (executable)
index 0000000..93175ad
--- /dev/null
+++ b/drivers/power/rt-battery.c
@@ -0,0 +1,189 @@
+/*
+ *  drivers/power/rt-battery.c
+ *  Driver for Richtek RT Test Battery driver
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/version.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+
+#include <linux/power/rt-battery.h>
+
+struct rt_battery_info {
+       struct device *dev;
+       struct power_supply psy;
+       int chg_status;
+       unsigned char batt_present:1;
+       unsigned char suspend:1;
+};
+
+static enum power_supply_property rt_battery_props[] = {
+       POWER_SUPPLY_PROP_STATUS,
+       POWER_SUPPLY_PROP_HEALTH,
+       POWER_SUPPLY_PROP_PRESENT,
+       POWER_SUPPLY_PROP_ONLINE,
+       POWER_SUPPLY_PROP_CAPACITY,
+       POWER_SUPPLY_PROP_VOLTAGE_NOW,
+};
+
+static int rt_battery_set_property(struct power_supply *psy,
+                                  enum power_supply_property psp,
+                                  const union power_supply_propval *val)
+{
+       struct rt_battery_info *rbi = dev_get_drvdata(psy->dev->parent);
+       int ret = 0;
+
+       switch (psp) {
+       case POWER_SUPPLY_PROP_STATUS:
+               rbi->chg_status = val->intval;
+               break;
+       case POWER_SUPPLY_PROP_PRESENT:
+               rbi->batt_present = val->intval;
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+       case POWER_SUPPLY_PROP_HEALTH:
+       case POWER_SUPPLY_PROP_ONLINE:
+       case POWER_SUPPLY_PROP_CAPACITY:
+       default:
+               ret = -EINVAL;
+               break;
+       }
+       return ret;
+}
+
+static int rt_battery_get_property(struct power_supply *psy,
+                                  enum power_supply_property psp,
+                                  union power_supply_propval *val)
+{
+       struct rt_battery_info *rbi = dev_get_drvdata(psy->dev->parent);
+       int ret = 0;
+
+       switch (psp) {
+       case POWER_SUPPLY_PROP_STATUS:
+               val->intval = rbi->chg_status;
+               break;
+       case POWER_SUPPLY_PROP_HEALTH:
+               val->intval = POWER_SUPPLY_HEALTH_GOOD;
+               break;
+       case POWER_SUPPLY_PROP_PRESENT:
+               val->intval = rbi->batt_present;
+               break;
+       case POWER_SUPPLY_PROP_ONLINE:
+               val->intval = 1;
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+               val->intval = 4000 * 1000;
+               break;
+       case POWER_SUPPLY_PROP_CAPACITY:
+               if (rbi->chg_status == POWER_SUPPLY_STATUS_FULL)
+                       val->intval = 100;
+               else
+                       val->intval = 50;
+               break;
+       default:
+               ret = -EINVAL;
+               break;
+       }
+       return ret;
+}
+
+static int rt_battery_probe(struct platform_device *pdev)
+{
+       struct rt_battery_info *rbi;
+       int ret;
+
+       rbi = devm_kzalloc(&pdev->dev, sizeof(*rbi), GFP_KERNEL);
+       if (!rbi)
+               return -ENOMEM;
+       rbi->dev = &pdev->dev;
+       rbi->chg_status = POWER_SUPPLY_STATUS_DISCHARGING;
+       rbi->batt_present = 1;
+       platform_set_drvdata(pdev, rbi);
+
+       rbi->psy.name = RT_BATT_NAME;
+       rbi->psy.type = POWER_SUPPLY_TYPE_BATTERY;
+       rbi->psy.set_property = rt_battery_set_property;
+       rbi->psy.get_property = rt_battery_get_property;
+       rbi->psy.properties = rt_battery_props;
+       rbi->psy.num_properties = ARRAY_SIZE(rt_battery_props);
+       ret = power_supply_register(&pdev->dev, &rbi->psy);
+       if (ret < 0) {
+               dev_err(&pdev->dev, "battery supply registered fail\n");
+               goto out_dev;
+       }
+       dev_info(&pdev->dev, "driver successfully loaded\n");
+       return 0;
+out_dev:
+       return ret;
+}
+
+static int rt_battery_remove(struct platform_device *pdev)
+{
+       struct rt_battery_info *rbi = platform_get_drvdata(pdev);
+
+       power_supply_unregister(&rbi->psy);
+       return 0;
+}
+
+static int rt_battery_suspend(struct platform_device *pdev, pm_message_t state)
+{
+       struct rt_battery_info *rbi = platform_get_drvdata(pdev);
+
+       rbi->suspend = 1;
+       return 0;
+}
+
+static int rt_battery_resume(struct platform_device *pdev)
+{
+       struct rt_battery_info *rbi = platform_get_drvdata(pdev);
+
+       rbi->suspend = 0;
+       return 0;
+}
+
+static const struct of_device_id rt_match_table[] = {
+       {.compatible = "rt,rt-battery",},
+       {},
+};
+
+static struct platform_driver rt_battery_driver = {
+       .driver = {
+                  .name = "rt-battery",
+                  .owner = THIS_MODULE,
+                  .of_match_table = rt_match_table,
+                  },
+       .probe = rt_battery_probe,
+       .remove = rt_battery_remove,
+       .suspend = rt_battery_suspend,
+       .resume = rt_battery_resume,
+};
+
+static int __init rt_battery_init(void)
+{
+       return platform_driver_register(&rt_battery_driver);
+}
+subsys_initcall(rt_battery_init);
+
+static void __exit rt_battery_exit(void)
+{
+       platform_driver_unregister(&rt_battery_driver);
+}
+module_exit(rt_battery_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("CY Huang <cy_huang@richtek.com>");
+MODULE_DESCRIPTION("RT Test Battery driver");
+MODULE_ALIAS("platform:rt-battery");
+MODULE_VERSION("1.0.0_G");

diff --git a/drivers/power/rt-power.c b/drivers/power/rt-power.c
old mode 100755 (executable)
new mode 100644 (file)
index 22fc92c..055d54e
--- a/drivers/power/rt-power.c
+++ b/drivers/power/rt-power.c
@@ -58,135 +58,164 @@ static int rtpower_set_charger(struct rt_power_info *pi)
 
        chg_psy = power_supply_get_by_name("rt-charger");
        if (chg_psy) {
-               rc = chg_psy->get_property(chg_psy, POWER_SUPPLY_PROP_ONLINE, &pval);
+               rc = chg_psy->get_property(chg_psy, POWER_SUPPLY_PROP_ONLINE,
+                                          &pval);
                if (rc < 0)
                        dev_err(pi->dev, "get chg online prop fail\n");
                else
                        is_chg_on = pval.intval;
                if (pi->ac_online) {
                        pval.intval = pi->acchg_icc;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CURRENT_AVG,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CURRENT_AVG,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set acchg aicr fail\n");
                        pval.intval = 500;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CURRENT_NOW,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CURRENT_NOW,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set acchg icc fail\n");
                        pval.intval = POWER_SUPPLY_TYPE_MAINS;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CHARGE_NOW,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CHARGE_NOW,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set charge cable fail\n");
                        if (!is_chg_on) {
                                pval.intval = pi->chg_volt;
-                               rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_VOLTAGE_NOW,\
+                               rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_VOLTAGE_NOW,
                                        &pval);
                                if (rc < 0)
-                                       dev_err(pi->dev, "set chg voltage fail\n");
+                                       dev_err(pi->dev,
+                                               "set chg voltage fail\n");
                                pval.intval = 1;
-                               rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_ONLINE,\
+                               rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_ONLINE,
                                        &pval);
                                if (rc < 0)
-                                       dev_err(pi->dev, "set charger online fail\n");
+                                       dev_err(pi->dev,
+                                               "set charger online fail\n");
                        }
                        pval.intval = 1;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_PRESENT,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_PRESENT,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set charger present fail\n");
                } else if (pi->usbta_online) {
                        pval.intval = pi->usbtachg_icc;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CURRENT_AVG,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CURRENT_AVG,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set usbtachg aicr fail\n");
                        pval.intval = 500;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CURRENT_NOW,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CURRENT_NOW,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set usbtachg icc fail\n");
                        pval.intval = POWER_SUPPLY_TYPE_USB_DCP;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CHARGE_NOW,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CHARGE_NOW,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set charge cable fail\n");
                        if (!is_chg_on) {
                                pval.intval = pi->chg_volt;
-                               rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_VOLTAGE_NOW,\
-                                       &pval);
+                               rc = chg_psy->set_property(chg_psy,
+                                               POWER_SUPPLY_PROP_VOLTAGE_NOW,
+                                               &pval);
                                if (rc < 0)
-                                       dev_err(pi->dev, "set chg voltage fail\n");
+                                       dev_err(pi->dev,
+                                               "set chg voltage fail\n");
                                pval.intval = 1;
-                               rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_ONLINE,\
-                                       &pval);
+                               rc = chg_psy->set_property(chg_psy,
+                                               POWER_SUPPLY_PROP_ONLINE,
+                                               &pval);
                                if (rc < 0)
-                                       dev_err(pi->dev, "set charger online fail\n");
+                                       dev_err(pi->dev,
+                                               "set charger online fail\n");
                        }
                        pval.intval = 1;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_PRESENT,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                               POWER_SUPPLY_PROP_PRESENT,
+                                               &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set charger present fail\n");
                } else if (pi->usb_online) {
                        pval.intval = pi->usbchg_icc;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CURRENT_AVG,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CURRENT_AVG,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set usbchg aicr fail\n");
                        pval.intval = 500;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CURRENT_NOW,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CURRENT_NOW,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set usbchg icc fail\n");
                        pval.intval = POWER_SUPPLY_TYPE_USB;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CHARGE_NOW,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CHARGE_NOW,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set charge cable fail\n");
                        if (!is_chg_on) {
                                pval.intval = pi->chg_volt;
-                               rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_VOLTAGE_NOW,\
-                                       &pval);
+                               rc = chg_psy->set_property(chg_psy,
+                                               POWER_SUPPLY_PROP_VOLTAGE_NOW,
+                                               &pval);
                                if (rc < 0)
-                                       dev_err(pi->dev, "set chg voltage fail\n");
+                                       dev_err(pi->dev,
+                                               "set chg voltage fail\n");
                                pval.intval = 1;
-                               rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_ONLINE,\
-                                       &pval);
+                               rc = chg_psy->set_property(chg_psy,
+                                               POWER_SUPPLY_PROP_ONLINE,
+                                               &pval);
                                if (rc < 0)
-                                       dev_err(pi->dev, "set charger online fail\n");
+                                       dev_err(pi->dev,
+                                               "set charger online fail\n");
                        }
                        pval.intval = 1;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_PRESENT,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                                  POWER_SUPPLY_PROP_PRESENT,
+                                                  &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set charger present fail\n");
-
                } else {
                        pval.intval = 0;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_ONLINE,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                                  POWER_SUPPLY_PROP_ONLINE,
+                                                  &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set charger online fail\n");
                        pval.intval = 0;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CHARGE_NOW,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                                  POWER_SUPPLY_PROP_CHARGE_NOW,
+                                                  &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set charge cable fail\n");
                        pval.intval = pi->chg_volt;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_VOLTAGE_NOW,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_VOLTAGE_NOW,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set chg voltage fail\n");
                        pval.intval = 500;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CURRENT_AVG,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CURRENT_AVG,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set chg aicr fail\n");
                        pval.intval = 500;
-                       rc = chg_psy->set_property(chg_psy, POWER_SUPPLY_PROP_CURRENT_NOW,\
-                               &pval);
+                       rc = chg_psy->set_property(chg_psy,
+                                       POWER_SUPPLY_PROP_CURRENT_NOW,
+                                       &pval);
                        if (rc < 0)
                                dev_err(pi->dev, "set chg icc fail\n");
                }
@@ -198,8 +227,9 @@ static int rtpower_set_charger(struct rt_power_info *pi)
        return rc;
 }
 
-static int rtpower_get_property(struct power_supply *psy, enum power_supply_property psp, \
-                       union power_supply_propval *val)
+static int rtpower_get_property(struct power_supply *psy,
+                               enum power_supply_property psp,
+                               union power_supply_propval *val)
 {
        struct rt_power_info *pi = dev_get_drvdata(psy->dev->parent);
        int rc = 0;
@@ -207,7 +237,8 @@ static int rtpower_get_property(struct power_supply *psy, enum power_supply_prop
        switch (psp) {
        case POWER_SUPPLY_PROP_ONLINE:
                if (psy->type == POWER_SUPPLY_TYPE_MAINS)
-                       val->intval = (pi->ac_online || pi->usbta_online)?1 : 0;
+                       val->intval = (pi->ac_online
+                                      || pi->usbta_online) ? 1 : 0;
                else if (psy->type == POWER_SUPPLY_TYPE_USB)
                        val->intval = pi->usb_online;
                else
@@ -220,7 +251,8 @@ static int rtpower_get_property(struct power_supply *psy, enum power_supply_prop
        return rc;
 }
 
-static int rtpower_set_property(struct power_supply *psy, enum power_supply_property psp, \
+static int rtpower_set_property(struct power_supply *psy,
+                               enum power_supply_property psp,
                                const union power_supply_propval *val)
 {
        struct rt_power_info *pi = dev_get_drvdata(psy->dev->parent);
@@ -239,13 +271,16 @@ static int rtpower_set_property(struct power_supply *psy, enum power_supply_prop
                                if (val->intval) {
                                        pi->usbcnt = 0;
                                        wake_lock(&pi->usbdet_wakelock);
-                                       schedule_delayed_work(&pi->usbdet_work, 1*HZ);
+                                       schedule_delayed_work(&pi->usbdet_work,
+                                                             1 * HZ);
                                } else {
                                        pi->usbcnt = RT_USBCNT_MAX;
-                                       schedule_delayed_work(&pi->usbdet_work, 0);
+                                       schedule_delayed_work(&pi->usbdet_work,
+                                                             0);
                                        if (pi->usbta_online) {
                                                pi->usbta_online = 0;
-                                               power_supply_changed(&pi->ac_psy);
+                                               power_supply_changed
+                                                   (&pi->ac_psy);
                                        }
                                }
                                rc = rtpower_set_charger(pi);

diff --git a/drivers/power/rt5036-charger.c b/drivers/power/rt5036-charger.c
new file mode 100755 (executable)
index 0000000..8583078
--- /dev/null
+++ b/drivers/power/rt5036-charger.c
@@ -0,0 +1,1234 @@
+/*
+ *  drivers/power/rt5036-charger.c
+ *  Driver for Richtek RT5036 PMIC Charger driver
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/version.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/workqueue.h>
+#include <linux/of.h>
+#include <linux/power_supply.h>
+#include <linux/delay.h>
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+#include <linux/of_gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+
+#include <linux/mfd/rt5036/rt5036.h>
+#include <linux/power/rt5036-charger.h>
+#ifdef CONFIG_RT_POWER
+#include <linux/power/rt-power.h>
+#endif /* #ifdef CONFIG_RT_POWER */
+#ifdef CONFIG_RT_BATTERY
+#include <linux/power/rt-battery.h>
+#endif /* #ifdef CONFIG_RT_BATTERY */
+
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+#define RT5036_ACIN_LEVEL      0
+#define RT5036_USBIN_LEVEL     1
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+
+static unsigned char chg_init_regval[] = {
+       0xb0,                   /*REG 0x01*/
+       0x58,                   /*REG 0x02*/
+       0x00,                   /*REG 0x03*/
+       0xFE,                   /*REG 0x04*/
+       0x93,                   /*REG 0x05*/
+       0xAD,                   /*REG 0x06*/
+       0xB4,                   /*REG 0x07*/
+       0x01,                   /*REG 0x08*/
+       0x0C,                   /*REG 0x13*/
+       0x80,                   /*REG 0x14*/
+       0x00,                   /*REG 0x15*/
+       0x70,                   /*REG 0x18*/
+};
+
+static char *rtdef_chg_name = "rt-charger";
+
+static char *rt_charger_supply_list[] = {
+       "none",
+};
+
+static enum power_supply_property rt_charger_props[] = {
+       POWER_SUPPLY_PROP_STATUS,
+       POWER_SUPPLY_PROP_ONLINE,
+       POWER_SUPPLY_PROP_PRESENT,
+       POWER_SUPPLY_PROP_CHARGE_NOW,
+       POWER_SUPPLY_PROP_CURRENT_MAX,
+       POWER_SUPPLY_PROP_CURRENT_AVG,
+       POWER_SUPPLY_PROP_CURRENT_NOW,
+       POWER_SUPPLY_PROP_VOLTAGE_NOW,
+       POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+       POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+};
+
+static int rt_charger_get_property(struct power_supply *psy,
+                                  enum power_supply_property psp,
+                                  union power_supply_propval *val)
+{
+       struct rt5036_charger_info *ci = dev_get_drvdata(psy->dev->parent);
+       int ret = 0;
+       int regval = 0;
+
+       switch (psp) {
+       case POWER_SUPPLY_PROP_ONLINE:
+               val->intval = ci->online;
+               break;
+       case POWER_SUPPLY_PROP_STATUS:
+               regval = rt5036_reg_read(ci->i2c, RT5036_REG_CHGSTAT1);
+               if (regval < 0) {
+                       ret = -EINVAL;
+               } else {
+                       regval &= RT5036_CHGSTAT_MASK;
+                       regval >>= RT5036_CHGSTAT_SHIFT;
+                       switch (regval) {
+                       case 0:
+                               val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
+                               break;
+                       case 1:
+                               val->intval = POWER_SUPPLY_STATUS_CHARGING;
+                               break;
+                       case 2:
+                               val->intval = POWER_SUPPLY_STATUS_FULL;
+                               break;
+                       case 3:
+                               val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
+                               break;
+                       }
+               }
+               break;
+       case POWER_SUPPLY_PROP_PRESENT:
+               regval = rt5036_reg_read(ci->i2c, RT5036_REG_CHGSTAT1);
+               if (regval < 0) {
+                       ret = -EINVAL;
+               } else {
+                       if (regval & RT5036_CHGDIS_MASK)
+                               val->intval = 0;
+                       else
+                               val->intval = 1;
+               }
+               break;
+       case POWER_SUPPLY_PROP_CHARGE_NOW:
+               val->intval = ci->charge_cable;
+               break;
+       case POWER_SUPPLY_PROP_CURRENT_MAX:
+               val->intval = 2000;
+               break;
+       case POWER_SUPPLY_PROP_CURRENT_AVG:
+               regval = rt5036_reg_read(ci->i2c, RT5036_REG_CHGCTL1);
+               if (regval < 0) {
+                       ret = -EINVAL;
+               } else {
+                       regval &= RT5036_CHGAICR_MASK;
+                       regval >>= RT5036_CHGAICR_SHIFT;
+                       switch (regval) {
+                       case 0:
+                               val->intval = 0;
+                               break;
+                       case 1:
+                               val->intval = 100;
+                               break;
+                       case 2:
+                               val->intval = 500;
+                               break;
+                       case 3:
+                               val->intval = 700;
+                               break;
+                       case 4:
+                               val->intval = 900;
+                               break;
+                       case 5:
+                               val->intval = 1000;
+                               break;
+                       case 6:
+                               val->intval = 1500;
+                               break;
+                       case 7:
+                               val->intval = 2000;
+                               break;
+                       }
+               }
+               break;
+       case POWER_SUPPLY_PROP_CURRENT_NOW:
+               regval = rt5036_reg_read(ci->i2c, RT5036_REG_CHGSTAT1);
+               if (regval < 0) {
+                       ret = -EINVAL;
+               } else {
+                       if (regval & RT5036_CHGOPASTAT_MASK) {
+                               val->intval = -1;
+                       } else {
+                               regval =
+                                   rt5036_reg_read(ci->i2c,
+                                                   RT5036_REG_CHGCTL5);
+                               if (regval < 0) {
+                                       ret = -EINVAL;
+                               } else {
+                                       regval &= RT5036_CHGICC_MASK;
+                                       regval >>= RT5036_CHGICC_SHIFT;
+                                       val->intval = 500 + regval * 100;
+                               }
+                       }
+               }
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+               regval = rt5036_reg_read(ci->i2c, RT5036_REG_CHGCTL2);
+               if (regval < 0) {
+                       ret = -EINVAL;
+               } else {
+                       regval &= RT5036_CHGCV_MASK;
+                       regval >>= RT5036_CHGCV_SHIFT;
+                       val->intval = regval * 25 + 3650;
+               }
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+               val->intval = 3650;
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+               val->intval = 4400;
+               break;
+       default:
+               ret = -EINVAL;
+       }
+       return ret;
+}
+
+static int rt_charger_set_property(struct power_supply *psy,
+                                  enum power_supply_property psp,
+                                  const union power_supply_propval *val)
+{
+       struct rt5036_charger_info *ci = dev_get_drvdata(psy->dev->parent);
+       int ret = 0;
+       int regval = 0;
+
+       RTINFO("prop = %d, val->intval = %d\n", psp, val->intval);
+       switch (psp) {
+       case POWER_SUPPLY_PROP_ONLINE:
+               ci->online = val->intval;
+               if (ci->online) {
+#ifdef CONFIG_RT_BATTERY
+                       union power_supply_propval pval;
+                       struct power_supply *psy =
+                           power_supply_get_by_name(RT_BATT_NAME);
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_CHARGING;
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get RT battery\n");
+                       }
+#else
+#ifdef CONFIG_RT9420_FUELGAUGE
+                       union power_supply_propval pval;
+                       struct power_supply *psy =
+                           power_supply_get_by_name("rt-fuelgauge");
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_CHARGING;
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev,
+                                       "couldn't get rt fuelgauge battery\n");
+                               }
+#else
+                       union power_supply_propval pval;
+                       struct power_supply *psy =
+                           power_supply_get_by_name("battery");
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_CHARGING;
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get battery\n");
+                               }
+#endif /* #ifdef CONFIG_RT9420_FUELGAUGE */
+#endif /* #ifdef CONFIG_RT_BATTERY */
+                       if (ci->te_en)
+                               ret =
+                                   rt5036_set_bits(ci->i2c, RT5036_REG_CHGCTL1,
+                                                   RT5036_CHGTEEN_MASK);
+               } else {
+#ifdef CONFIG_RT_BATTERY
+                       union power_supply_propval pval;
+                       struct power_supply *psy =
+                           power_supply_get_by_name(RT_BATT_NAME);
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_DISCHARGING;
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get RT battery\n");
+                       }
+#else
+#ifdef CONFIG_RT9420_FUELGAUGE
+                       union power_supply_propval pval;
+                       struct power_supply *psy =
+                           power_supply_get_by_name("rt-fuelgauge");
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_DISCHARGING;
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev,
+                                       "couldn't get rt fuelgauge battery\n");
+                       }
+#else
+                       union power_supply_propval pval;
+                       struct power_supply *psy =
+                           power_supply_get_by_name("battery");
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_DISCHARGING;
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get battery\n");
+                       }
+#endif /* #ifdef CONFIG_RT9420_FUELGAUGE */
+#endif /* #ifdef CONFIG_RT_BATTERY */
+                       if (ci->te_en) {
+                               ret =
+                                   rt5036_clr_bits(ci->i2c, RT5036_REG_CHGCTL1,
+                                                   RT5036_CHGTEEN_MASK);
+                               /* te rst workaround */
+                               rt5036_set_bits(ci->i2c, 0x20,
+                                               RT5036_TERST_MASK);
+                               rt5036_clr_bits(ci->i2c, 0x20,
+                                               RT5036_TERST_MASK);
+                       }
+               }
+               break;
+       case POWER_SUPPLY_PROP_PRESENT:
+               if (ci->online && val->intval) {
+                       int icc = 0;
+                       union power_supply_propval pval;
+
+                       if (ci->charge_cable == POWER_SUPPLY_TYPE_MAINS)
+                               icc = ci->acchg_icc;
+                       else if (ci->charge_cable == POWER_SUPPLY_TYPE_USB_DCP)
+                               icc = ci->usbtachg_icc;
+                       else
+                               icc = ci->usbchg_icc;
+                       pval.intval = icc;
+                       ret =
+                           psy->set_property(psy,
+                                             POWER_SUPPLY_PROP_CURRENT_NOW,
+                                             &pval);
+                       if (ret < 0)
+                               dev_err(ci->dev, "set final icc fail\n");
+               }
+               break;
+       case POWER_SUPPLY_PROP_CHARGE_NOW:
+               ci->charge_cable = val->intval;
+               break;
+       case POWER_SUPPLY_PROP_CURRENT_AVG:
+               if (val->intval <= 0)
+                       regval = 0;
+               else if (val->intval <= 100)
+                       regval = 1;
+               else if (val->intval <= 500)
+                       regval = 2;
+               else if (val->intval <= 700)
+                       regval = 3;
+               else if (val->intval <= 900)
+                       regval = 4;
+               else if (val->intval <= 1000)
+                       regval = 5;
+               else if (val->intval <= 1500)
+                       regval = 6;
+               else if (val->intval <= 2000)
+                       regval = 7;
+               else
+                       regval = 0;
+               if (!ci->batabs)
+                       ret = rt5036_assign_bits(ci->i2c, RT5036_REG_CHGCTL1,
+                                                RT5036_CHGAICR_MASK,
+                                                regval <<
+                                                RT5036_CHGAICR_SHIFT);
+               break;
+       case POWER_SUPPLY_PROP_CURRENT_NOW:
+               if (val->intval < 0) {
+                       union power_supply_propval pval;
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+                       struct power_supply *psy =
+                           power_supply_get_by_name(RT_USB_NAME);
+                       pval.intval = 0;
+                       psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &pval);
+                       power_supply_changed(psy);
+                       ci->otg_en = 1;
+                       if (ci->charge_cable != POWER_SUPPLY_TYPE_MAINS) {
+                               /* otg drop fix */
+                               rt5036_set_bits(ci->i2c, 0x23, 0x3);
+                               pval.intval = ci->otg_volt;
+                               ci->psy.set_property(&ci->psy,
+                                       POWER_SUPPLY_PROP_VOLTAGE_NOW,
+                                       &pval);
+                               ret =
+                                   rt5036_set_bits(ci->i2c, RT5036_REG_CHGCTL1,
+                                                   RT5036_CHGOPAMODE_MASK);
+                               /* otg drop fix */
+                               mdelay(10);
+                               rt5036_clr_bits(ci->i2c, 0x23, 0x3);
+                       }
+#else
+                       ci->otg_en = 1;
+                       /* otg drop fix */
+                       rt5036_set_bits(ci->i2c, 0x23, 0x3);
+                       pval.intval = ci->otg_volt;
+                       ci->psy.set_property(&ci->psy,
+                                            POWER_SUPPLY_PROP_VOLTAGE_NOW,
+                                            &pval);
+                       ret =
+                           rt5036_set_bits(ci->i2c, RT5036_REG_CHGCTL1,
+                                           RT5036_CHGOPAMODE_MASK);
+                       /* otg drop fix */
+                       mdelay(10);
+                       rt5036_clr_bits(ci->i2c, 0x23, 0x3);
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+               } else if (val->intval == 0) {
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+                       if (ci->charge_cable != POWER_SUPPLY_TYPE_MAINS)
+                               ret =
+                                   rt5036_clr_bits(ci->i2c, RT5036_REG_CHGCTL1,
+                                                   RT5036_CHGOPAMODE_MASK);
+#else
+                       ret =
+                           rt5036_clr_bits(ci->i2c, RT5036_REG_CHGCTL1,
+                                           RT5036_CHGOPAMODE_MASK);
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+                       ci->otg_en = 0;
+               } else if (val->intval < 500)
+                       regval = 0;
+               else if (val->intval > 2000)
+                       regval = 15;
+               else
+                       regval = (val->intval - 500) / 100;
+               regval += 5;
+               if (regval > 15)
+                       regval = 15;
+               if (!ci->batabs && val->intval > 0)
+                       ret =
+                           rt5036_assign_bits(ci->i2c, RT5036_REG_CHGCTL5,
+                                              RT5036_CHGICC_MASK,
+                                              regval << RT5036_CHGICC_SHIFT);
+               rt5036_reg_write(ci->i2c, RT5036_REG_CHGCTL4,
+                                chg_init_regval[4]);
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+               if (val->intval < 3650)
+                       regval = 0;
+               else if (val->intval > 5225)
+                       regval = 0x3F;
+               else
+                       regval = (val->intval - 3650) / 25;
+               ret =
+                   rt5036_assign_bits(ci->i2c, RT5036_REG_CHGCTL2,
+                                      RT5036_CHGCV_MASK,
+                                      regval << RT5036_CHGCV_SHIFT);
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+       case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+       case POWER_SUPPLY_PROP_CURRENT_MAX:
+       case POWER_SUPPLY_PROP_STATUS:
+       default:
+               ret = -EINVAL;
+       }
+       return ret;
+}
+
+static void rt5036_stat2alrt_irq_handler(void *info, int eventno)
+{
+       struct rt5036_charger_info *ci = info;
+       unsigned char old_stat, new_stat;
+       int ret;
+
+       old_stat = ci->stat2;
+       ret = rt5036_reg_read(ci->i2c, RT5036_REG_CHGSTAT2);
+       if (ret < 0) {
+               dev_err(ci->dev, "read stat io fail\n");
+               return;
+       }
+       new_stat = ret;
+       /*cablein status change*/
+       if ((old_stat ^ new_stat) & RT5036_PWRRDY_MASK) {
+               if (new_stat & RT5036_PWRRDY_MASK) {
+#ifndef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+                       union power_supply_propval pval;
+                       struct power_supply *psy =
+                           power_supply_get_by_name(RT_USB_NAME);
+                       if (psy) {
+                               pval.intval = 1;
+                               psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get RT usb\n");
+                       }
+#endif /* #ifndef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+                       dev_info(ci->dev, "cable in\n");
+               } else {
+#ifndef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+                       union power_supply_propval pval;
+                       struct power_supply *psy =
+                           power_supply_get_by_name(RT_USB_NAME);
+                       if (psy) {
+                               pval.intval = 0;
+                               psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get RT usb\n");
+                       }
+#endif /* #ifndef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+                       dev_info(ci->dev, "cable out\n");
+               }
+       }
+       /*jeita status change*/
+       old_stat = new_stat & RT5036_TSEVENT_MASK;
+       if (old_stat & RT5036_TSWC_MASK) {
+               dev_info(ci->dev, "warm or cool parameter\n");
+               rt5036_set_bits(ci->i2c, RT5036_REG_CHGCTL7,
+                               RT5036_CCJEITA_MASK);
+       } else if (old_stat & RT5036_TSHC_MASK) {
+               dev_info(ci->dev, "hot or cold temperature\n");
+               rt5036_clr_bits(ci->i2c, RT5036_REG_CHGCTL7,
+                               RT5036_CCJEITA_MASK);
+       } else {
+               dev_info(ci->dev, "normal temperature\n");
+               rt5036_clr_bits(ci->i2c, RT5036_REG_CHGCTL7,
+                               RT5036_CCJEITA_MASK);
+       }
+       ci->stat2 = new_stat;
+}
+
+static void rt5036_batabs_irq_handler(void *info, int eventno)
+{
+       struct rt5036_charger_info *ci = info;
+       struct power_supply *psy = &ci->psy;
+       union power_supply_propval val;
+       int ret;
+       /*disable battery detection*/
+       ret = rt5036_clr_bits(ci->i2c, RT5036_REG_CHGCTL6, RT5036_BATDEN_MASK);
+       if (ret < 0)
+               dev_err(ci->dev, "set battary detection disable fail\n");
+       /*set aicr to 2000*/
+       val.intval = 2000;
+       ret = psy->set_property(psy, POWER_SUPPLY_PROP_CURRENT_AVG, &val);
+       if (ret < 0)
+               dev_err(ci->dev, "set aicr to 2000 fail\n");
+       /*set icc to 2000*/
+       val.intval = 2000;
+       ret = psy->set_property(psy, POWER_SUPPLY_PROP_CURRENT_NOW, &val);
+       if (ret < 0)
+               dev_err(ci->dev, "set icc to 2000 fail\n");
+       /*set charger offline*/
+       val.intval = 0;
+       ret = psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &val);
+       if (ret < 0)
+               dev_err(ci->dev, "set charger offline fail\n");
+#ifdef CONFIG_RT_BATTERY
+       psy = power_supply_get_by_name(RT_BATT_NAME);
+       if (psy) {
+               val.intval = 0;
+               ret = psy->set_property(psy, POWER_SUPPLY_PROP_PRESENT, &val);
+               if (ret < 0)
+                       dev_err(ci->dev, "set battery not present fail\n");
+       } else {
+               dev_err(ci->dev, "couldn't get batt psy\n");
+               }
+#else
+#ifdef CONFIG_RT9420_FUELGAUGE
+       psy = power_supply_get_by_name("rt-fuelgauge");
+       if (psy) {
+               val.intval = 0;
+               ret = psy->set_property(psy, POWER_SUPPLY_PROP_PRESENT, &val);
+               if (ret < 0)
+                       dev_err(ci->dev, "set battery not present fail\n");
+       } else {
+               dev_err(ci->dev, "couldn't get rt fuelgauge psy\n");
+               }
+#else
+       psy = power_supply_get_by_name("battery");
+       if (psy) {
+               val.intval = 0;
+               ret = psy->set_property(psy, POWER_SUPPLY_PROP_PRESENT, &val);
+               if (ret < 0)
+                       dev_err(ci->dev, "set battery not present fail\n");
+       } else {
+               dev_err(ci->dev, "couldn't get battery psy\n");
+               }
+#endif /* #ifdef CONFIG_RT9420_FUELGAUGE */
+#endif /* #ifdef CONFIG_RT_BATTERY */
+       ci->batabs = 1;
+}
+
+static void rt5036_general_irq_handler(void *info, int eventno)
+{
+       struct rt5036_charger_info *ci = info;
+
+       RTINFO("eventno=%02d\n", eventno);
+       switch (eventno) {
+       case CHGEVENT_CHTMRFI:
+               rt5036_clr_bits(ci->i2c, RT5036_REG_CHGCTL3,
+                               RT5036_CHGOTGEN_MASK);
+               msleep(5);
+               rt5036_set_bits(ci->i2c, RT5036_REG_CHGCTL3,
+                               RT5036_CHGOTGEN_MASK);
+               break;
+       case CHGEVENT_CHRCHGI:
+               if (!ci->online) {
+                       dev_warn(ci->dev, "recharge false alarm\n");
+               } else {
+#ifdef CONFIG_RT_BATTERY
+                       struct power_supply *psy =
+                           power_supply_get_by_name(RT_BATT_NAME);
+                       union power_supply_propval pval;
+
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_CHARGING;
+                               /*set battery status*/
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get batt psy\n");
+                               }
+#else
+#ifdef CONFIG_RT9420_FUELGAUGE
+                       struct power_supply *psy =
+                           power_supply_get_by_name("rt-fuelgauge");
+                       union power_supply_propval pval;
+
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_CHARGING;
+                               /*set battery status*/
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev,
+                                       "couldn't get rt fuelgauge psy\n");
+                               }
+#else
+                       struct power_supply *psy =
+                           power_supply_get_by_name("battery");
+                       union power_supply_propval pval;
+
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_CHARGING;
+                               /*set battery status*/
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get battery psy\n");
+                               }
+#endif /* #ifdef CONFIG_RT9420_FUELGAUGE */
+#endif /* #ifdfef CONFIG_RT_BATTERY */
+                       dev_info(ci->dev, "recharge occur\n");
+               }
+               break;
+       case CHGEVENT_IEOCI:
+               if (!ci->online) {
+                       dev_warn(ci->dev, "eoc false alarm\n");
+               } else {
+#ifdef CONFIG_RT_BATTERY
+                       struct power_supply *psy =
+                           power_supply_get_by_name(RT_BATT_NAME);
+                       union power_supply_propval pval;
+
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_FULL;
+                               /*set battery status*/
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get batt psy\n");
+                               }
+#else
+#ifdef CONFIG_RT9420_FUELGAUGE
+                       struct power_supply *psy =
+                           power_supply_get_by_name("rt-fuelgauge");
+                       union power_supply_propval pval;
+
+                       if (psy) {
+                               /*set battery status*/
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev,
+                                       "couldn't get rt fuelgauge psy\n");
+                               }
+#else
+                       struct power_supply *psy =
+                           power_supply_get_by_name("battery");
+                       union power_supply_propval pval;
+
+                       if (psy) {
+                               pval.intval = POWER_SUPPLY_STATUS_FULL;
+                               /*set battery status*/
+                               psy->set_property(psy, POWER_SUPPLY_PROP_STATUS,
+                                                 &pval);
+                               power_supply_changed(psy);
+                       } else {
+                               dev_err(ci->dev, "couldn't get battery psy\n");
+                               }
+#endif /* #ifdef CONFIG_RT9420_FUELGAUGE */
+#endif /* #ifdfef CONFIG_RT_BATTERY */
+                       dev_info(ci->dev, "eoc really occur\n");
+               }
+               break;
+       default:
+               break;
+       }
+}
+
+static rt_irq_handler rt_chgirq_handler[CHGEVENT_MAX] = {
+       [CHGEVENT_STAT2ALT] = rt5036_stat2alrt_irq_handler,
+       [CHGEVENT_CHBSTLOWVI] = rt5036_general_irq_handler,
+       [CHGEVENT_BSTOLI] = rt5036_general_irq_handler,
+       [CHGEVENT_BSTVIMIDOVP] = rt5036_general_irq_handler,
+       [CHGEVENT_CHTMRFI] = rt5036_general_irq_handler,
+       [CHGEVENT_CHRCHGI] = rt5036_general_irq_handler,
+       [CHGEVENT_CHTERMI] = rt5036_general_irq_handler,
+       [CHGEVENT_CHBATOVI] = rt5036_general_irq_handler,
+       [CHGEVENT_CHRVPI] = rt5036_general_irq_handler,
+       [CHGEVENT_BATABSENSE] = rt5036_batabs_irq_handler,
+       [CHGEVENT_CHBADADPI] = rt5036_general_irq_handler,
+       [CHGEVENT_VINCHGPLUGOUT] = rt5036_general_irq_handler,
+       [CHGEVENT_VINCHGPLUGIN] = rt5036_general_irq_handler,
+       [CHGEVENT_PPBATLVI] = rt5036_general_irq_handler,
+       [CHGEVENT_IEOCI] = rt5036_general_irq_handler,
+       [CHGEVENT_VINOVPI] = rt5036_general_irq_handler,
+};
+
+void rt5036_charger_irq_handler(struct rt5036_charger_info *ci,
+                               unsigned int irqevent)
+{
+       int i;
+       unsigned int masked_irq_event =
+           (chg_init_regval[8] << 16) | (chg_init_regval[9] << 8) |
+           chg_init_regval[10];
+       unsigned int final_irq_event = irqevent & (~masked_irq_event);
+
+       for (i = 0; i < CHGEVENT_MAX; i++) {
+               if ((final_irq_event & (1 << i)) && rt_chgirq_handler[i])
+                       rt_chgirq_handler[i] (ci, i);
+       }
+}
+EXPORT_SYMBOL(rt5036_charger_irq_handler);
+
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+static irqreturn_t rt5036_acdet_irq_handler(int irqno, void *param)
+{
+       struct rt5036_charger_info *ci = param;
+
+       if (RT5036_ACIN_LEVEL == gpio_get_value(ci->acdet_gpio)) {
+               union power_supply_propval pval;
+               struct power_supply *psy = power_supply_get_by_name(RT_AC_NAME);
+
+               if (RT5036_ACIN_LEVEL)
+                       irq_set_irq_type(ci->acdet_irq, IRQF_TRIGGER_FALLING);
+               else
+                       irq_set_irq_type(ci->acdet_irq, IRQF_TRIGGER_RISING);
+               if (psy) {
+                       if (ci->otg_en)
+                               rt5036_clr_bits(ci->i2c, RT5036_REG_CHGCTL1,
+                                               RT5036_CHGOPAMODE_MASK);
+                       pval.intval = 1;
+                       psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &pval);
+                       power_supply_changed(psy);
+               } else {
+                       dev_err(ci->dev, "couldn't get RT ac\n");
+                       }
+               dev_info(ci->dev, "ac in\n");
+       } else {
+               union power_supply_propval pval;
+               struct power_supply *psy = power_supply_get_by_name(RT_AC_NAME);
+
+               if (RT5036_ACIN_LEVEL)
+                       irq_set_irq_type(ci->acdet_irq, IRQF_TRIGGER_RISING);
+               else
+                       irq_set_irq_type(ci->acdet_irq, IRQF_TRIGGER_FALLING);
+               if (psy) {
+                       pval.intval = 0;
+                       psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &pval);
+                       power_supply_changed(psy);
+                       if (ci->otg_en) {
+                               /*set otg voltage*/
+                               pval.intval = ci->otg_volt;
+                               ci->psy.set_property(&ci->psy,
+                                       POWER_SUPPLY_PROP_VOLTAGE_NOW,
+                                       &pval);
+                               rt5036_set_bits(ci->i2c, RT5036_REG_CHGCTL1,
+                                               RT5036_CHGOPAMODE_MASK);
+                       }
+               } else {
+                       dev_err(ci->dev, "couldn't get RT ac\n");
+                       }
+               dev_info(ci->dev, "ac out\n");
+       }
+       return IRQ_HANDLED;
+}
+
+static irqreturn_t rt5036_usbdet_irq_handler(int irqno, void *param)
+{
+       struct rt5036_charger_info *ci = param;
+
+       if (ci->otg_en) {
+               dev_info(ci->dev, "currently in otg mode\n");
+               goto usb_out;
+       }
+       if (RT5036_USBIN_LEVEL == gpio_get_value(ci->usbdet_gpio)) {
+               union power_supply_propval pval;
+               struct power_supply *psy =
+                   power_supply_get_by_name(RT_USB_NAME);
+               if (RT5036_USBIN_LEVEL)
+                       irq_set_irq_type(ci->usbdet_irq, IRQF_TRIGGER_FALLING);
+               else
+                       irq_set_irq_type(ci->usbdet_irq, IRQF_TRIGGER_RISING);
+               if (psy) {
+                       pval.intval = 1;
+                       psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &pval);
+                       power_supply_changed(psy);
+               } else {
+                       dev_err(ci->dev, "couldn't get RT usb\n");
+                       }
+               dev_info(ci->dev, "usb in\n");
+       } else {
+               union power_supply_propval pval;
+               struct power_supply *psy =
+                   power_supply_get_by_name(RT_USB_NAME);
+               if (RT5036_USBIN_LEVEL)
+                       irq_set_irq_type(ci->usbdet_irq, IRQF_TRIGGER_RISING);
+               else
+                       irq_set_irq_type(ci->usbdet_irq, IRQF_TRIGGER_FALLING);
+               if (psy) {
+                       pval.intval = 0;
+                       psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &pval);
+                       power_supply_changed(psy);
+               } else {
+                       dev_err(ci->dev, "couldn't get RT usb\n");
+                       }
+               dev_info(ci->dev, "usb out\n");
+       }
+usb_out:
+       return IRQ_HANDLED;
+}
+
+static int rt5036_acusb_irqinit(struct rt5036_charger_info *ci)
+{
+       int rc = 0;
+
+       if (gpio_is_valid(ci->acdet_gpio) && gpio_is_valid(ci->usbdet_gpio)) {
+               rc = gpio_request(ci->acdet_gpio, "rt5036_acdet_gpio");
+               if (rc < 0) {
+                       dev_err(ci->dev, "request acdet gpio fail\n");
+                       goto irq_out;
+               }
+               rc = gpio_request(ci->usbdet_gpio, "rt5036_usbdet_gpio");
+               if (rc < 0) {
+                       dev_err(ci->dev, "request usbdet gpio fail\n");
+                       goto irq_out;
+               }
+               gpio_direction_input(ci->acdet_gpio);
+               gpio_direction_input(ci->usbdet_gpio);
+
+               ci->acdet_irq = gpio_to_irq(ci->acdet_gpio);
+               ci->usbdet_irq = gpio_to_irq(ci->usbdet_gpio);
+
+               rc = devm_request_threaded_irq(ci->dev, ci->acdet_irq, NULL,
+                                              rt5036_acdet_irq_handler,
+                                              IRQF_TRIGGER_FALLING |
+                                              IRQF_DISABLED,
+                                              "rt5036_acdet_irq", ci);
+               if (rc < 0) {
+                       dev_err(ci->dev, "request acdet irq fail\n");
+                       goto irq_out;
+               }
+               rc = devm_request_threaded_irq(ci->dev, ci->usbdet_irq, NULL,
+                                              rt5036_usbdet_irq_handler,
+                                              IRQF_TRIGGER_FALLING |
+                                              IRQF_DISABLED,
+                                              "rt5036_usbdet_irq", ci);
+               if (rc < 0) {
+                       dev_err(ci->dev, "request usbdet irq fail\n");
+                       goto irq_out;
+               }
+               enable_irq_wake(ci->acdet_irq);
+               enable_irq_wake(ci->usbdet_irq);
+       } else {
+               rc = -EINVAL;
+               }
+irq_out:
+       return rc;
+}
+
+static void rt5036_acusb_irqdeinit(struct rt5036_charger_info *ci)
+{
+       devm_free_irq(ci->dev, ci->acdet_irq, ci);
+       devm_free_irq(ci->dev, ci->usbdet_irq, ci);
+       gpio_free(ci->acdet_gpio);
+       gpio_free(ci->usbdet_gpio);
+}
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+
+static void rt5036_chg_dwork_func(struct work_struct *work)
+{
+       struct rt5036_charger_info *ci =
+           container_of(work, struct rt5036_charger_info,
+                        dwork.work);
+       rt5036_stat2alrt_irq_handler(ci, 0);
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+       rt5036_acdet_irq_handler(ci->acdet_irq, ci);
+       rt5036_usbdet_irq_handler(ci->usbdet_irq, ci);
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+}
+
+static int rt5036_charger_reginit(struct i2c_client *client)
+{
+       /*thermal HGM*/
+       rt5036_set_bits(client, 0x20, 0x40);
+       /*charger fix in rev D IC*/
+       rt5036_reg_write(client, 0x22, 0xE0);
+       /*write charger init val*/
+       rt5036_reg_block_write(client, RT5036_REG_CHGCTL1, 8, chg_init_regval);
+       rt5036_reg_block_write(client, RT5036_REG_CHGIRQMASK1, 3,
+                              &chg_init_regval[8]);
+       rt5036_reg_write(client, RT5036_REG_CHGSTAT2MASK, chg_init_regval[11]);
+       /*always read at first time*/
+       rt5036_reg_read(client, RT5036_REG_CHGIRQ1);
+       rt5036_reg_read(client, RT5036_REG_CHGIRQ2);
+       rt5036_reg_read(client, RT5036_REG_CHGIRQ3);
+       rt5036_set_bits(client, 0x20, RT5036_TERST_MASK);
+       rt5036_clr_bits(client, 0x20, RT5036_TERST_MASK);
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt_parse_dt(struct rt5036_charger_info *ci,
+                                struct device *dev)
+{
+#ifdef CONFIG_OF
+       struct device_node *np = dev->of_node;
+       u32 val;
+
+       if (of_property_read_bool(np, "rt,te_en"))
+               ci->te_en = 1;
+
+       if (of_property_read_u32(np, "rt,iprec", &val)) {
+               dev_info(dev, "no iprec property, use the default value\n");
+       } else {
+               if (val > RT5036_IPREC_MAX)
+                       val = RT5036_IPREC_MAX;
+               chg_init_regval[4] &= (~RT5036_CHGIPREC_MASK);
+               chg_init_regval[4] |= (val << RT5036_CHGIPREC_SHIFT);
+       }
+
+       if (of_property_read_u32(np, "rt,ieoc", &val)) {
+               dev_info(dev, "no ieoc property, use the default value\n");
+       } else {
+               if (val > RT5036_IEOC_MAX)
+                       val = RT5036_IEOC_MAX;
+               chg_init_regval[4] &= (~RT5036_CHGIEOC_MASK);
+               chg_init_regval[4] |= val;
+       }
+
+       if (of_property_read_u32(np, "rt,vprec", &val)) {
+               dev_info(dev, "no vprec property, use the default value\n");
+       } else {
+               if (val > RT5036_VPREC_MAX)
+                       val = RT5036_VPREC_MAX;
+               chg_init_regval[5] &= (~RT5036_CHGVPREC_MASK);
+               chg_init_regval[5] |= val;
+       }
+
+       if (of_property_read_u32(np, "rt,batlv", &val)) {
+               dev_info(dev, "no batlv property, use the default value\n");
+       } else {
+               if (val > RT5036_BATLV_MAX)
+                       val = RT5036_BATLV_MAX;
+               chg_init_regval[6] &= (~RT5036_CHGBATLV_MASK);
+               chg_init_regval[6] |= val;
+       }
+
+       if (of_property_read_u32(np, "rt,vrechg", &val)) {
+               dev_info(dev, "no vrechg property, use the default value\n");
+       } else {
+               if (val > RT5036_VRECHG_MAX)
+                       val = RT5036_VRECHG_MAX;
+               chg_init_regval[7] &= (~RT5036_CHGVRECHG_MASK);
+               chg_init_regval[7] |= (val << RT5036_CHGVRECHG_SHIFT);
+       }
+
+       if (of_property_read_u32(np, "rt,chg_volt", &val)) {
+               dev_info(dev,
+                        "no chg_volt property, use 4200 as the default value\n");
+               ci->chg_volt = 4200;
+       } else {
+               ci->chg_volt = val;
+               }
+
+       if (of_property_read_u32(np, "rt,otg_volt", &val)) {
+               dev_info(dev,
+                        "no otg_volt property, use 5025 as the default value\n");
+               ci->otg_volt = 5025;
+       } else {
+               ci->otg_volt = val;
+               }
+
+       if (of_property_read_u32(np, "rt,acchg_icc", &val)) {
+               dev_info(dev,
+                        "no acchg_icc property, use 2000 as the default value\n");
+               ci->acchg_icc = 2000;
+       } else {
+               ci->acchg_icc = val;
+               }
+
+       if (of_property_read_u32(np, "rt,usbtachg_icc", &val)) {
+               dev_info(dev,
+                        "no usbtachg_icc property, use 2000 as the default value\n");
+               ci->usbtachg_icc = 2000;
+       } else {
+               ci->usbtachg_icc = val;
+               }
+
+       if (of_property_read_u32(np, "rt,usbchg_icc", &val)) {
+               dev_info(dev,
+                        "no usbchg_icc property, use 500 as the default value\n");
+               ci->usbchg_icc = 500;
+       } else {
+               ci->usbchg_icc = val;
+               }
+
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+       ci->acdet_gpio = of_get_named_gpio(np, "rt,acdet_gpio", 0);
+       ci->usbdet_gpio = of_get_named_gpio(np, "rt,usbdet_gpio", 0);
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+#endif /* #ifdef CONFIG_OF */
+       rt5036_charger_reginit(ci->i2c);
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt_parse_pdata(struct rt5036_charger_info *ci,
+                                   struct device *dev)
+{
+       struct rt5036_chg_data *pdata = dev->platform_data;
+
+       if (pdata->te_en)
+               ci->te_en = 1;
+
+       chg_init_regval[4] &= (~RT5036_CHGIPREC_MASK);
+       chg_init_regval[4] |= (pdata->iprec << RT5036_CHGIPREC_SHIFT);
+
+       chg_init_regval[4] &= (~RT5036_CHGIEOC_MASK);
+       chg_init_regval[4] |= pdata->ieoc;
+
+       chg_init_regval[5] &= (~RT5036_CHGVPREC_MASK);
+       chg_init_regval[5] |= pdata->vprec;
+
+       chg_init_regval[6] &= (~RT5036_CHGBATLV_MASK);
+       chg_init_regval[6] |= pdata->batlv;
+
+       chg_init_regval[7] &= (~RT5036_CHGVRECHG_MASK);
+       chg_init_regval[7] |= (pdata->vrechg << RT5036_CHGVRECHG_SHIFT);
+
+       ci->chg_volt = pdata->chg_volt;
+       ci->otg_volt = pdata->otg_volt;
+       ci->acchg_icc = pdata->acchg_icc;
+       ci->usbtachg_icc = pdata->usbtachg_icc;
+       ci->usbchg_icc = pdata->usbchg_icc;
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+       ci->acdet_gpio = pdata->acdet_gpio;
+       ci->usbdet_gpio = pdata->usbdet_gpio;
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+       rt5036_charger_reginit(ci->i2c);
+       RTINFO("\n");
+       return 0;
+}
+
+#ifdef CONFIG_RT_POWER
+static struct platform_device rt_power_dev = {
+       .name = "rt-power",
+       .id = -1,
+};
+#endif /* #ifdef CONFIG_RT_POWER */
+
+#ifdef CONFIG_RT_BATTERY
+static struct platform_device rt_battery_dev = {
+       .name = "rt-battery",
+       .id = -1,
+};
+#endif /* #ifdef CONFIG_RT_BATTERY */
+
+static int rt5036_charger_probe(struct platform_device *pdev)
+{
+       struct rt5036_chip *chip = dev_get_drvdata(pdev->dev.parent);
+       struct rt5036_platform_data *pdata = (pdev->dev.parent)->platform_data;
+#ifdef CONFIG_RT_POWER
+       struct rt_power_data *rt_power_pdata;
+#endif /* #ifdef CONFIG_RT_POWER */
+       struct rt5036_charger_info *ci;
+       bool use_dt = pdev->dev.of_node;
+       int ret = 0;
+
+       ci = devm_kzalloc(&pdev->dev, sizeof(*ci), GFP_KERNEL);
+       if (!ci)
+               return -ENOMEM;
+
+       ci->i2c = chip->i2c;
+       if (use_dt) {
+               rt_parse_dt(ci, &pdev->dev);
+       } else {
+               if (!pdata) {
+                       dev_err(&pdev->dev, "platform data invalid\n");
+                       ret = -EINVAL;
+                       goto out_dev;
+               }
+               pdev->dev.platform_data = pdata->chg_pdata;
+               rt_parse_pdata(ci, &pdev->dev);
+       }
+
+       ci->dev = &pdev->dev;
+       INIT_DELAYED_WORK(&ci->dwork, rt5036_chg_dwork_func);
+
+       platform_set_drvdata(pdev, ci);
+       /*power supply register*/
+       ci->psy.name = rtdef_chg_name;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+       ci->psy.type = POWER_SUPPLY_TYPE_UNKNOWN;
+#else
+       ci->psy.type = -1;
+#endif /* #ifdef (LINUX_VERSION_CODE */
+       ci->psy.supplied_to = rt_charger_supply_list;
+       ci->psy.properties = rt_charger_props;
+       ci->psy.num_properties = ARRAY_SIZE(rt_charger_props);
+       ci->psy.get_property = rt_charger_get_property;
+       ci->psy.set_property = rt_charger_set_property;
+       ret = power_supply_register(&pdev->dev, &ci->psy);
+       if (ret < 0) {
+               dev_err(&pdev->dev,
+                       "couldn't create power supply for rt-charger\n");
+               goto out_dev;
+       }
+#ifdef CONFIG_RT_BATTERY
+       rt_battery_dev.dev.parent = &pdev->dev;
+       ret = platform_device_register(&rt_battery_dev);
+       if (ret < 0)
+               goto out_dev;
+#endif /* #ifdef CONFIG_RT_BATTERY */
+
+#ifdef CONFIG_RT_POWER
+       rt_power_pdata =
+           devm_kzalloc(&pdev->dev, sizeof(*rt_power_pdata), GFP_KERNEL);
+       if (!rt_power_pdata) {
+               ret = -ENOMEM;
+               goto out_psy;
+       }
+       rt_power_pdata->chg_volt = ci->chg_volt;
+       rt_power_pdata->acchg_icc = ci->acchg_icc;
+       rt_power_pdata->usbtachg_icc = ci->usbtachg_icc;
+       rt_power_pdata->usbchg_icc = ci->usbchg_icc;
+
+       rt_power_dev.dev.platform_data = rt_power_pdata;
+       rt_power_dev.dev.parent = &pdev->dev;
+       ret = platform_device_register(&rt_power_dev);
+       if (ret < 0)
+               goto out_psy;
+#endif /* #ifdef CONFIG_RT_POWER */
+
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+       ret = rt5036_acusb_irqinit(ci);
+       if (ret < 0)
+               goto out_all;
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+
+       schedule_delayed_work(&ci->dwork, msecs_to_jiffies(100));
+       chip->chg_info = ci;
+       dev_info(&pdev->dev, "driver successfully loaded\n");
+       return 0;
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+out_all:
+       platform_device_unregister(&rt_power_dev);
+       devm_kfree(&pdev->dev, rt_power_pdata);
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+#ifdef CONFIG_RT_POWER
+out_psy:
+#endif /* #ifdef CONFIG_RT_POEWR */
+#ifdef CONFIG_RT_BATTERY
+       platform_device_unregister(&rt_battery_dev);
+#endif /* #ifdef CONFIG_RT_BATTERY */
+       power_supply_unregister(&ci->psy);
+out_dev:
+       return ret;
+}
+
+static int rt5036_charger_remove(struct platform_device *pdev)
+{
+       struct rt5036_charger_info *ci = platform_get_drvdata(pdev);
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+       rt5036_acusb_irqdeinit(ci);
+#endif /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+#ifdef CONFIG_RT_POWER
+       platform_device_unregister(&rt_power_dev);
+#endif /* #ifdef CONFIG_RT_POWER */
+#ifdef CONFIG_RT_BATTERY
+       platform_device_unregister(&rt_battery_dev);
+#endif /* #ifdef CONFIG_RT_BATTERY */
+       power_supply_unregister(&ci->psy);
+       return 0;
+}
+
+static const struct of_device_id rt_match_table[] = {
+       {.compatible = "rt,rt5036-charger",},
+       {},
+};
+
+static struct platform_driver rt5036_charger_driver = {
+       .driver = {
+                  .name = RT5036_DEV_NAME "-charger",
+                  .owner = THIS_MODULE,
+                  .of_match_table = rt_match_table,
+                  },
+       .probe = rt5036_charger_probe,
+       .remove = rt5036_charger_remove,
+};
+
+static int __init rt5036_charger_init(void)
+{
+       return platform_driver_register(&rt5036_charger_driver);
+}
+subsys_initcall(rt5036_charger_init);
+
+static void __exit rt5036_charger_exit(void)
+{
+       platform_driver_unregister(&rt5036_charger_driver);
+}
+module_exit(rt5036_charger_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("CY Huang <cy_huang@richtek.com");
+MODULE_DESCRIPTION("Charger driver for RT5036");
+MODULE_ALIAS("platform:" RT5036_DEV_NAME "-charger");
+MODULE_VERSION(RT5036_DRV_VER);

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 13e1a2f433c7012116025322d8e426e7b5d5de27..0e3d77db3a5dc80bb5b658831c4083ccd6f43512 100755 (executable)
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -269,6 +269,12 @@ config REGULATOR_RT5025
        help
          This driver supports voltage regulator in RT5025 PMIC chips.
 
+config REGULATOR_RT5036
+       bool "RT5036 regulator support"
+       depends on MFD_RT5036
+       help
+         This driver support voltage regulator in Richtek RT5036.
+
 config ROCKCHIP_PWM_REGULATOR
        tristate "rockchip pwm voltage regulator for discrete dcdc or ldo"
        help

diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 153030939736b3498e1337db500071746ae41d03..efdfb9b86d34495ec20ffa4f4c91393296f434a2 100755 (executable)
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
 obj-$(CONFIG_REGULATOR_SYR82X) += syr82x.o
 obj-$(CONFIG_REGULATOR_RICOH619) += ricoh619-regulator.o
 obj-$(CONFIG_REGULATOR_RT5025) += rt5025-regulator.o
+obj-$(CONFIG_REGULATOR_RT5036) += rt5036-regulator.o
 
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip_io_vol_domain.o
 

diff --git a/drivers/regulator/rt5036-regulator.c b/drivers/regulator/rt5036-regulator.c
new file mode 100644 (file)
index 0000000..28bd28e
--- /dev/null
+++ b/drivers/regulator/rt5036-regulator.c
@@ -0,0 +1,665 @@
+/*
+ *  drivers/regulator/rt5036-regulator.c
+ *  Driver for Richtek RT5036 PMIC Regulator
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/version.h>
+#ifdef CONFIG_OF
+#include <linux/regulator/of_regulator.h>
+#endif /* #ifdef CONFIG_OF */
+
+#include <linux/mfd/rt5036/rt5036.h>
+#include <linux/regulator/rt5036-regulator.h>
+
+struct rt5036_regulator_info {
+       struct regulator_desc desc;
+       struct regulator_dev *regulator;
+       struct i2c_client *i2c;
+       const unsigned int *vol_output_list;
+       const int vol_output_size;
+       int min_uV;
+       int max_uV;
+       unsigned char nvol_reg;
+       unsigned char nvol_shift;
+       unsigned char nvol_mask;
+       unsigned char nenable_reg;
+       unsigned char nenable_bit;
+       unsigned char nmode_reg;
+       unsigned char nmode_bit;
+       unsigned char nramp_reg;
+       unsigned char nramp_bit;
+       unsigned char nramp_shift;
+       unsigned char svol_reg;
+       unsigned char svol_shift;
+       unsigned char svol_mask;
+       unsigned char senable_reg;
+       unsigned char senable_bit;
+       unsigned char smode_reg;
+       unsigned char smode_bit;
+       unsigned char sramp_reg;
+       unsigned char sramp_bit;
+       unsigned char sramp_shift;
+};
+
+/*For DCDC1~4 and LDO1~4 and LSW1~2*/
+static const unsigned int rt5036_vol_output_list[] = {
+       /*0~7 */
+       800 * 1000, 825 * 1000, 850 * 1000, 875 * 1000, 900 * 1000, 925 * 1000,
+           950 * 1000, 975 * 1000,
+       /*8~15 */
+       1000 * 1000, 1025 * 1000, 1050 * 1000, 1075 * 1000, 1100 * 1000,
+           1125 * 1000, 1150 * 1000, 1175 * 1000,
+       /*16~23 */
+       1200 * 1000, 1225 * 1000, 1250 * 1000, 1275 * 1000, 1300 * 1000,
+           1325 * 1000, 1350 * 1000, 1375 * 1000,
+       /*24~31 */
+       1400 * 1000, 1425 * 1000, 1450 * 1000, 1475 * 1000, 1500 * 1000,
+           1525 * 1000, 1550 * 1000, 1575 * 1000,
+       /*32~39 */
+       1600 * 1000, 1625 * 1000, 1650 * 1000, 1675 * 1000, 1700 * 1000,
+           1725 * 1000, 1750 * 1000, 1775 * 1000,
+       /*40~47 */
+       1800 * 1000, 1825 * 1000, 1850 * 1000, 1875 * 1000, 1900 * 1000,
+           1925 * 1000, 1950 * 1000, 1975 * 1000,
+       /*48~55 */
+       2000 * 1000, 2025 * 1000, 2050 * 1000, 2075 * 1000, 2100 * 1000,
+           2125 * 1000, 2150 * 1000, 2175 * 1000,
+       /*56~63 */
+       2200 * 1000, 2225 * 1000, 2250 * 1000, 2275 * 1000, 2300 * 1000,
+           2325 * 1000, 2350 * 1000, 2375 * 1000,
+       /*64~71 */
+       2400 * 1000, 2425 * 1000, 2450 * 1000, 2475 * 1000, 2500 * 1000,
+           2525 * 1000, 2550 * 1000, 2575 * 1000,
+       /*72~79 */
+       2600 * 1000, 2625 * 1000, 2650 * 1000, 2675 * 1000, 2700 * 1000,
+           2725 * 1000, 2750 * 1000, 2775 * 1000,
+       /*80~87 */
+       2800 * 1000, 2825 * 1000, 2850 * 1000, 2875 * 1000, 2900 * 1000,
+           2925 * 1000, 2950 * 1000, 2975 * 1000,
+       /*88~95 */
+       3000 * 1000, 3025 * 1000, 3050 * 1000, 3075 * 1000, 3100 * 1000,
+           3125 * 1000, 3150 * 1000, 3175 * 1000,
+       /*96~103 */
+       3200 * 1000, 3225 * 1000, 3250 * 1000, 3275 * 1000, 3300 * 1000,
+           3300 * 1000, 3300 * 1000, 3300 * 1000,
+       /*104~111 */
+       3300 * 1000, 3300 * 1000, 3300 * 1000, 3300 * 1000, 3300 * 1000,
+           3300 * 1000, 3300 * 1000, 3300 * 1000,
+       /*112~119 */
+       3300 * 1000, 3300 * 1000, 3300 * 1000, 3300 * 1000, 3300 * 1000,
+           3300 * 1000, 3300 * 1000, 3300 * 1000,
+       /*120~127 */
+       3300 * 1000, 3300 * 1000, 3300 * 1000, 3300 * 1000, 3300 * 1000,
+           3300 * 1000, 3300 * 1000, 3300 * 1000,
+};
+
+#define rt5036_vol_output_size ARRAY_SIZE(rt5036_vol_output_list)
+
+static inline int check_range(struct rt5036_regulator_info *info,
+                             int min_uV, int max_uV)
+{
+       if (min_uV < info->min_uV || min_uV > info->max_uV)
+               return -EINVAL;
+       return 0;
+}
+
+static int rt5036_list_voltage(struct regulator_dev *rdev, unsigned index)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+
+       return (index >= info->vol_output_size) ?
+           -EINVAL : info->vol_output_list[index];
+}
+
+static int rt5036_find_voltage(struct regulator_dev *rdev,
+                              int min_uV, int max_uV)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       int i = 0;
+       const int count = info->vol_output_size;
+
+       for (i = 0; i < count; i++) {
+               if ((info->vol_output_list[i] >= min_uV)
+                   && (info->vol_output_list[i] <= max_uV))
+                       return i;
+       }
+       return -EINVAL;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
+static int rt5036_set_voltage_sel(struct regulator_dev *rdev, unsigned selector)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       unsigned char data;
+       const int count = info->vol_output_size;
+
+       if (selector > count)
+               return -EINVAL;
+       data = (unsigned char)selector;
+       data <<= info->nvol_shift;
+       return rt5036_assign_bits(info->i2c, info->nvol_reg, info->nvol_mask,
+                                 data);
+}
+
+static int rt5036_get_voltage_sel(struct regulator_dev *rdev)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       int ret;
+
+       ret = rt5036_reg_read(info->i2c, info->nvol_reg);
+       if (ret < 0)
+               return ret;
+       return (ret & info->nvol_mask) >> info->nvol_shift;
+}
+#else
+
+static int rt5036_set_voltage(struct regulator_dev *rdev,
+                             int min_uV, int max_uV, unsigned *selector)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       unsigned char data;
+
+       if (check_range(info, min_uV, max_uV)) {
+               dev_err(&rdev->dev, "invalid voltage range (%d, %d) uV\n",
+                       min_uV, max_uV);
+               return -EINVAL;
+       }
+       data = rt5036_find_voltage(rdev, min_uV, max_uV);
+       data <<= info->nvol_shift;
+       return rt5036_assign_bits(info->i2c, info->nvol_reg, info->nvol_mask,
+                                 data);
+}
+
+static int rt5036_get_voltage(struct regulator_dev *rdev)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       int ret;
+
+       ret = rt5036_reg_read(info->i2c, info->nvol_reg);
+       if (ret < 0)
+               return ret;
+       ret = (ret & info->nvol_mask) >> info->nvol_shift;
+       return rt5036_list_voltage(rdev, ret);
+}
+#endif /* LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,38) */
+
+static int rt5036_enable(struct regulator_dev *rdev)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+
+       return rt5036_set_bits(info->i2c, info->nenable_reg, info->nenable_bit);
+}
+
+static int rt5036_disable(struct regulator_dev *rdev)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+
+       return rt5036_clr_bits(info->i2c, info->nenable_reg, info->nenable_bit);
+}
+
+static int rt5036_is_enabled(struct regulator_dev *rdev)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       int ret;
+
+       ret = rt5036_reg_read(info->i2c, info->nenable_reg);
+       if (ret < 0)
+               return ret;
+       return (ret & info->nenable_bit) ? 1 : 0;
+}
+
+static int rt5036_set_mode(struct regulator_dev *rdev, unsigned int mode)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       int ret;
+
+       switch (mode) {
+       case REGULATOR_MODE_NORMAL:
+               ret =
+                   rt5036_set_bits(info->i2c, info->nmode_reg,
+                                   info->nmode_bit);
+               break;
+       case REGULATOR_MODE_FAST:
+               ret =
+                   rt5036_clr_bits(info->i2c, info->nmode_reg,
+                                   info->nmode_bit);
+               break;
+       default:
+               ret = -EINVAL;
+               break;
+       }
+       return ret;
+}
+
+static unsigned int rt5036_get_mode(struct regulator_dev *rdev)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       unsigned int mode;
+       int data;
+
+       data = rt5036_reg_read(info->i2c, info->nmode_reg);
+       mode =
+           (data & info->nmode_bit) ? REGULATOR_MODE_NORMAL :
+           REGULATOR_MODE_FAST;
+       return mode;
+}
+
+static int rt5036_set_suspend_voltage(struct regulator_dev *rdev, int uV)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       unsigned char data;
+
+       if (check_range(info, uV, uV)) {
+               dev_err(&rdev->dev, "invalid voltage range (%d, %d) uV\n",
+                       uV, uV);
+               return -EINVAL;
+       }
+       data = rt5036_find_voltage(rdev, uV, uV);
+       data <<= info->svol_shift;
+       return rt5036_assign_bits(info->i2c, info->svol_reg, info->svol_mask,
+                                 data);
+}
+
+static int rt5036_set_suspend_enable(struct regulator_dev *rdev)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+
+       return rt5036_set_bits(info->i2c, info->senable_reg, info->senable_bit);
+}
+
+static int rt5036_set_suspend_disable(struct regulator_dev *rdev)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+
+       return rt5036_clr_bits(info->i2c, info->senable_reg, info->senable_bit);
+}
+
+static int rt5036_set_suspend_mode(struct regulator_dev *rdev,
+                                  unsigned int mode)
+{
+       struct rt5036_regulator_info *info = rdev_get_drvdata(rdev);
+       int ret;
+
+       switch (mode) {
+       case REGULATOR_MODE_NORMAL:
+               ret =
+                   rt5036_set_bits(info->i2c, info->smode_reg,
+                                   info->smode_bit);
+               break;
+       case REGULATOR_MODE_FAST:
+               ret =
+                   rt5036_clr_bits(info->i2c, info->smode_reg,
+                                   info->smode_bit);
+               break;
+       default:
+               ret = -EINVAL;
+               break;
+       }
+       return ret;
+}
+
+static struct regulator_ops rt5036_regulator_ops = {
+       .list_voltage = rt5036_list_voltage,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
+       .get_voltage_sel = rt5036_get_voltage_sel,
+       .set_voltage_sel = rt5036_set_voltage_sel,
+#else
+       .set_voltage = rt5036_set_voltage,
+       .get_voltage = rt5036_get_voltage,
+#endif /* LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,38) */
+       .enable = rt5036_enable,
+       .disable = rt5036_disable,
+       .is_enabled = rt5036_is_enabled,
+       .set_mode = rt5036_set_mode,
+       .get_mode = rt5036_get_mode,
+       .set_suspend_voltage = rt5036_set_suspend_voltage,
+       .set_suspend_enable = rt5036_set_suspend_enable,
+       .set_suspend_disable = rt5036_set_suspend_disable,
+       .set_suspend_mode = rt5036_set_suspend_mode,
+};
+
+#define RT5036_VOUT_LIST rt5036_vol_output_list
+#define RT5036_VOUT_SIZE rt5036_vol_output_size
+
+#define RT5036_DCDC(_id, min, max)                             \
+{                                                              \
+       .desc   = {                                             \
+               .name   = "rt5036-dcdc" #_id,                   \
+               .n_voltages = RT5036_VOUT_SIZE,                 \
+               .ops    = &rt5036_regulator_ops,                \
+               .type   = REGULATOR_VOLTAGE,                    \
+               .id     = RT5036_ID_DCDC##_id,                  \
+               .owner  = THIS_MODULE,                          \
+       },                                                      \
+       .vol_output_list = RT5036_VOUT_LIST,                    \
+       .vol_output_size = RT5036_VOUT_SIZE,                    \
+       .min_uV         = min * 1000,                           \
+       .max_uV         = max * 1000,                           \
+       .nvol_reg       = RT5036_REG_BUCKVN##_id,               \
+       .nvol_shift     = RT5036_DCDCVOUT_SHIFT##_id,           \
+       .nvol_mask      = RT5036_DCDCVOUT_MASK##_id,            \
+       .nenable_reg    = RT5036_REG_BUCKLDONEN,                \
+       .nenable_bit    = RT5036_DCDCEN_MASK##_id,              \
+       .nmode_reg      = RT5036_REG_BUCKVRCNEN,                \
+       .nmode_bit      = RT5036_DCDCMODE_MASK##_id,            \
+       .nramp_reg      = RT5036_REG_BUCKVRCN,                  \
+       .nramp_bit      = RT5036_DCDCRAMP_MASK##_id,            \
+       .nramp_shift    = RT5036_DCDCRAMP_SHIFT##_id,           \
+       .svol_reg       = RT5036_REG_BUCKVS##_id,               \
+       .svol_shift     = RT5036_DCDCVOUT_SHIFT##_id,           \
+       .svol_mask      = RT5036_DCDCVOUT_MASK##_id,            \
+       .senable_reg    = RT5036_REG_BUCKLDOSEN,                \
+       .senable_bit    = RT5036_DCDCEN_MASK##_id,              \
+       .smode_reg      = RT5036_REG_BUCKVRCSEN,                \
+       .smode_bit      = RT5036_DCDCMODE_MASK##_id,            \
+       .sramp_reg      = RT5036_REG_BUCKVRCS,                  \
+       .sramp_bit      = RT5036_DCDCRAMP_MASK##_id,            \
+       .sramp_shift    = RT5036_DCDCRAMP_SHIFT##_id,           \
+}
+
+#define RT5036_LDO(_id, min, max)                              \
+{                                                              \
+       .desc   = {                                             \
+               .name   = "rt5036-ldo" #_id,                    \
+               .n_voltages = RT5036_VOUT_SIZE,                 \
+               .ops    = &rt5036_regulator_ops,                \
+               .type   = REGULATOR_VOLTAGE,                    \
+               .id     = RT5036_ID_LDO##_id,                   \
+               .owner  = THIS_MODULE,                          \
+       },                                                      \
+       .vol_output_list = RT5036_VOUT_LIST,                    \
+       .vol_output_size = RT5036_VOUT_SIZE,                    \
+       .min_uV         = min * 1000,                           \
+       .max_uV         = max * 1000,                           \
+       .nvol_reg       = RT5036_REG_LDOVN##_id,                \
+       .nvol_shift     = RT5036_LDOVOUT_SHIFT##_id,            \
+       .nvol_mask      = RT5036_LDOVOUT_MASK##_id,             \
+       .nenable_reg    = RT5036_REG_BUCKLDONEN,                \
+       .nenable_bit    = RT5036_LDOEN_MASK##_id,               \
+       .nmode_reg      = RT5036_REG_LDOVRCNEN,                 \
+       .nmode_bit      = RT5036_LDOMODE_MASK##_id,             \
+       .nramp_reg      = RT5036_REG_LDOVRCN,                   \
+       .nramp_bit      = RT5036_LDORAMP_MASK##_id,             \
+       .nramp_shift    = RT5036_LDORAMP_SHIFT##_id,            \
+       .svol_reg       = RT5036_REG_LDOVS##_id,                \
+       .svol_shift     = RT5036_LDOVOUT_SHIFT##_id,            \
+       .svol_mask      = RT5036_LDOVOUT_MASK##_id,             \
+       .senable_reg    = RT5036_REG_BUCKLDOSEN,                \
+       .senable_bit    = RT5036_LDOEN_MASK##_id,               \
+       .smode_reg      = RT5036_REG_LDOVRCSEN,                 \
+       .smode_bit      = RT5036_LDOMODE_MASK##_id,             \
+       .sramp_reg      = RT5036_REG_LDOVRCS,                   \
+       .sramp_bit      = RT5036_LDORAMP_MASK##_id,             \
+       .sramp_shift    = RT5036_LDORAMP_SHIFT##_id,            \
+}
+
+#define RT5036_LSW(_id, min, max)                              \
+{                                                              \
+       .desc   = {                                             \
+               .name   = "rt5036-lsw" #_id,                    \
+               .n_voltages = RT5036_VOUT_SIZE,                 \
+               .ops    = &rt5036_regulator_ops,                \
+               .type   = REGULATOR_VOLTAGE,                    \
+               .id     = RT5036_ID_LSW##_id,                   \
+               .owner  = THIS_MODULE,                          \
+       },                                                      \
+       .vol_output_list = RT5036_VOUT_LIST,                    \
+       .vol_output_size = RT5036_VOUT_SIZE,                    \
+       .min_uV         = min * 1000,                           \
+       .max_uV         = max * 1000,                           \
+       .nvol_reg       = RT5036_REG_LSWVN##_id,                \
+       .nvol_shift     = RT5036_LSWVOUT_SHIFT##_id,            \
+       .nvol_mask      = RT5036_LSWVOUT_MASK##_id,             \
+       .nenable_reg    = RT5036_REG_LSWEN,                     \
+       .nenable_bit    = RT5036_LSWNEN_MASK##_id,              \
+       .nmode_reg      = RT5036_REG_LSWVRCEN,                  \
+       .nmode_bit      = RT5036_LSWNMODE_MASK##_id,            \
+       .nramp_reg      = RT5036_REG_LSWVRC,                    \
+       .nramp_bit      = RT5036_LSWNRAMP_MASK##_id,            \
+       .nramp_shift    = RT5036_LSWNRAMP_SHIFT##_id,           \
+       .svol_reg       = RT5036_REG_LSWVS##_id,                \
+       .svol_shift     = RT5036_LSWVOUT_SHIFT##_id,            \
+       .svol_mask      = RT5036_LSWVOUT_MASK##_id,             \
+       .senable_reg    = RT5036_REG_LSWEN,                     \
+       .senable_bit    = RT5036_LSWSEN_MASK##_id,              \
+       .smode_reg      = RT5036_REG_LSWVRCEN,                  \
+       .smode_bit      = RT5036_LSWSMODE_MASK##_id,            \
+       .sramp_reg      = RT5036_REG_LSWVRC,                    \
+       .sramp_bit      = RT5036_LSWSRAMP_MASK##_id,            \
+       .sramp_shift    = RT5036_LSWSRAMP_SHIFT##_id,           \
+}
+
+static struct rt5036_regulator_info rt5036_regulator_info[] = {
+       RT5036_DCDC(1, 800, 3300),
+       RT5036_DCDC(2, 800, 3300),
+       RT5036_DCDC(3, 800, 3300),
+       RT5036_DCDC(4, 800, 3300),
+       RT5036_LDO(1, 800, 3300),
+       RT5036_LDO(2, 800, 3300),
+       RT5036_LDO(3, 800, 3300),
+       RT5036_LDO(4, 800, 3300),
+       RT5036_LSW(1, 800, 3300),
+       RT5036_LSW(2, 800, 3300),
+};
+
+static struct rt5036_regulator_info *find_regulator_info(int id)
+{
+       struct rt5036_regulator_info *ri;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(rt5036_regulator_info); i++) {
+               ri = &rt5036_regulator_info[i];
+               if (ri->desc.id == id)
+                       return ri;
+       }
+       return NULL;
+}
+
+inline struct regulator_dev *rt5036_regulator_register(struct regulator_desc
+                                                      *regulator_desc,
+                                                      struct device *dev,
+                                                      struct
+                                                      regulator_init_data
+                                                      *init_data,
+                                                      void *driver_data)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+       struct regulator_config config = {
+               .dev = dev,
+               .init_data = init_data,
+               .driver_data = driver_data,
+               .of_node = dev->of_node,
+       };
+       return regulator_register(regulator_desc, &config);
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 37))
+       return regulator_register(regulator_desc, dev, init_data, driver_data,
+                                 dev->of_node);
+#else
+       return regulator_register(regulator_desc, dev, init_data, driver_data);
+#endif /* LINUX_VERSION_CODE>=KERNEL_VERSION(3,5,0)) */
+}
+
+static struct regulator_init_data *rt_parse_dt(struct
+                                                        rt5036_regulator_info
+                                                        *ri,
+                                                        struct device *dev)
+{
+       struct regulator_init_data *init_data = NULL;
+#ifdef CONFIG_OF
+       struct device_node *np = dev->of_node;
+       int rc;
+       u32 tmp;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+       init_data = of_get_regulator_init_data(dev, dev->of_node);
+#else
+       init_data = of_get_regulator_init_data(dev);
+#endif /* #if (LINUX_KERNEL_VERSION >= KERNEL_VERSION(3,3,0)) */
+
+       if (init_data) {
+               init_data->supply_regulator = (char *)of_get_property(np,
+                                                       "supply-regulator",
+                                                       NULL);
+               rc = of_property_read_u32(np, "rt,standby_vol", &tmp);
+               if (rc)
+                       dev_info(dev, "no standby voltage specified\n");
+               else
+                       init_data->constraints.state_standby.uV = tmp;
+               if (of_property_read_bool(np, "rt,standby_enabled")) {
+                       init_data->constraints.state_standby.enabled = 1;
+                       init_data->constraints.initial_state =
+                           PM_SUSPEND_STANDBY;
+               }
+               if (of_property_read_bool(np, "rt,standby_disabled")) {
+                       init_data->constraints.state_standby.disabled = 1;
+                       init_data->constraints.initial_state =
+                           PM_SUSPEND_STANDBY;
+               }
+       }
+
+       rc = of_property_read_u32(np, "rt,nramp_sel", &tmp);
+       if (rc) {
+               dev_info(dev, "no nramp_sel property, use default value\n");
+       } else {
+               if (tmp > RT5036_RAMP_MAX)
+                       tmp = RT5036_RAMP_MAX;
+               rt5036_assign_bits(ri->i2c, ri->nramp_reg, ri->nramp_bit,
+                                  tmp << ri->nramp_shift);
+       }
+
+       rc = of_property_read_u32(np, "rt,sramp_sel", &tmp);
+       if (rc) {
+               dev_info(dev, "no sramp_sel property, use default value\n");
+       } else {
+               if (tmp > RT5036_RAMP_MAX)
+                       tmp = RT5036_RAMP_MAX;
+               rt5036_assign_bits(ri->i2c, ri->sramp_reg, ri->sramp_bit,
+                                  tmp << ri->sramp_shift);
+       }
+
+       if (of_property_read_bool(np, "rt,allow_mode_mask")) {
+               init_data->constraints.valid_modes_mask |=
+                   (REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL);
+               init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_MODE;
+       }
+#endif /* #ifdef CONFIG_OF */
+       return init_data;
+}
+
+static int rt5036_regulator_probe(struct platform_device *pdev)
+{
+       struct rt5036_chip *chip = dev_get_drvdata(pdev->dev.parent);
+       struct rt5036_platform_data *pdata = (pdev->dev.parent)->platform_data;
+       struct rt5036_regulator_info *ri;
+       struct rt5036_regulator_ramp *ramp;
+       struct regulator_dev *rdev;
+       struct regulator_init_data *init_data;
+       bool use_dt = pdev->dev.of_node;
+
+       ri = find_regulator_info(pdev->id);
+       if (ri == NULL) {
+               dev_err(&pdev->dev, "invalid regulator ID specified\n");
+               return -EINVAL;
+       }
+
+       ri->i2c = chip->i2c;
+       if (use_dt) {
+               init_data = rt_parse_dt(ri, &pdev->dev);
+       } else {
+               if (!pdata)
+                       return -EINVAL;
+               init_data = pdata->regulator[pdev->id];
+               ramp = init_data ? init_data->driver_data : NULL;
+               if (ramp) {
+                       rt5036_assign_bits(ri->i2c, ri->nramp_reg,
+                                          ri->nramp_bit,
+                                          ramp->nramp_sel << ri->nramp_shift);
+                       rt5036_assign_bits(ri->i2c, ri->sramp_reg,
+                                          ri->sramp_bit,
+                                          ramp->sramp_sel << ri->sramp_shift);
+               }
+       }
+
+       if (!init_data) {
+               dev_err(&pdev->dev, "no initializing data\n");
+               return -EINVAL;
+       }
+
+       rdev = rt5036_regulator_register(&ri->desc, &pdev->dev, init_data, ri);
+       if (IS_ERR(rdev)) {
+               dev_err(&pdev->dev, "failed to register regulator %s\n",
+                       ri->desc.name);
+               return PTR_ERR(rdev);
+       }
+
+       platform_set_drvdata(pdev, rdev);
+       /*dev_info(&pdev->dev, "regulator successfully registered\n");*/
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt5036_regulator_remove(struct platform_device *pdev)
+{
+       struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+       regulator_unregister(rdev);
+       RTINFO("\n");
+       return 0;
+}
+
+static const struct of_device_id rt_match_table[] = {
+       {.compatible = "rt,rt5036-dcdc1",},
+       {.compatible = "rt,rt5036-dcdc2",},
+       {.compatible = "rt,rt5036-dcdc3",},
+       {.compatible = "rt,rt5036-dcdc4",},
+       {.compatible = "rt,rt5036-ldo1",},
+       {.compatible = "rt,rt5036-ldo2",},
+       {.compatible = "rt,rt5036-ldo3",},
+       {.compatible = "rt,rt5036-ldo4",},
+       {.compatible = "rt,rt5036-lsw1",},
+       {.compatible = "rt,rt5036-lsw2",},
+       {},
+};
+
+static struct platform_driver rt5036_regulator_driver = {
+       .driver = {
+                  .name = RT5036_DEV_NAME "-regulator",
+                  .owner = THIS_MODULE,
+                  .of_match_table = rt_match_table,
+                  },
+       .probe = rt5036_regulator_probe,
+       .remove = rt5036_regulator_remove,
+};
+
+static int __init rt5036_regulator_init(void)
+{
+       return platform_driver_register(&rt5036_regulator_driver);
+}
+subsys_initcall(rt5036_regulator_init);
+
+static void __exit rt5036_regulator_exit(void)
+{
+       platform_driver_unregister(&rt5036_regulator_driver);
+}
+module_exit(rt5036_regulator_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("CY Huang <cy_huang@richtek.com");
+MODULE_DESCRIPTION("Regulator driver for RT5036");
+MODULE_ALIAS("platform:" RT5036_DEV_NAME "-regulator");
+MODULE_VERSION(RT5036_DRV_VER);

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 9eb29e7582068036cfde3ccd2952b2c0154e863f..87d6c4f6911e72feec0de47912bb7be15d750f21 100755 (executable)
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -435,6 +435,13 @@ config  RK818_RTC
        help
                enable rk818 rtc for system
 
+config RTC_RT5036
+       bool "RT5036 RTC driver support"
+       depends on MFD_RT5036
+       default n
+       help
+         Say Y here if you want to support Richtek RT5036 RTC.
+
 config RTC_DRV_TPS80031
        tristate "TI TPS80031/TPS80032 RTC driver"
        depends on MFD_TPS80031

diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 00df76aaabd9b75c43815866487f4fcc450b5ab3..026c58c6b1b38182090b4ede46dd250b984f70ce 100755 (executable)
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -129,6 +129,7 @@ obj-$(CONFIG_RTC_DRV_VT8500)        += rtc-vt8500.o
 obj-$(CONFIG_RTC_DRV_WM831X)   += rtc-wm831x.o
 obj-$(CONFIG_RK808_RTC)  += rtc-rk808.o
 obj-$(CONFIG_RK818_RTC)  += rtc-rk818.o
+obj-$(CONFIG_RTC_RT5036)       += rtc-rt5036.o
 obj-$(CONFIG_RTC_DRV_WM8350)   += rtc-wm8350.o
 obj-$(CONFIG_RTC_DRV_X1205)    += rtc-x1205.o
 obj-$(CONFIG_RTC_DRV_RC5T619)  += rtc-ricoh619.o

diff --git a/drivers/rtc/rtc-rt5036.c b/drivers/rtc/rtc-rt5036.c
new file mode 100755 (executable)
index 0000000..9755820
--- /dev/null
+++ b/drivers/rtc/rtc-rt5036.c
@@ -0,0 +1,336 @@
+/*
+ *  drivers/rtc/rt5036-rtc.c
+ *  Driver for Richtek RT5036 PMIC RTC driver
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/of.h>
+
+#include <linux/mfd/rt5036/rt5036.h>
+#include <linux/rtc/rtc-rt5036.h>
+
+static unsigned char rtc_init_regval[] = {
+       0x1,                    /*REG 0x97*/
+       0x3,                    /*REG 0xA5*/
+};
+
+static int rt5036_read_time(struct device *dev, struct rtc_time *tm)
+{
+       struct rt5036_rtc_info *ri = dev_get_drvdata(dev);
+       unsigned char val[6];
+       int rc;
+
+       RTINFO("\n");
+       rc = rt5036_reg_block_read(ri->i2c, RT5036_REG_RTCTSEC, ARRAY_SIZE(val),
+                                  val);
+       if (rc < 0) {
+               dev_err(dev, "reading rtc time io error\n");
+       } else {
+               tm->tm_sec = val[0] & RT5036_RTC_SECMASK;
+               tm->tm_min = val[1] & RT5036_RTC_MINMASK;
+               tm->tm_hour = val[2] & RT5036_RTC_HOURMASK;
+               tm->tm_year = (val[3] & RT5036_RTC_YEARMASK) + 100;
+               tm->tm_mon = (val[4] & RT5036_RTC_MONMASK) - 1;
+               tm->tm_mday = val[5] & RT5036_RTC_DAYMASK;
+               RTINFO("%04d:%02d:%02d, %02d:%02d:%02d\n", tm->tm_year + 1900,
+                      tm->tm_mon + 1, tm->tm_mday, tm->tm_hour, tm->tm_min,
+                      tm->tm_sec);
+               rc = rtc_valid_tm(tm);
+               if (rc < 0) {
+                       dev_err(dev, "not invalid time reading from RT5036\n");
+                       return -EINVAL;
+               }
+       }
+       return rc;
+}
+
+static int rt5036_set_time(struct device *dev, struct rtc_time *tm)
+{
+       struct rt5036_rtc_info *ri = dev_get_drvdata(dev);
+       unsigned char val[6];
+       int rc;
+
+       RTINFO("\n");
+       rc = rt5036_reg_block_read(ri->i2c, RT5036_REG_RTCTSEC, ARRAY_SIZE(val),
+                                  val);
+       if (rc < 0) {
+               dev_err(dev, "reading rtc time io error\n");
+       } else {
+               val[0] &= ~RT5036_RTC_SECMASK;
+               val[0] |= (tm->tm_sec & RT5036_RTC_SECMASK);
+               val[1] &= ~RT5036_RTC_MINMASK;
+               val[1] |= (tm->tm_min & RT5036_RTC_MINMASK);
+               val[2] &= ~RT5036_RTC_HOURMASK;
+               val[2] |= (tm->tm_hour & RT5036_RTC_HOURMASK);
+               val[3] &= ~RT5036_RTC_YEARMASK;
+               val[3] |= ((tm->tm_year - 100) & RT5036_RTC_YEARMASK);
+               val[4] &= ~RT5036_RTC_MONMASK;
+               val[4] |= ((tm->tm_mon + 1) & RT5036_RTC_MONMASK);
+               val[5] &= ~RT5036_RTC_DAYMASK;
+               val[5] |= (tm->tm_mday & RT5036_RTC_DAYMASK);
+               val[5] &= ~RT5036_RTC_WEEKMASK;
+               val[5] |=
+                   ((tm->
+                     tm_wday & RT5036_RTC_WEEKMASK) << RT5036_RTC_WEEKSHIFT);
+               RTINFO("%04d:%02d:%02d, %02d:%02d:%02d\n", tm->tm_year + 1900,
+                      tm->tm_mon + 1, tm->tm_mday, tm->tm_hour, tm->tm_min,
+                      tm->tm_sec);
+
+               if (tm->tm_year < 100)
+                       return -EINVAL;
+
+               rc = rt5036_reg_block_write(ri->i2c, RT5036_REG_RTCTSEC,
+                                           ARRAY_SIZE(val), val);
+               if (rc < 0) {
+                       dev_err(dev, "writing rtc time io error\n");
+                       return rc;
+               }
+       }
+       return rc;
+}
+
+static int rt5036_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
+{
+       struct rt5036_rtc_info *ri = dev_get_drvdata(dev);
+       struct rtc_time *tm = &(alarm->time);
+       unsigned char val[6];
+       int rc;
+
+       RTINFO("\n");
+       rc = rt5036_reg_block_read(ri->i2c, RT5036_REG_RTCASEC, ARRAY_SIZE(val),
+                                  val);
+       if (rc < 0) {
+               dev_err(dev, "reading alarm time io error\n");
+       } else {
+               tm->tm_sec = val[0] & RT5036_RTC_SECMASK;
+               tm->tm_min = val[1] & RT5036_RTC_MINMASK;
+               tm->tm_hour = val[2] & RT5036_RTC_HOURMASK;
+               tm->tm_year = (val[3] & RT5036_RTC_YEARMASK) + 100;
+               tm->tm_mon = (val[4] & RT5036_RTC_MONMASK) - 1;
+               tm->tm_mday = val[5] & RT5036_RTC_DAYMASK;
+               RTINFO("%04d_%02d_%02d, %02d:%02d:%02d\n", tm->tm_year + 1900,
+                      tm->tm_mon + 1, tm->tm_mday, tm->tm_hour, tm->tm_min,
+                      tm->tm_sec);
+               rc = rtc_valid_tm(tm);
+               if (rc < 0) {
+                       dev_err(dev, "not invalid alarm reading from RT5036\n");
+                       return -EINVAL;
+               }
+       }
+       return rc;
+}
+
+static int rt5036_alarm_irq_enable(struct device *dev, unsigned int enabled);
+
+static int rt5036_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
+{
+       struct rt5036_rtc_info *ri = dev_get_drvdata(dev);
+       struct rtc_time *tm = &alarm->time;
+       unsigned char val[6];
+       int rc;
+
+       RTINFO("\n");
+       rt5036_alarm_irq_enable(ri->dev, 0);
+       rc = rt5036_reg_block_read(ri->i2c, RT5036_REG_RTCASEC, ARRAY_SIZE(val),
+                                  val);
+       if (rc < 0) {
+               dev_err(dev, "reading rtc time io error\n");
+       } else {
+               val[0] &= ~RT5036_RTC_SECMASK;
+               val[0] |= (tm->tm_sec & RT5036_RTC_SECMASK);
+               val[1] &= ~RT5036_RTC_MINMASK;
+               val[1] |= (tm->tm_min & RT5036_RTC_MINMASK);
+               val[2] &= ~RT5036_RTC_HOURMASK;
+               val[2] |= (tm->tm_hour & RT5036_RTC_HOURMASK);
+               val[3] &= ~RT5036_RTC_YEARMASK;
+               val[3] |= ((tm->tm_year - 100) & RT5036_RTC_YEARMASK);
+               val[4] &= ~RT5036_RTC_MONMASK;
+               val[4] |= ((tm->tm_mon + 1) & RT5036_RTC_MONMASK);
+               val[5] &= ~RT5036_RTC_DAYMASK;
+               val[5] |= (tm->tm_mday & RT5036_RTC_DAYMASK);
+               RTINFO("%04d:%02d:%02d, %02d:%02d:%02d\n", tm->tm_year + 1900,
+                      tm->tm_mon + 1, tm->tm_mday, tm->tm_hour, tm->tm_min,
+                      tm->tm_sec);
+
+               if (tm->tm_year < 100)
+                       return -EINVAL;
+
+               rc = rt5036_reg_block_write(ri->i2c, RT5036_REG_RTCASEC,
+                                           ARRAY_SIZE(val), val);
+               if (rc < 0) {
+                       dev_err(dev, "writing alarm time io error\n");
+                       return rc;
+               }
+       }
+       rt5036_alarm_irq_enable(ri->dev, alarm->enabled);
+       return rc;
+}
+
+static int rt5036_alarm_irq_enable(struct device *dev, unsigned int enabled)
+{
+       struct rt5036_rtc_info *ri = dev_get_drvdata(dev);
+
+       RTINFO("enable=%d\n", enabled);
+       if (enabled) {
+               rt5036_clr_bits(ri->i2c, RT5036_REG_STBWACKIRQMASK,
+                               RT5036_RTCAIRQ_MASK);
+               rt5036_set_bits(ri->i2c, RT5036_REG_STBMODE,
+                               RT5036_RTCAEN_MASK);
+       } else {
+               rt5036_clr_bits(ri->i2c, RT5036_REG_STBMODE,
+                               RT5036_RTCAEN_MASK);
+               rt5036_set_bits(ri->i2c, RT5036_REG_STBWACKIRQMASK,
+                               RT5036_RTCAIRQ_MASK);
+       }
+       return 0;
+}
+
+static const struct rtc_class_ops rt5036_rtc_ops = {
+       .read_time = rt5036_read_time,
+       .set_time = rt5036_set_time,
+       .read_alarm = rt5036_read_alarm,
+       .set_alarm = rt5036_set_alarm,
+       .alarm_irq_enable = rt5036_alarm_irq_enable,
+};
+
+static void rt5036_general_irq_handler(void *info, int eventno)
+{
+       struct rt5036_rtc_info *ri = info;
+
+       dev_info(ri->dev, "eventno=%02d\n", eventno);
+       switch (eventno) {
+       case RTCEVENT_CAIRQ:
+               rt5036_alarm_irq_enable(ri->dev, 0);
+               break;
+       default:
+               break;
+       }
+}
+
+static rt_irq_handler rt_rtcirq_handler[RTCEVENT_MAX] = {
+       [RTCEVENT_CAIRQ] = rt5036_general_irq_handler,
+       [RTCEVENT_CDIRQ] = rt5036_general_irq_handler,
+};
+
+void rt5036_rtc_irq_handler(struct rt5036_rtc_info *ri, unsigned int irqevent)
+{
+       int i;
+
+       for (i = 0; i < RTCEVENT_MAX; i++) {
+               if ((irqevent & (1 << i)) && rt_rtcirq_handler[i])
+                       rt_rtcirq_handler[i] (ri, i);
+       }
+}
+EXPORT_SYMBOL(rt5036_rtc_irq_handler);
+
+static int rt5036_rtc_reginit(struct i2c_client *i2c)
+{
+       rt5036_reg_write(i2c, RT5036_REG_STBMODE, rtc_init_regval[0]);
+       rt5036_reg_write(i2c, RT5036_REG_STBWACKIRQMASK, rtc_init_regval[1]);
+       /*always clear at the fist time*/
+       rt5036_reg_read(i2c, RT5036_REG_STBWACKIRQ);
+       return 0;
+}
+
+static int rt_parse_dt(struct rt5036_rtc_info *ri, struct device *dev)
+{
+       rt5036_rtc_reginit(ri->i2c);
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt_parse_pdata(struct rt5036_rtc_info *ri,
+                                   struct device *dev)
+{
+       rt5036_rtc_reginit(ri->i2c);
+       RTINFO("\n");
+       return 0;
+}
+
+static int rt5036_rtc_probe(struct platform_device *pdev)
+{
+       struct rt5036_chip *chip = dev_get_drvdata(pdev->dev.parent);
+       struct rt5036_rtc_info *ri;
+       bool use_dt = pdev->dev.of_node;
+
+       ri = devm_kzalloc(&pdev->dev, sizeof(*ri), GFP_KERNEL);
+       if (!ri)
+               return -ENOMEM;
+
+       ri->i2c = chip->i2c;
+       if (use_dt)
+               rt_parse_dt(ri, &pdev->dev);
+       else
+               rt_parse_pdata(ri, &pdev->dev);
+
+       ri->dev = &pdev->dev;
+       platform_set_drvdata(pdev, ri);
+
+       ri->rtc = rtc_device_register("rt5036-rtc", &pdev->dev,
+                                     &rt5036_rtc_ops, THIS_MODULE);
+       if (IS_ERR(ri->rtc)) {
+               dev_err(&pdev->dev, "rtc device register failed\n");
+               goto out_dev;
+       }
+       chip->rtc_info = ri;
+       device_init_wakeup(&pdev->dev, 1);
+       dev_info(&pdev->dev, "driver successfully loaded\n");
+       return 0;
+out_dev:
+       return -EINVAL;
+}
+
+static int rt5036_rtc_remove(struct platform_device *pdev)
+{
+       struct rt5036_rtc_info *ri = platform_get_drvdata(pdev);
+
+       rtc_device_unregister(ri->rtc);
+       return 0;
+}
+
+static const struct of_device_id rt_match_table[] = {
+       {.compatible = "rt,rt5036-rtc",},
+       {},
+};
+
+static struct platform_driver rt5036_rtc_driver = {
+       .driver = {
+                  .name = RT5036_DEV_NAME "-rtc",
+                  .owner = THIS_MODULE,
+                  .of_match_table = rt_match_table,
+                  },
+       .probe = rt5036_rtc_probe,
+       .remove = rt5036_rtc_remove,
+};
+
+static int __init rt5036_rtc_init(void)
+{
+       return platform_driver_register(&rt5036_rtc_driver);
+}
+subsys_initcall(rt5036_rtc_init);
+
+static void __exit rt5036_rtc_exit(void)
+{
+       platform_driver_unregister(&rt5036_rtc_driver);
+}
+module_exit(rt5036_rtc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("CY Huang <cy_huang@richtek.com");
+MODULE_DESCRIPTION("RTC driver for RT5036");
+MODULE_ALIAS("platform:" RT5036_DEV_NAME "-rtc");
+MODULE_VERSION(RT5036_DRV_VER);

diff --git a/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.c b/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.c
index ba701686eb9c70171c81bd0eb9a4487ccc0be69f..bffef81b3bbf8ccdd6833557127566433fa4c9f2 100755 (executable)
--- a/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.c
+++ b/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.c
@@ -252,18 +252,28 @@ static const char coeff_csc[][24] = {
            Y   = 0.504G   + 0.257R + 0.098B + 16
            Cr  = -0.368G + 0.439R - 0.071B + 128*/
        {
-       0x11, 0x29, 0x10, 0x97, 0x01, 0xc1, 0x00, 0x80,
-       0x02, 0x04, 0x01, 0x07, 0x00, 0x64, 0x00, 0x10,
-       0x11, 0x78, 0x01, 0xc1, 0x10, 0x48, 0x00, 0x80},
+       //0x11, 0x78, 0x01, 0xc1, 0x10, 0x48, 0x00, 0x80,
+       //0x02, 0x04, 0x01, 0x07, 0x00, 0x64, 0x00, 0x10,
+       //0x11, 0x29, 0x10, 0x97, 0x01, 0xc1, 0x00, 0x80
+
+       //0x11,0x4b,0x01,0x8a,0x10,0x3f,0x00,0x80,
+       //0x01,0xbb,0x00,0xe2,0x00,0x56,0x00,0x1d,
+       //0x11,0x05,0x10,0x85,0x01,0x8a,0x00,0x80
+
+       0x11,0x5f,0x01,0x82,0x10,0x23,0x00,0x80,
+       0x02,0x1c,0x00,0xa1,0x00,0x36,0x00,0x1e,
+       0x11,0x29,0x10,0x59,0x01,0x82,0x00,0x80
+       },
 
        /*RGB2YUV:709 HD mode:
            Cb = - 0.338G - 0.101R +  0.439B + 128
            Y  =    0.614G + 0.183R +  0.062B + 16
            Cr = - 0.399G + 0.439R  -  0.040B + 128*/
        {
-       0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80,
+       0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
        0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
-       0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80},
+       0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
+       },
        /*RGB[0:255]2RGB[16:235]:
        R' = R x (235-16)/255 + 16;
        G' = G x (235-16)/255 + 16;
@@ -282,7 +292,8 @@ static int rk3036_hdmi_video_csc(struct hdmi *hdmi_drv,
                                                        struct rk_hdmi_device,
                                                        driver);
        /* Enable or disalbe color space convert */
-       printk("rk3036_hdmi_video_csc:input_color=%d,output_color=%d\n",vpara->input_color,vpara->output_color);
+       hdmi_dbg(hdmi_drv->dev, "[%s] input_color=%d,output_color=%d\n",
+                __func__, vpara->input_color, vpara->output_color);
        if (vpara->input_color != vpara->output_color) {
                if(vpara->input_color == VIDEO_INPUT_COLOR_RGB) {/*rgb2yuv*/
                        coeff = coeff_csc[3];
@@ -294,7 +305,7 @@ static int rk3036_hdmi_video_csc(struct hdmi *hdmi_drv,
                        hdmi_writel(hdmi_dev, VIDEO_CONTRL3, value);
                        hdmi_msk_reg(hdmi_dev, VIDEO_CONTRL,
                                     m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_EXCHANGE,
-                                    v_VIDEO_AUTO_CSC(0) | v_VIDEO_C0_C2_EXCHANGE(0));
+                                    v_VIDEO_AUTO_CSC(0) | v_VIDEO_C0_C2_EXCHANGE(1));
                } else {/*yuv2rgb*/
 #ifdef AUTO_DEFINE_CSC
                        value = v_SOF_DISABLE | v_CSC_DISABLE;
@@ -369,9 +380,8 @@ static void rk3036_hdmi_config_avi(struct hdmi *hdmi_drv,
 
        info[4] = (avi_color_mode << 5);
        info[5] =
-           (AVI_COLORIMETRY_NO_DATA << 6) | (AVI_CODED_FRAME_ASPECT_NO_DATA <<
-                                             4) |
-           ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME;
+           (AVI_COLORIMETRY_NO_DATA << 6) | (AVI_CODED_FRAME_ASPECT_NO_DATA << 4) |
+            ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME;
        info[6] = 0;
        info[7] = vic;
        if ((vic == HDMI_720X480I_60HZ_VIC) || (vic == HDMI_720X576I_50HZ_VIC))
@@ -396,6 +406,7 @@ static int rk3036_hdmi_config_video(struct hdmi *hdmi_drv,
        struct rk_hdmi_device *hdmi_dev = container_of(hdmi_drv,
                                                       struct rk_hdmi_device,
                                                       driver);
+       int val;
 
        hdmi_dbg(hdmi_drv->dev, "[%s]\n", __func__);
 
@@ -426,11 +437,10 @@ static int rk3036_hdmi_config_video(struct hdmi *hdmi_drv,
        hdmi_writel(hdmi_dev, VIDEO_CONTRL1,
                    v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444) |
                    v_DE_EXTERNAL);
-       hdmi_writel(hdmi_dev, VIDEO_CONTRL2,
-                   v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
-                   v_VIDEO_OUTPUT_FORMAT(vpara->output_color & 0xFF));
-       hdmi_writel(hdmi_dev, VIDEO_CONTRL2,
-                   v_VIDEO_INPUT_CSP(vpara->input_color && 0x1));
+       val = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
+                   v_VIDEO_OUTPUT_FORMAT(vpara->output_color & 0x3) |
+                   v_VIDEO_INPUT_CSP(vpara->input_color && 0x1);
+       hdmi_writel(hdmi_dev, VIDEO_CONTRL2,val);
 
        /* Set HDMI Mode */
        hdmi_writel(hdmi_dev, HDCP_CTRL, v_HDMI_DVI(vpara->output_mode));
@@ -670,7 +680,7 @@ void rk3036_hdmi_irq(struct hdmi *hdmi_drv)
                        hdmi_drv->state = WAIT_HOTPLUG;
 
                queue_delayed_work(hdmi_drv->workqueue, &hdmi_drv->delay_work,
-                                  msecs_to_jiffies(40));
+                                  msecs_to_jiffies(0));
 
        }/*plug out*/
 

diff --git a/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.h b/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.h
index 661cf20d456ff1c32b48302306cc5e71057988bb..d60bafe99d4879398d0d12e78b933afc68a8371c 100755 (executable)
--- a/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.h
+++ b/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.h
@@ -64,7 +64,7 @@ enum {
 #define m_VIDEO_OUTPUT_FORMAT  (3 << 6)
 #define m_VIDEO_INPUT_BITS     (3 << 4)
 #define m_VIDEO_INPUT_CSP      (1 << 0)
-#define v_VIDEO_OUTPUT_FORMAT(n)(n << 6)
+#define v_VIDEO_OUTPUT_FORMAT(n) (((n)&0x3) << 6)
 #define v_VIDEO_INPUT_BITS(n)  (n << 4)
 #define v_VIDEO_INPUT_CSP(n)   (n << 0)
 

diff --git a/drivers/video/rockchip/lcdc/rk312x_lcdc.c b/drivers/video/rockchip/lcdc/rk312x_lcdc.c
index 201a2703171bafb38247dd8ed9f557ee8962bb15..0c629252cf2c55aa20dd485e7fafe94380f9b847 100755 (executable)
--- a/drivers/video/rockchip/lcdc/rk312x_lcdc.c
+++ b/drivers/video/rockchip/lcdc/rk312x_lcdc.c
@@ -537,12 +537,13 @@ static int rk312x_lcdc_set_hwc_lut(struct rk_lcdc_driver *dev_drv, int *hwc_lut,
                if(mode == 1)
                        dev_drv->hwc_lut[i] = hwc_lut[i];
                v = dev_drv->hwc_lut[i];
-               c = lcdc_dev->hwc_lut_addr_base + (i<<2);
+               c = lcdc_dev->hwc_lut_addr_base + i;
                writel_relaxed(v, c);
        }
        lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(1));
         lcdc_cfg_done(lcdc_dev);
         spin_unlock(&lcdc_dev->reg_lock);
+
        return 0;
 
 }
@@ -562,13 +563,11 @@ static int rk312x_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
                v = dev_drv->cur_screen->dsp_lut[i];
                c = lcdc_dev->dsp_lut_addr_base + (i<<2);
                writel_relaxed(v, c);
-
        }
        lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
         lcdc_cfg_done(lcdc_dev);
         spin_unlock(&lcdc_dev->reg_lock);
        return 0;
-
 }
 
 static int rk312x_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
@@ -635,6 +634,8 @@ static int rk312x_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
        lcdc_cfg_done(lcdc_dev);
        if (dev_drv->iommu_enabled)     /* disable win0 to workaround iommu pagefault */
                lcdc_layer_enable(lcdc_dev, 0, 0);
+       if ((dev_drv->ops->open_bcsh)&&(dev_drv->output_color == COLOR_YCBCR))
+               dev_drv->ops->open_bcsh(dev_drv,1);
        lcdc_dev->pre_init = true;
 
        return 0;
@@ -861,13 +862,13 @@ static int rk312x_lcdc_set_scaler(struct rk_lcdc_driver *dev_drv,
 
         spin_lock(&lcdc_dev->reg_lock);
        if (dst->color_mode != src->color_mode) {
-               dev_drv->output_color = dst->color_mode;
+               /*dev_drv->output_color = dst->color_mode;
                if (dev_drv->output_color == COLOR_YCBCR)
                        dev_drv->overlay_mode = VOP_YUV_DOMAIN;
                else
                        dev_drv->overlay_mode = VOP_RGB_DOMAIN;
                lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE,
-                            v_SW_OVERLAY_MODE(dev_drv->overlay_mode));
+                            v_SW_OVERLAY_MODE(dev_drv->overlay_mode));*/
        }
 
        lcdc_writel(lcdc_dev, SCALER_FACTOR,
@@ -922,7 +923,7 @@ static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
        spin_lock(&lcdc_dev->reg_lock);
        if (likely(lcdc_dev->clk_on)) {
                /* Select output color domain */
-               dev_drv->output_color = screen->color_mode;
+               /*dev_drv->output_color = screen->color_mode;
                if (lcdc_dev->soc_type == VOP_RK312X) {
                        if (dev_drv->output_color == COLOR_YCBCR)
                                dev_drv->overlay_mode = VOP_YUV_DOMAIN;
@@ -931,7 +932,8 @@ static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
                } else {
                        dev_drv->output_color = COLOR_RGB;
                        dev_drv->overlay_mode = VOP_RGB_DOMAIN;
-               }
+               }*/
+               dev_drv->overlay_mode = VOP_RGB_DOMAIN;/*something wrong at yuv domain*/
 
                switch (screen->type) {
                 case SCREEN_RGB:
@@ -985,6 +987,7 @@ static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
                        }
                        break;
                case SCREEN_TVOUT:
+               case SCREEN_TVOUT_TEST:
                        mask = m_TVE_DAC_DCLK_EN;
                        val = v_TVE_DAC_DCLK_EN(1);
                        if (screen->pixelrepeat) {
@@ -1004,7 +1007,8 @@ static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
                                return -1;
                        }
                         if (lcdc_dev->soc_type == VOP_RK312X) {
-                               dev_drv->overlay_mode = VOP_YUV_DOMAIN;
+                               if (screen->type == SCREEN_TVOUT_TEST)/*for TVE index test,vop must ovarlay at yuv domain*/
+                                       dev_drv->overlay_mode = VOP_YUV_DOMAIN;
                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
                                              m_SW_UV_OFFSET_EN,
                                              v_SW_UV_OFFSET_EN(1));
@@ -1194,6 +1198,7 @@ static int rk312x_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
        if ((open) && (!lcdc_dev->atv_layer_cnt)) {
                 rockchip_set_system_status(SYS_STATUS_LCDC0);
                rk312x_lcdc_pre_init(dev_drv);
+               rk312x_lcdc_clk_enable(lcdc_dev);
 #if defined(CONFIG_ROCKCHIP_IOMMU)
                if (dev_drv->iommu_enabled) {
                        if (!dev_drv->mmu_dev) {
@@ -1202,13 +1207,14 @@ static int rk312x_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
                                if (dev_drv->mmu_dev) {
                                        rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
                                                                  dev_drv->dev);
-                                        rockchip_iovmm_activate(dev_drv->dev);
                                 } else {
                                        dev_err(dev_drv->dev,
                                                "failed to get rockchip iommu device\n");
                                        return -1;
                                }
                        }
+                       if (dev_drv->mmu_dev)
+                               rockchip_iovmm_activate(dev_drv->dev);
                }
 #endif
                rk312x_lcdc_reg_restore(lcdc_dev);
@@ -1545,7 +1551,7 @@ static int rk312x_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
                if (dev_drv->cur_screen->dsp_lut)
                        rk312x_lcdc_set_lut(dev_drv);
                /*set hwc lut*/
-               //rk312x_lcdc_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0);
+               rk312x_lcdc_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0);
 
                spin_lock(&lcdc_dev->reg_lock);
 
@@ -1737,8 +1743,25 @@ static int rk312x_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
 
        spin_lock(&lcdc_dev->reg_lock);
        if (lcdc_dev->clk_on) {
+               if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
+                       if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
+                               lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_Y2R_EN,
+                                               v_BCSH_Y2R_EN(0));
+                       else    /* YUV2RGB */
+                               lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
+                                               m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE,
+                                               v_BCSH_Y2R_EN(1) | v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG));
+               } else {        /* overlay_mode=VOP_RGB_DOMAIN */
+                       if (dev_drv->output_color == COLOR_RGB) /* bypass */
+                               lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
+                                               v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(1));
+                       else    /* RGB2YUV */
+                               lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
+                                               m_BCSH_R2Y_EN | m_BCSH_R2Y_CSC_MODE,
+                                               v_BCSH_R2Y_EN(1) | v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG));
+               }
                if (open) {
-                       lcdc_writel(lcdc_dev, BCSH_CTRL,
+                       lcdc_msk_reg(lcdc_dev, BCSH_CTRL,m_BCSH_EN | m_BCSH_OUT_MODE,
                                    v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
                        lcdc_writel(lcdc_dev, BCSH_BCS,
                                    v_BCSH_BRIGHTNESS(0x00) |
@@ -1751,24 +1774,7 @@ static int rk312x_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
                        lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
                }
                lcdc_cfg_done(lcdc_dev);
-       }
 
-       if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
-               if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
-                       lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_Y2R_EN,
-                                       v_BCSH_Y2R_EN(0));
-               else    /* YUV2RGB */
-                       lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
-                                       m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE,
-                                       v_BCSH_Y2R_EN(1) | v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG));
-       } else {        /* overlay_mode=VOP_RGB_DOMAIN */
-               if (dev_drv->output_color == COLOR_RGB) /* bypass */
-                       lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_R2Y_EN,
-                                       v_BCSH_R2Y_EN(0));
-               else    /* RGB2YUV */
-                       lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
-                                       m_BCSH_R2Y_EN | m_BCSH_R2Y_CSC_MODE,
-                                       v_BCSH_R2Y_EN(1) | v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG));
        }
 
        spin_unlock(&lcdc_dev->reg_lock);

diff --git a/drivers/video/rockchip/lcdc/rk3288_lcdc.c b/drivers/video/rockchip/lcdc/rk3288_lcdc.c
index a794a0d50c27f9c866f1b5c49892d9ce51ec2812..1be30625903e0bc1f7aeef0d46d00add75e8535e 100755 (executable)
--- a/drivers/video/rockchip/lcdc/rk3288_lcdc.c
+++ b/drivers/video/rockchip/lcdc/rk3288_lcdc.c
@@ -1306,6 +1306,7 @@ static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
        if ((open) && (!lcdc_dev->atv_layer_cnt)) {
                rockchip_set_system_status(sys_status);
                rk3288_lcdc_pre_init(dev_drv);
+               rk3288_lcdc_clk_enable(lcdc_dev);
 #if defined(CONFIG_ROCKCHIP_IOMMU)
                if (dev_drv->iommu_enabled) {
                        if (!dev_drv->mmu_dev) {
@@ -1314,16 +1315,16 @@ static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
                                if (dev_drv->mmu_dev) {
                                        rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
                                                                  dev_drv->dev);
-                                        rockchip_iovmm_activate(dev_drv->dev);
                                 } else {
                                        dev_err(dev_drv->dev,
                                                "failed to get rockchip iommu device\n");
                                        return -1;
                                }
                        }
+                       if (dev_drv->mmu_dev)
+                               rockchip_iovmm_activate(dev_drv->dev);
                }
 #endif
-               rk3288_lcdc_clk_enable(lcdc_dev);
                rk3288_lcdc_reg_restore(lcdc_dev);
                if (dev_drv->iommu_enabled)
                        rk3288_lcdc_mmu_en(dev_drv);

diff --git a/drivers/video/rockchip/rk_fb.c b/drivers/video/rockchip/rk_fb.c
index c4289ea79ff8c1f0125f2fcd8650fc899b6c3d96..3cbe44505371c9146e71696f49dd419c83ef8653 100755 (executable)
--- a/drivers/video/rockchip/rk_fb.c
+++ b/drivers/video/rockchip/rk_fb.c
@@ -1170,6 +1170,11 @@ static int rk_fb_pan_display(struct fb_var_screeninfo *var,
        u32 stride_32bit_2;
        u16 uv_x_off, uv_y_off, uv_y_act;
        u8 is_pic_yuv = 0;
+#ifdef CONFIG_ROCKCHIP_IOMMU
+       ion_phys_addr_t phy_addr;
+       size_t len = 0;
+       int ret = 0;
+#endif
 
        win_id = dev_drv->ops->fb_get_win_id(dev_drv, info->fix.id);
        if (win_id < 0)
@@ -1282,16 +1287,40 @@ static int rk_fb_pan_display(struct fb_var_screeninfo *var,
 
        dev_drv->ops->pan_display(dev_drv, win_id);
        if (rk_fb->disp_mode == DUAL) {
-               if (extend_win->state && (hdmi_switch_complete)) {
+               if (extend_win->state &&
+                   (hdmi_switch_complete & (1 << extend_win_id))) {
                        extend_win->area[0].y_offset = win->area[0].y_offset;
                        if (extend_dev_drv->rotate_mode > X_Y_MIRROR) {
                                rk_fb_rotate(extend_info, info,
                                                win->area[0].y_offset);
                        } else {
+#ifdef CONFIG_ROCKCHIP_IOMMU
+                               if (extend_dev_drv->iommu_enabled) {
+                                       ret = ion_map_iommu(extend_dev_drv->dev,
+                                                           rk_fb->ion_client,
+                                                           win->area[0].ion_hdl,
+                                                           (unsigned long *)&phy_addr,
+                                                           (unsigned long *)&len);
+                                       if (ret < 0) {
+                                               dev_err(extend_dev_drv->dev, "ion map to get phy addr failed\n");
+                                               ion_free(rk_fb->ion_client, win->area[0].ion_hdl);
+                                               return -ENOMEM;
+                                       }
+                                       extend_win->area[0].smem_start = phy_addr;
+                                       extend_win->area[0].cbr_start =
+                                                       win->area[0].cbr_start;
+                               } else {
+                                       extend_win->area[0].smem_start =
+                                                       win->area[0].smem_start;
+                                       extend_win->area[0].cbr_start =
+                                                       win->area[0].cbr_start;
+                               }
+#else
                                extend_win->area[0].smem_start =
                                                win->area[0].smem_start;
                                extend_win->area[0].cbr_start =
                                                win->area[0].cbr_start;
+#endif
                        }
                        extend_dev_drv->ops->pan_display(extend_dev_drv,
                                                         extend_win_id);
@@ -1402,6 +1431,9 @@ void rk_fb_free_dma_buf(struct rk_lcdc_driver *dev_drv,
        int i, index_buf;
        struct rk_fb_reg_area_data *area_data;
        struct rk_fb *rk_fb = platform_get_drvdata(fb_pdev);
+#if defined(CONFIG_ROCKCHIP_IOMMU)
+       struct rk_lcdc_driver *ext_dev_drv = rk_get_extend_lcdc_drv();
+#endif
 
        for (i = 0; i < reg_win_data->area_num; i++) {
                area_data = &reg_win_data->reg_area_data[i];
@@ -1412,6 +1444,12 @@ void rk_fb_free_dma_buf(struct rk_lcdc_driver *dev_drv,
                                        area_data->ion_handle);
                        freed_addr[freed_index++] = area_data->smem_start;
                }
+               if (rk_fb->disp_mode == DUAL && hdmi_switch_complete == 0xff) {
+                       if (ext_dev_drv->iommu_enabled)
+                               ion_unmap_iommu(ext_dev_drv->dev,
+                                               rk_fb->ion_client,
+                                               area_data->ion_handle);
+               }
 #endif
                if (area_data->ion_handle != NULL) {
                        ion_unmap_kernel(rk_fb->ion_client,
@@ -1461,8 +1499,10 @@ static void rk_fb_update_driver(struct rk_lcdc_driver *dev_drv,
                win->g_alpha_val = reg_win_data->g_alpha_val;
                for (i = 0; i < RK_WIN_MAX_AREA; i++) {
                        if (reg_win_data->reg_area_data[i].smem_start > 0) {
+                               win->area[i].ion_hdl =
+                                       reg_win_data->reg_area_data[i].ion_handle;
                                win->area[i].smem_start =
-                                   reg_win_data->reg_area_data[i].smem_start;
+                                       reg_win_data->reg_area_data[i].smem_start;
                                 if (inf->disp_mode == DUAL) {
                                        win->area[i].xpos =
                                                reg_win_data->reg_area_data[i].xpos;
@@ -1529,10 +1569,14 @@ static int rk_fb_update_hdmi_win(struct rk_lcdc_win *ext_win,
         struct rk_lcdc_win *last_win;
         bool is_yuv = false;
         static u8 fb_index = 0;
-
+#ifdef CONFIG_ROCKCHIP_IOMMU
+       ion_phys_addr_t phy_addr;
+       size_t len = 0;
+       int ret = 0;
+#endif
         if ((rk_fb->disp_mode != DUAL) ||
                 (hdmi_get_hotplug() != HDMI_HPD_ACTIVED) ||
-                (!hdmi_switch_complete)) {
+                (hdmi_switch_complete != 0xff)) {
                 printk(KERN_INFO "%s: hdmi is disconnect!\n", __func__);
                 return -1;
         }
@@ -1611,7 +1655,25 @@ static int rk_fb_update_hdmi_win(struct rk_lcdc_win *ext_win,
                 y_stride = ALIGN_N_TIMES(vir_width_bit, 32) / 8;
                 ext_win->area[0].y_vir_stride = y_stride >> 2;
        } else {
+#ifdef CONFIG_ROCKCHIP_IOMMU
+               if (ext_dev_drv->iommu_enabled) {
+                       ret = ion_map_iommu(ext_dev_drv->dev,
+                                           rk_fb->ion_client,
+                                           win->area[0].ion_hdl,
+                                           (unsigned long *)&phy_addr,
+                                           (unsigned long *)&len);
+                       if (ret < 0) {
+                               dev_err(ext_dev_drv->dev, "ion map to get phy addr failed\n");
+                               ion_free(rk_fb->ion_client, win->area[0].ion_hdl);
+                               return -ENOMEM;
+                       }
+                       ext_win->area[0].smem_start = phy_addr;
+               } else {
+                       ext_win->area[0].smem_start = win->area[0].smem_start;
+               }
+#else
                ext_win->area[0].smem_start = win->area[0].smem_start;
+#endif
                 ext_win->area[0].y_offset = win->area[0].y_offset;
                 ext_win->area[0].xact = win->area[0].xact;
                 ext_win->area[0].yact = win->area[0].yact;
@@ -1691,7 +1753,17 @@ static int rk_fb_update_hdmi_win(struct rk_lcdc_win *ext_win,
                ext_win->area[0].c_offset = win->area[0].c_offset;
         } else {
                ext_win->area[0].uv_vir_stride = win->area[0].uv_vir_stride;
+#ifdef CONFIG_ROCKCHIP_IOMMU
+               if (ext_dev_drv->iommu_enabled)
+                       ext_win->area[0].cbr_start =
+                               ext_win->area[0].smem_start +
+                                ext_win->area[0].y_offset +
+                                ext_win->area[0].xvir * ext_win->area[0].yvir;
+               else
+                       ext_win->area[0].cbr_start = win->area[0].cbr_start;
+#else
                ext_win->area[0].cbr_start = win->area[0].cbr_start;
+#endif
                ext_win->area[0].c_offset = win->area[0].c_offset;
         }
 
@@ -1762,7 +1834,7 @@ static void rk_fb_update_reg(struct rk_lcdc_driver *dev_drv,
 
        if ((rk_fb->disp_mode == DUAL)
            && (hdmi_get_hotplug() == HDMI_HPD_ACTIVED)
-           && hdmi_switch_complete) {
+           && (hdmi_switch_complete == 0xff)) {
                 ext_dev_drv = rk_get_extend_lcdc_drv();
                 if (!ext_dev_drv) {
                         printk(KERN_ERR "hdmi lcdc driver not found!\n");
@@ -2322,6 +2394,7 @@ EXPORT_SYMBOL(rk_get_real_fps);
 #ifdef CONFIG_ROCKCHIP_IOMMU
 #define ION_MAX 10
 static struct ion_handle *ion_hanle[ION_MAX];
+static struct ion_handle *ion_hwc[1];
 #endif
 static int rk_fb_ioctl(struct fb_info *info, unsigned int cmd,
                       unsigned long arg)
@@ -2356,6 +2429,51 @@ static int rk_fb_ioctl(struct fb_info *info, unsigned int cmd,
        }
 
        switch (cmd) {
+       case RK_FBIOSET_HWC_ADDR:
+       {
+               u32 hwc_phy[1];
+               if (copy_from_user(hwc_phy, argp, 4))
+                       return -EFAULT;
+               if (!dev_drv->iommu_enabled) {
+                       fix->smem_start = hwc_phy[0];
+               } else {
+                       int usr_fd;
+                       struct ion_handle *hdl;
+                       ion_phys_addr_t phy_addr;
+                       size_t len;
+
+                       usr_fd = hwc_phy[0];
+                       if (!usr_fd) {
+                               fix->smem_start = 0;
+                               fix->mmio_start = 0;
+                               break;
+                       }
+
+                       if (ion_hwc[0] != 0) {
+                               ion_free(rk_fb->ion_client, ion_hwc[0]);
+                               ion_hwc[0] = 0;
+                       }
+
+                       hdl = ion_import_dma_buf(rk_fb->ion_client, usr_fd);
+                       if (IS_ERR(hdl)) {
+                               dev_err(info->dev, "failed to get hwc ion handle:%ld\n",
+                                       PTR_ERR(hdl));
+                               return -EFAULT;
+                       }
+
+                       ret = ion_map_iommu(dev_drv->dev, rk_fb->ion_client, hdl,
+                                               (unsigned long *)&phy_addr,
+                                               (unsigned long *)&len);
+                       if (ret < 0) {
+                               dev_err(info->dev, "ion map to get hwc phy addr failed");
+                               ion_free(rk_fb->ion_client, hdl);
+                               return -ENOMEM;
+                       }
+                       fix->smem_start = phy_addr;
+                       ion_hwc[0] = hdl;
+               }
+               break;
+       }
        case RK_FBIOSET_YUV_ADDR:
                {
                        u32 yuv_phy[2];
@@ -2898,7 +3016,7 @@ static int rk_fb_set_par(struct fb_info *info)
        win->g_alpha_val = 0;
 
        if (rk_fb->disp_mode == DUAL) {
-               if (extend_win->state && (hdmi_switch_complete)) {
+               if (extend_win->state && (hdmi_switch_complete == 0xff)) {
                        if (info != extend_info) {
                                if (win->area[0].xact < win->area[0].yact) {
                                        extend_win->area[0].xact =
@@ -3282,19 +3400,25 @@ int rk_fb_switch_screen(struct rk_screen *screen, int enable, int lcdc_id)
                                }
                        }
                        if (dev_drv->win[win_id]->logicalstate) {
-                               dev_drv->ops->open(dev_drv, win_id, 1);
+                               if (!dev_drv->win[win_id]->state)
+                                       dev_drv->ops->open(dev_drv, win_id, 1);
                                if (!load_screen) {
                                        dev_drv->ops->load_screen(dev_drv, 1);
                                        load_screen = 1;
                                }
                                info->var.activate |= FB_ACTIVATE_FORCE;
                                info->fbops->fb_set_par(info);
-                               info->fbops->fb_pan_display(&info->var, info);
+                               hdmi_switch_complete |= (1 << win_id);
+                               if (rk_fb->disp_mode == DUAL)
+                                       pmy_info->fbops->fb_pan_display(&pmy_info->var,
+                                                                       pmy_info);
+                               else
+                                       info->fbops->fb_pan_display(&info->var, info);
                        }
                }
        }
 
-       hdmi_switch_complete = 1;
+       hdmi_switch_complete = 0xff;
        if (rk_fb->disp_mode == ONE_DUAL) {
                if (dev_drv->ops->set_screen_scaler)
                        dev_drv->ops->set_screen_scaler(dev_drv, dev_drv->screen0, 1);
@@ -3607,6 +3731,7 @@ static int init_lcdc_device_driver(struct rk_fb *rk_fb,
        dev_drv->trsm_ops = rk_fb_trsm_ops_get(screen->type);
        if (dev_drv->prop != PRMRY)
                rk_fb_get_prmry_screen(screen);
+       dev_drv->output_color = screen->color_mode;
 
        return 0;
 }
@@ -3765,22 +3890,15 @@ int rk_fb_register(struct rk_lcdc_driver *dev_drv,
        if (dev_drv->prop == PRMRY) {
                struct fb_info *main_fbi = rk_fb->fb[0];
                main_fbi->fbops->fb_open(main_fbi, 1);
-/*
+
 #if defined(CONFIG_ROCKCHIP_IOMMU)
                if (dev_drv->iommu_enabled) {
-                       mmu_dev =
-                           rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name);
-                       if (mmu_dev) {
-                               rk_fb_platform_set_sysmmu(mmu_dev, dev_drv->dev);
+                       if (dev_drv->mmu_dev)
                                rockchip_iovmm_set_fault_handler(dev_drv->dev,
-                                                                 rk_fb_sysmmu_fault_handler);
-                               rockchip_iovmm_activate(dev_drv->dev);
-                       } else
-                               dev_err(dev_drv->dev,
-                                       "failed to get rockchip iommu device\n");
+                                               rk_fb_sysmmu_fault_handler);
                }
 #endif
-*/
+
                rk_fb_alloc_buffer(main_fbi, 0);        /* only alloc memory for main fb */
                if (support_uboot_display()) {
                        if (dev_drv->iommu_enabled) {

diff --git a/include/dt-bindings/rkfb/rk_fb.h b/include/dt-bindings/rkfb/rk_fb.h
index 03e4016772cf25b447560f57087199110ff2c137..f05d165e873d976ba2789f27b508711264537ae2 100755 (executable)
--- a/include/dt-bindings/rkfb/rk_fb.h
+++ b/include/dt-bindings/rkfb/rk_fb.h
@@ -31,6 +31,7 @@
 #define SCREEN_MIPI       7
 #define SCREEN_DUAL_MIPI   8
 #define SCREEN_EDP         9
+#define SCREEN_TVOUT_TEST  10
 
 #define LVDS_8BIT_1     0
 #define LVDS_8BIT_2     1

diff --git a/include/linux/mfd/rt5036/rt5036-irq.h b/include/linux/mfd/rt5036/rt5036-irq.h
new file mode 100755 (executable)
index 0000000..2de886f
--- /dev/null
+++ b/include/linux/mfd/rt5036/rt5036-irq.h
@@ -0,0 +1,19 @@
+/*
+ *  include/linux/mfd/rt5036/rt5036-irq.h
+ *  Include header file for Richtek RT5036 irq option driver
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#ifndef _LINUX_MFD_RT5036_IRQ_H
+#define _LINUX_MFD_RT5036_IRQ_H
+
+#define RT5036_IRQPREZ_MASK 0x80
+
+#endif /* #ifndef _LINUX_MFD_RT5036_IRQ_H */

diff --git a/include/linux/mfd/rt5036/rt5036-misc.h b/include/linux/mfd/rt5036/rt5036-misc.h
new file mode 100755 (executable)
index 0000000..3533539
--- /dev/null
+++ b/include/linux/mfd/rt5036/rt5036-misc.h
@@ -0,0 +1,55 @@
+/*
+ *  include/linux/mfd/rt5036/rt5036-misc.h
+ *  Include header file for Richtek RT5036 Misc option
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#ifndef _LINUX_MFD_RT5036_MISC_H
+#define _LINUX_MFD_RT5036_MISC_H
+
+enum {
+       MISCEVENT_PWRONLP = 3,
+       MISCEVENT_PWRONSP,
+       MISCEVENT_PWRONF,
+       MISCEVENT_PWRONR,
+       MISCEVENT_KPSHDN,
+       MISCEVENT_VDDALV,
+       MISCEVNET_OTM,
+       MISCEVENT_PMICSYSLV = 13,
+       MISCEVENT_LSW2LV,
+       MISCEVENT_LSW1LV,
+       MISCEVENT_LDO4LV,
+       MISCEVENT_LDO3LV,
+       MISCEVENT_LDO2LV,
+       MISCEVENT_LDO1LV,
+       MISCEVENT_BUCK4LV,
+       MISCEVENT_BUCK3LV,
+       MISCEVENT_BUCK2LV,
+       MISCEVENT_BUCK1LV,
+       MISCEVENT_MAX,
+};
+
+#define RT5036_SHDNPRESS_MASK  0x0C
+#define RT5036_SHDNPRESS_SHIFT 2
+
+#define RT5036_STBEN_MASK      0x06
+#define RT5036_STBEN_SHIFT     1
+
+#define RT5036_LPSHDNEN_MASK   0x04
+#define RT5036_CHIPSHDN_MASK   0x80
+#define RT5036_SYSUVLO_SHIFT   5
+#define RT5036_SYSUVLO_MASK    0xE0
+#define RT5036_SYSLVENSHDN_MASK        0x20
+#define RT5036_PWRRDY_MASK     0x80
+
+extern int rt5036_vin_exist(void);
+extern void rt5036_chip_shutdown(void);
+
+#endif /* #ifndef _LINUX_MFD_RT5036_MISC_H */

diff --git a/include/linux/mfd/rt5036/rt5036.h b/include/linux/mfd/rt5036/rt5036.h
new file mode 100644 (file)
index 0000000..2b56d41
--- /dev/null
+++ b/include/linux/mfd/rt5036/rt5036.h
@@ -0,0 +1,369 @@
+/*
+ *  include/linux/mfd/rt5036/rt5036.h
+ *  Include header file for Richtek RT5036 Core file
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#ifndef _LINUX_MFD_RT5036_H
+#define _LINUX_MFD_RT5036_H
+#include <linux/power_supply.h>
+
+#define RT5036_DEV_NAME                "rt5036"
+#define RT5036_DRV_VER         "1.0.8_R"
+
+enum {
+       RT5036_ID_DCDC1,
+       RT5036_ID_DCDC2,
+       RT5036_ID_DCDC3,
+       RT5036_ID_DCDC4,
+       RT5036_ID_LDO1,
+       RT5036_ID_LDO2,
+       RT5036_ID_LDO3,
+       RT5036_ID_LDO4,
+       RT5036_ID_LSW1,
+       RT5036_ID_LSW2,
+       RT5036_MAX_REGULATOR,
+};
+
+enum {
+       RT5036_REG_DEVID,
+       RT5036_REG_RANGE1START = RT5036_REG_DEVID,
+       RT5036_REG_CHGCTL1,
+       RT5036_REG_CHGCTL2,
+       RT5036_REG_RESV1,
+       RT5036_REG_CHGCTL3,
+       RT5036_REG_CHGCTL4,
+       RT5036_REG_CHGCTL5,
+       RT5036_REG_CHGCTL6,
+       RT5036_REG_CHGCTL7,
+       RT5036_REG_RSTCHG,
+       RT5036_REG_RANGE1END = RT5036_REG_RSTCHG,
+       RT5036_REG_CHGIRQ1 = 0x10,
+       RT5036_REG_RANGE2START = RT5036_REG_CHGIRQ1,
+       RT5036_REG_CHGIRQ2,
+       RT5036_REG_CHGIRQ3,
+       RT5036_REG_CHGIRQMASK1,
+       RT5036_REG_CHGIRQMASK2,
+       RT5036_REG_CHGIRQMASK3,
+       RT5036_REG_CHGSTAT1,
+       RT5036_REG_CHGSTAT2,
+       RT5036_REG_CHGSTAT2MASK,
+       RT5036_REG_RANGE2END = RT5036_REG_CHGSTAT2MASK,
+       RT5036_REG_BUCKVN1 = 0x41,
+       RT5036_REG_RANGE3START = RT5036_REG_BUCKVN1,
+       RT5036_REG_BUCKVN2,
+       RT5036_REG_BUCKVN3,
+       RT5036_REG_BUCKVN4,
+       RT5036_REG_BUCKVRCN,
+       RT5036_REG_BUCKVRCNEN,
+       RT5036_REG_BUCKMODE,
+       RT5036_REG_LDOVN1,
+       RT5036_REG_LDOVN2,
+       RT5036_REG_LDOVN3,
+       RT5036_REG_LDOVN4,
+       RT5036_REG_LDOVRCN,
+       RT5036_REG_LDOVRCNEN,
+       RT5036_REG_LDOMODE,
+       RT5036_REG_BUCKLDONEN,
+       RT5036_REG_LSWEN,
+       RT5036_REG_MISC1,
+       RT5036_REG_MISC2,
+       RT5036_REG_MISC3,
+       RT5036_REG_MISC4,
+       RT5036_REG_MISC5,
+       RT5036_REG_ONOFFEVENT,
+       RT5036_REG_BUCKLDOIRQ,
+       RT5036_REG_LSWBASEIRQ,
+       RT5036_REG_PWRKEYIRQ,
+       RT5036_REG_BUCKLDOIRQMASK,
+       RT5036_REG_LSWBASEIRQMASK,
+       RT5036_REG_PWRKEYIRQMASK,
+       RT5036_REG_RANGE3END = RT5036_REG_PWRKEYIRQMASK,
+       RT5036_REG_MISC6 = 0x65,
+       RT5036_REG_RANGE4START = RT5036_REG_MISC6,
+       RT5036_REG_RANGE4END = RT5036_REG_MISC6,
+       RT5036_REG_BUCKVS1 = 0x71,
+       RT5036_REG_RANGE5START = RT5036_REG_BUCKVS1,
+       RT5036_REG_BUCKVS2,
+       RT5036_REG_BUCKVS3,
+       RT5036_REG_BUCKVS4,
+       RT5036_REG_BUCKVRCS,
+       RT5036_REG_BUCKVRCSEN,
+       RT5036_REG_RESV2,
+       RT5036_REG_LDOVS1,
+       RT5036_REG_LDOVS2,
+       RT5036_REG_LDOVS3,
+       RT5036_REG_LDOVS4,
+       RT5036_REG_LDOVRCS,
+       RT5036_REG_LDOVRCSEN,
+       RT5036_REG_RESV3,
+       RT5036_REG_BUCKLDOSEN,
+       RT5036_REG_LSWVN2,
+       RT5036_REG_LSWVN1,
+       RT5036_REG_LSWVS2,
+       RT5036_REG_LSWVS1,
+       RT5036_REG_LSWVRC,
+       RT5036_REG_LSWVRCEN,
+       RT5036_REG_BUCKOCPSEL,
+       RT5036_REG_RANGE5END = RT5036_REG_BUCKOCPSEL,
+       RT5036_REG_RTCADJ = 0x90,
+       RT5036_REG_RANGE6START = RT5036_REG_RTCADJ,
+       RT5036_REG_RTCTSEC,
+       RT5036_REG_RTCTMINUTE,
+       RT5036_REG_RTCTHOUR,
+       RT5036_REG_RTCTYEAR,
+       RT5036_REG_RTCTMON,
+       RT5036_REG_RTCTDATEW,
+       RT5036_REG_STBMODE,
+       RT5036_REG_RTCASEC,
+       RT5036_REG_RTCAMINUTE,
+       RT5036_REG_RTCAHOUR,
+       RT5036_REG_RTCAYEAR,
+       RT5036_REG_RTCAMONTH,
+       RT5036_REG_RTCADATE,
+       RT5036_REG_STBCDSEC,
+       RT5036_REG_STBCDMINUTE,
+       RT5036_REG_STBCDHOUR,
+       RT5036_REG_STBCDDATEL,
+       RT5036_REG_STBCDDATEH,
+       RT5036_REG_RESV4,
+       RT5036_REG_STBWACKIRQ,
+       RT5036_REG_STBWACKIRQMASK,
+       RT5036_REG_RANGE6END = RT5036_REG_STBWACKIRQMASK,
+       RT5036_REG_MAX,
+};
+
+enum {
+       RT5036_RAMP_25mV,
+       RT5036_RAMP_50mV,
+       RT5036_RAMP_75mV,
+       RT5036_RAMP_100mV,
+       RT5036_RAMP_MAX = RT5036_RAMP_100mV,
+};
+
+enum {
+       RT5036_SHDHPRESS_4S,
+       RT5036_SHDNPRESS_6S,
+       RT5036_SHDNPRESS_8S,
+       RT5036_SHDNPRESS_10S,
+       RT5036_SHDNPRESS_MAX = RT5036_SHDNPRESS_10S,
+};
+
+enum {
+       RT5036_STB_DISABLE,
+       RT5036_STB_EN1MS,
+       RT5036_STB_EN2MS,
+       RT5036_STB_EN4MS,
+       RT5036_STB_MAX = RT5036_STB_EN4MS,
+};
+
+enum {
+       RT5036_SYSLV_2P8V,
+       RT5036_SYSLV_2P9V,
+       RT5036_SYSLV_3P0V,
+       RT5036_SYSLV_3P1V,
+       RT5036_SYSLV_3P2V,
+       RT5036_SYSLV_3P3V,
+       RT5036_SYSLV_3P4V,
+       RT5036_SYSLV_3P5V,
+       RT5036_SYSLV_MAX = RT5036_SYSLV_3P5V
+};
+
+enum {
+       RT5036_IPREC_150mA,
+       RT5036_IPREC_250mA,
+       RT5036_IPREC_350mA,
+       RT5036_IPREC_450mA,
+       RT5036_IPREC_MAX = RT5036_IPREC_450mA,
+};
+
+enum {
+       RT5036_IEOC_DISABLE,
+       RT5036_IEOC_150mA,
+       RT5036_IEOC_200mA,
+       RT5036_IEOC_250mA,
+       RT5036_IEOC_300mA,
+       RT5036_IEOC_400mA,
+       RT5036_IEOC_500mA,
+       RT5036_IEOC_600mA,
+       RT5036_IEOC_MAX = RT5036_IEOC_600mA,
+};
+
+enum {
+       RT5036_VPREC_2P3V,
+       RT5036_VPREC_2P4V,
+       RT5036_VPREC_2P5V,
+       RT5036_VPREC_2P6V,
+       RT5036_VPREC_2P7V,
+       RT5036_VPREC_2P8V,
+       RT5036_VPREC_2P9V,
+       RT5036_VPREC_3P0V,
+       RT5036_VPREC_3P1V,
+       RT5036_VPREC_3P2V,
+       RT5036_VPREC_3P3V,
+       RT5036_VPREC_3P4V,
+       RT5036_VPREC_3P5V,
+       RT5036_VPREC_3P6V,
+       RT5036_VPREC_3P7V,
+       RT5036_VPREC_3P8V,
+       RT5036_VPREC_MAX = RT5036_VPREC_3P8V,
+};
+
+enum {
+       RT5036_BATLV_2P4V,
+       RT5036_BATLV_2P5V,
+       RT5036_BATLV_2P6V,
+       RT5036_BATLV_2P7V,
+       RT5036_BATLV_2P8V,
+       RT5036_BATLV_2P9V,
+       RT5036_BATLV_3P0V,
+       RT5036_BATLV_3P1V,
+       RT5036_BATLV_MAX = RT5036_BATLV_3P1V,
+};
+
+enum {
+       RT5036_VRECHG_0P1V,
+       RT5036_VRECHG_0P2V,
+       RT5036_VRECHG_0P3V,
+       RT5036_VRECHG_0P3V_1,
+       RT5036_VRECHG_MAX = RT5036_VRECHG_0P3V_1,
+};
+
+typedef void (*rt_irq_handler) (void *info, int eventno);
+
+struct rt5036_regulator_ramp {
+       unsigned char nramp_sel:2;
+       unsigned char sramp_sel:2;
+};
+
+struct rt5036_chg_data {
+       int chg_volt;
+       int otg_volt;
+       int acchg_icc;
+       int usbtachg_icc;
+       int usbchg_icc;
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+       int acdet_gpio;
+       int usbdet_gpio;
+#endif                         /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+       u16 te_en:1;
+       u16 iprec:2;
+       u16 ieoc:3;
+       u16 vprec:4;
+       u16 batlv:3;
+       u16 vrechg:2;
+};
+
+struct rt5036_misc_data {
+       u16 shdn_press:2;
+       u16 stb_en:2;
+       u16 lp_enshdn:1;
+       u16 vsysuvlo:3;
+       u16 syslv_enshdn:1;
+};
+
+struct rt5036_irq_data {
+       int irq_gpio;
+};
+
+struct rt5036_chip;
+struct rt5036_platform_data {
+       struct regulator_init_data *regulator[RT5036_MAX_REGULATOR];
+       struct rt5036_chg_data *chg_pdata;
+       struct rt5036_misc_data *misc_pdata;
+       struct rt5036_irq_data *irq_pdata;
+       int (*pre_init)(struct rt5036_chip *rt5036_chip);
+       int (*post_init)(void);
+};
+
+struct rt5036_charger_info {
+       struct i2c_client *i2c;
+       struct device *dev;
+       struct power_supply psy;
+       struct delayed_work dwork;
+       int chg_volt;
+       int otg_volt;
+       int acchg_icc;
+       int usbtachg_icc;
+       int usbchg_icc;
+       int charge_cable;
+#ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN
+       int acdet_gpio;
+       int usbdet_gpio;
+       int acdet_irq;
+       int usbdet_irq;
+       unsigned char usbinit_delay:1;
+#endif                         /* #ifdef CONFIG_RT_SUPPORT_ACUSB_DUALIN */
+       unsigned char online:1;
+       unsigned char batabs:1;
+       unsigned char te_en:1;
+       unsigned char otg_en:1;
+       unsigned char stat2;
+};
+
+struct rt5036_misc_info {
+       struct i2c_client *i2c;
+       struct device *dev;
+#ifdef CONFIG_MISC_RT5036_PWRKEY
+       struct input_dev *pwr_key;
+       unsigned char pwr_key_pressed:1;
+#endif                         /* #ifdef CONFIG_MISC_RT5036_PWRKEY */
+};
+
+struct rt5036_rtc_info {
+       struct i2c_client *i2c;
+       struct device *dev;
+       struct rtc_device *rtc;
+};
+
+struct rt5036_chip {
+       struct i2c_client *i2c;
+       struct rt5036_charger_info *chg_info;
+       struct rt5036_misc_info *misc_info;
+       struct rt5036_rtc_info *rtc_info;
+       struct mutex io_lock;
+       unsigned char suspend:1;
+};
+
+#ifdef CONFIG_CHARGER_RT5036
+void rt5036_charger_irq_handler(struct rt5036_charger_info *ci,
+                               unsigned int event);
+#endif /* #ifdef CONFIG_CHARGER_RT5036 */
+#ifdef CONFIG_MISC_RT5036
+void rt5036_misc_irq_handler(struct rt5036_misc_info *mi, unsigned int event);
+#endif /* #ifdef CONFIG_MISC_RT5036 */
+#ifdef CONFIG_RTC_RT5036
+void rt5036_rtc_irq_handler(struct rt5036_rtc_info *ri, unsigned int event);
+#endif /* #ifdef CONFIG_RTC_RT5036 */
+
+extern int rt5036_reg_block_read(struct i2c_client *i2c, int reg, int byte,
+                                void *dest);
+extern int rt5036_reg_block_write(struct i2c_client *i2c, int reg, int byte,
+                                 void *dest);
+extern int rt5036_reg_read(struct i2c_client *i2c, int reg);
+extern int rt5036_reg_write(struct i2c_client *i2c, int reg,
+                           unsigned char data);
+extern int rt5036_assign_bits(struct i2c_client *i2c, int reg,
+                             unsigned char mask, unsigned char data);
+extern int rt5036_set_bits(struct i2c_client *i2c, int reg, unsigned char mask);
+extern int rt5036_clr_bits(struct i2c_client *i2c, int reg, unsigned char mask);
+
+extern int rt5036_core_init(struct device *dev,
+                           struct rt5036_platform_data *pdata);
+extern int rt5036_core_deinit(struct device *dev);
+
+#ifdef CONFIG_MFD_RT5036_DBGINFO
+#define RTINFO(format, args...) \
+       pr_info("%s:%s() line-%d: " format, RT5036_DEV_NAME, __func__, \
+               __LINE__, ##args)
+#else
+#define RTINFO(format, args...)
+#endif /* CONFIG_MFD_RT5036_DBGINFO */
+#endif /* #ifndef _LINUX_MFD_RT5036_H */

diff --git a/include/linux/power/rt-battery.h b/include/linux/power/rt-battery.h
new file mode 100755 (executable)
index 0000000..ab0c7da
--- /dev/null
+++ b/include/linux/power/rt-battery.h
@@ -0,0 +1,19 @@
+/*
+ *  include/linux/power/rt-battery.h
+ *  Include header file for Richtek Richtek Battery Driver
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#ifndef __LINUX_RT_BATTERY_H
+#define __LINUX_RT_BATTERY_H
+
+#define RT_BATT_NAME   "rt-battery"
+
+#endif /* #ifndef __LINUX_RT_BATTERY_H */

diff --git a/include/linux/power/rt-power.h b/include/linux/power/rt-power.h
old mode 100755 (executable)
new mode 100644 (file)
index 7c5b64a..7533548
--- a/include/linux/power/rt-power.h
+++ b/include/linux/power/rt-power.h
@@ -1,6 +1,6 @@
 /*
- *  include/linux/power/rt5025/rt-power.h
- *  Include header file for Richtek RT5025 Core charger Driver
+ *  include/linux/power/rt-power.h
+ *  Include header file for Richtek Richtek Power Driver
  *
  *  Copyright (C) 2014 Richtek Technology Corp.
  *  cy_huang <cy_huang@richtek.com>

diff --git a/include/linux/power/rt5036-charger.h b/include/linux/power/rt5036-charger.h
new file mode 100755 (executable)
index 0000000..6ea60e3
--- /dev/null
+++ b/include/linux/power/rt5036-charger.h
@@ -0,0 +1,72 @@
+/*
+ *  include/linux/power/rt5036-charger.h
+ *  Include header file for Richtek RT5036 Charger Driver
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#ifndef _LINUX_POWER_RT5036_CHARGER_H
+#define _LINUX_POWER_RT5036_CHARGER_H
+
+enum {
+       CHGEVENT_STAT2ALT,
+       CHGEVENT_CHBSTLOWVI = 5,
+       CHGEVENT_BSTOLI,
+       CHGEVENT_BSTVIMIDOVP,
+       CHGEVENT_CHTMRFI = 10,
+       CHGEVENT_CHRCHGI,
+       CHGEVENT_CHTERMI,
+       CHGEVENT_CHBATOVI,
+       CHGEVENT_CHRVPI = 15,
+       CHGEVENT_BATABSENSE,
+       CHGEVENT_CHBADADPI,
+       CHGEVENT_VINCHGPLUGOUT,
+       CHGEVENT_VINCHGPLUGIN,
+       CHGEVENT_PPBATLVI,
+       CHGEVENT_IEOCI,
+       CHGEVENT_VINOVPI,
+       CHGEVENT_MAX,
+};
+
+#define RT5036_CHGTEEN_MASK    0x08
+
+#define RT5036_CHGIPREC_MASK   0x18
+#define RT5036_CHGIPREC_SHIFT  3
+
+#define RT5036_CHGIEOC_MASK    0x07
+
+#define RT5036_CHGVPREC_MASK   0x0F
+
+#define RT5036_CHGBATLV_MASK   0x07
+
+#define RT5036_CHGVRECHG_MASK  0x0C
+#define RT5036_CHGVRECHG_SHIFT 2
+
+#define RT5036_CHGSTAT_MASK    0x30
+#define RT5036_CHGSTAT_SHIFT   4
+#define RT5036_CHGDIS_MASK     0x01
+#define RT5036_CHGAICR_MASK    0xE0
+#define RT5036_CHGAICR_SHIFT   5
+#define RT5036_CHGICC_MASK     0xF0
+#define RT5036_CHGICC_SHIFT    4
+#define RT5036_CHGCV_MASK      0xFC
+#define RT5036_CHGCV_SHIFT     2
+#define RT5036_CHGOPAMODE_MASK 0x01
+#define RT5036_CHGOPASTAT_MASK 0x08
+
+#define RT5036_PWRRDY_MASK     0x80
+#define RT5036_TSEVENT_MASK    0x0F
+#define RT5036_TSWC_MASK       0x06
+#define RT5036_TSHC_MASK       0x09
+#define RT5036_CCJEITA_MASK    0x80
+#define RT5036_CHGOTGEN_MASK   0x40
+#define RT5036_BATDEN_MASK     0x80
+#define RT5036_TERST_MASK      0x10
+
+#endif /* #ifndef _LINUX_POWER_RT5036_CHARGER_H */

diff --git a/include/linux/regulator/rt5036-regulator.h b/include/linux/regulator/rt5036-regulator.h
new file mode 100755 (executable)
index 0000000..e6578b7
--- /dev/null
+++ b/include/linux/regulator/rt5036-regulator.h
@@ -0,0 +1,91 @@
+/*
+ *  include/linux/regulator/rt5036-regulator.h
+ *  Include header file to Richtek RT5036 Regulator driver
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#ifndef __LINUX_RT5036_REGULATOR_H
+#define __LINUX_RT5036_REGULATOR_H
+
+/*BUCK*/
+#define RT5036_DCDCVOUT_SHIFT1 0
+#define RT5036_DCDCVOUT_MASK1  0x7F
+#define RT5036_DCDCVOUT_SHIFT2 0
+#define RT5036_DCDCVOUT_MASK2  0x7F
+#define RT5036_DCDCVOUT_SHIFT3 0
+#define RT5036_DCDCVOUT_MASK3  0x7F
+#define RT5036_DCDCVOUT_SHIFT4 0
+#define RT5036_DCDCVOUT_MASK4  0x7F
+#define RT5036_DCDCEN_MASK1    0x08
+#define RT5036_DCDCEN_MASK2    0x04
+#define RT5036_DCDCEN_MASK3    0x02
+#define RT5036_DCDCEN_MASK4    0x01
+#define RT5036_DCDCMODE_MASK1  0x80
+#define RT5036_DCDCMODE_MASK2  0x40
+#define RT5036_DCDCMODE_MASK3  0x20
+#define RT5036_DCDCMODE_MASK4  0x10
+#define RT5036_DCDCRAMP_MASK1  0xC0
+#define RT5036_DCDCRAMP_SHIFT1 6
+#define RT5036_DCDCRAMP_MASK2  0x30
+#define RT5036_DCDCRAMP_SHIFT2 4
+#define RT5036_DCDCRAMP_MASK3  0x0C
+#define RT5036_DCDCRAMP_SHIFT3 2
+#define RT5036_DCDCRAMP_MASK4  0x03
+#define RT5036_DCDCRAMP_SHIFT4 0
+
+/*LDO*/
+#define RT5036_LDOVOUT_SHIFT1  0
+#define RT5036_LDOVOUT_MASK1   0x7F
+#define RT5036_LDOVOUT_SHIFT2  0
+#define RT5036_LDOVOUT_MASK2   0x7F
+#define RT5036_LDOVOUT_SHIFT3  0
+#define RT5036_LDOVOUT_MASK3   0x7F
+#define RT5036_LDOVOUT_SHIFT4  0
+#define RT5036_LDOVOUT_MASK4   0x7F
+#define RT5036_LDOEN_MASK1     0x80
+#define RT5036_LDOEN_MASK2     0x40
+#define RT5036_LDOEN_MASK3     0x20
+#define RT5036_LDOEN_MASK4     0x10
+#define RT5036_LDOMODE_MASK1   0x80
+#define RT5036_LDOMODE_MASK2   0x40
+#define RT5036_LDOMODE_MASK3   0x20
+#define RT5036_LDOMODE_MASK4   0x10
+#define RT5036_LDORAMP_MASK1   0xC0
+#define RT5036_LDORAMP_SHIFT1  6
+#define RT5036_LDORAMP_MASK2   0x30
+#define RT5036_LDORAMP_SHIFT2  4
+#define RT5036_LDORAMP_MASK3   0x0C
+#define RT5036_LDORAMP_SHIFT3  2
+#define RT5036_LDORAMP_MASK4   0x03
+#define RT5036_LDORAMP_SHIFT4  0
+
+/*LSW*/
+#define RT5036_LSWVOUT_SHIFT1  0
+#define RT5036_LSWVOUT_MASK1   0x7F
+#define RT5036_LSWVOUT_SHIFT2  0
+#define RT5036_LSWVOUT_MASK2   0x7F
+#define RT5036_LSWNEN_MASK2    0x02
+#define RT5036_LSWNEN_MASK1    0x01
+#define RT5036_LSWSEN_MASK2    0x08
+#define RT5036_LSWSEN_MASK1    0x04
+#define RT5036_LSWNMODE_MASK2  0x80
+#define RT5036_LSWNMODE_MASK1  0x40
+#define RT5036_LSWSMODE_MASK2  0x08
+#define RT5036_LSWSMODE_MASK1  0x04
+#define RT5036_LSWNRAMP_MASK2  0xC0
+#define RT5036_LSWNRAMP_SHIFT2 6
+#define RT5036_LSWNRAMP_MASK1  0x30
+#define RT5036_LSWNRAMP_SHIFT1 4
+#define RT5036_LSWSRAMP_MASK2  0x0C
+#define RT5036_LSWSRAMP_SHIFT2 2
+#define RT5036_LSWSRAMP_MASK1  0x03
+#define RT5036_LSWSRAMP_SHIFT1 0
+
+#endif /* __LINUX_RT5036_REGULATOR_H */

diff --git a/include/linux/rk_fb.h b/include/linux/rk_fb.h
index f4a1c3785033a0bfc12e99f53c464aaf30c5e40b..883483e5d7368273d4031da0a5e4cc0ef0a2de31 100755 (executable)
--- a/include/linux/rk_fb.h
+++ b/include/linux/rk_fb.h
@@ -54,6 +54,7 @@
 #define RK_FBIOGET_16OR32                              0X4621
 #define RK_FBIOGET_IDLEFBUff_16OR32                    0X4622
 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS                0X4623
+#define RK_FBIOSET_HWC_ADDR                            0x4624
 
 #define RK_FBIOGET_DMABUF_FD                           0x5003
 #define RK_FBIOSET_DMABUF_FD                           0x5004

diff --git a/include/linux/rockchip/iomap.h b/include/linux/rockchip/iomap.h
index 276ce2c7394b8d7b76a4abe632d84dfbbae41133..8aca1604b15ea209ae52024088ab1a02ee66e902 100755 (executable)
--- a/include/linux/rockchip/iomap.h
+++ b/include/linux/rockchip/iomap.h
@@ -17,6 +17,7 @@
 #define RK_DEBUG_UART_VIRT              RK_IO_ADDRESS(0x00060000)
 #define RK_CPU_AXI_BUS_VIRT             RK_IO_ADDRESS(0x00070000)
 #define RK_TIMER_VIRT                   RK_IO_ADDRESS(0x00080000)
+#define RK_PWM_VIRT                    RK_IO_ADDRESS(0x00088000)
 #define RK_GIC_VIRT                     RK_IO_ADDRESS(0x00090000)
 #define RK_BOOTRAM_VIRT                 RK_IO_ADDRESS(0x000a0000)
 #define RK_DDR_VIRT                     RK_IO_ADDRESS(0x000d0000)
@@ -177,5 +178,7 @@
 #define RK312X_EFUSE_SIZE               RK3036_EFUSE_SIZE
 #define RK312X_PMU_PHYS                        0x100a0000
 #define RK312X_PMU_SIZE                        SZ_64K
+#define RK312X_PWM_PHYS                        0x20050000
+#define RK312X_PWM_SIZE                        SZ_16K
 
 #endif

diff --git a/include/linux/rtc/rtc-rt5036.h b/include/linux/rtc/rtc-rt5036.h
new file mode 100755 (executable)
index 0000000..2ddb801
--- /dev/null
+++ b/include/linux/rtc/rtc-rt5036.h
@@ -0,0 +1,39 @@
+/*
+ *  include/linux/rtc/rt5036-rtc.h
+ *  Include header file for Richtek RT5036 RTC Driver
+ *
+ *  Copyright (C) 2014 Richtek Technology Corp.
+ *  cy_huang <cy_huang@richtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#ifndef _LINUX_RTC_RT5036_RTC_H
+#define _LINUX_RTC_RT5036_RTC_H
+
+enum {
+       RTCEVENT_CAIRQ,
+       RTCEVENT_CDIRQ,
+       RTCEVENT_MAX,
+};
+
+#define RT5036_RTC_SECMASK     0x3F
+#define RT5036_RTC_MINMASK     0x3F
+#define RT5036_RTC_HOURMASK    0x1F
+#define RT5036_RTC_YEARMASK    0x7F
+#define RT5036_RTC_MONMASK     0x0F
+#define RT5036_RTC_DAYMASK     0x1F
+#define RT5036_RTC_WEEKMASK    0xE0
+#define RT5036_RTC_WEEKSHIFT   5
+
+#define RT5036_STBCTL_MASK     0x01
+#define RT5036_RTCCDEN_MASK    0x02
+#define RT5036_RTCAEN_MASK     0x04
+
+#define RT5036_RTCCDIRQ_MASK   0x02
+#define RT5036_RTCAIRQ_MASK    0x01
+
+#endif /* #ifndef _LINUX_RTC_RT5036_RTC_H */

diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
old mode 100644 (file)
new mode 100755 (executable)
index c5ae2dd..dd645b7
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -33,6 +33,14 @@ choice
 endchoice
 endif #SND_RK_SOC && RK_HDMI
 
+config SND_RK_SOC_CARD_SPDIF
+       tristate "SoC spdif card support for rockchip"
+       depends on !SND_RK_SOC_HDMI_SPDIF
+               select SND_RK_SOC_SPDIF
+               select SND_SOC_HDMI_SPDIF
+
+
+
 config SND_RK_SOC_AK4396
        tristate "SoC I2S Audio support for rockchip - AK4396"
        depends on SND_RK_SOC

diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
old mode 100644 (file)
new mode 100755 (executable)
index 9fbecd9..a544bfb
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -69,5 +69,6 @@ obj-$(CONFIG_SND_RK_SOC_RK3026) += snd-soc-rk3026.o
 obj-$(CONFIG_SND_RK_SOC_RK3190) += snd-soc-rk3190.o
 obj-$(CONFIG_SND_RK_SOC_RT5512) += snd-soc-rt5512.o
 obj-$(CONFIG_SND_RK_SOC_CX2070X) += snd-soc-cx2070x.o
+obj-$(CONFIG_SND_RK_SOC_CARD_SPDIF) += snd-soc-hdmi-spdif.o
 obj-$(CONFIG_SND_RK_SOC_HDMI_I2S) += snd-soc-hdmi-i2s.o
 obj-$(CONFIG_SND_RK_SOC_HDMI_SPDIF) += snd-soc-hdmi-spdif.o

diff --git a/sound/soc/rockchip/rk_hdmi_spdif.c b/sound/soc/rockchip/rk_hdmi_spdif.c
index ad1616e4365717c69976ae1a0eefe643d218873e..c8ecb84a900b64fe5bbf61c225cbdf0a0d103961 100755 (executable)
--- a/sound/soc/rockchip/rk_hdmi_spdif.c
+++ b/sound/soc/rockchip/rk_hdmi_spdif.c
@@ -32,66 +32,16 @@
 #define RK_SPDIF_DBG(x...) do { } while (0)
 #endif
 
-static int set_audio_clock_rate(unsigned long pll_rate,
-                               unsigned long audio_rate)
-{
-       struct clk *sclk_spdif;
-#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188)
-       struct clk *hclk_spdif;
-#endif
-
-#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188)
-       hclk_spdif = clk_get(NULL, "hclk_spdif");
-       if (IS_ERR(hclk_spdif)) {
-               pr_err("spdif:failed to get hclk_spdif\n");
-               return -ENOENT;
-       }
-
-       clk_set_rate(hclk_spdif, pll_rate);
-       clk_put(hclk_spdif);
-#endif
-
-       sclk_spdif = clk_get(NULL, "spdif");
-       if (IS_ERR(sclk_spdif)) {
-               pr_err("spdif:failed to get sclk_spdif\n");
-               return -ENOENT;
-       }
-
-       clk_set_rate(sclk_spdif, audio_rate);
-       clk_put(sclk_spdif);
-
-       return 0;
-}
-
 static int rk_hw_params(struct snd_pcm_substream *substream,
-               struct snd_pcm_hw_params *params)
+                       struct snd_pcm_hw_params *params)
 {
        struct snd_soc_pcm_runtime *rtd = substream->private_data;
        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-       struct snd_soc_dai *codec_dai = rtd->codec_dai;
-       unsigned long pll_out, rclk_rate, dai_fmt = rtd->dai_link->dai_fmt;
+       unsigned long pll_out, rclk_rate;
        int ret, ratio;
 
        RK_SPDIF_DBG("spdif:Entered %s\n", __func__);
 
-       return 0;
-
-       /* set codec DAI configuration */
-       ret = snd_soc_dai_set_fmt(codec_dai, dai_fmt);
-       if (ret < 0) {
-               pr_err("%s():failed to set the format for codec side\n",
-                       __func__);
-               return ret;
-       }
-
-       /* set cpu DAI configuration */
-       ret = snd_soc_dai_set_fmt(cpu_dai, dai_fmt);
-       if (ret < 0) {
-               pr_err("%s():failed to set the format for cpu side\n",
-                       __func__);
-               return ret;
-       }
-
        switch (params_rate(params)) {
        case 44100:
                pll_out = 11289600;
@@ -114,7 +64,8 @@ static int rk_hw_params(struct snd_pcm_substream *substream,
        rclk_rate = params_rate(params) * ratio;
 
        /* Set audio source clock rates */
-       ret = set_audio_clock_rate(pll_out, rclk_rate);
+       ret = snd_soc_dai_set_sysclk(cpu_dai, 0,
+                                    rclk_rate, SND_SOC_CLOCK_IN);
        if (ret < 0)
                return ret;
 
@@ -148,7 +99,7 @@ static int rockchip_hdmi_spdif_audio_probe(struct platform_device *pdev)
        ret = rockchip_of_get_sound_card_info_(card, false);
        if (ret) {
                pr_err("%s() get sound card info failed:%d\n",
-                       __func__, ret);
+                      __func__, ret);
                return ret;
        }
 
@@ -156,7 +107,7 @@ static int rockchip_hdmi_spdif_audio_probe(struct platform_device *pdev)
 
        if (ret)
                pr_err("%s() register card failed:%d\n",
-                       __func__, ret);
+                      __func__, ret);
 
        return ret;
 }

diff --git a/sound/soc/rockchip/rk_spdif.c b/sound/soc/rockchip/rk_spdif.c
index e59ca12f974970d77723dbac682073e4b794be23..da0cf7bbbd4c2f8dba9d8b5777ec241e8bed062c 100755 (executable)
--- a/sound/soc/rockchip/rk_spdif.c
+++ b/sound/soc/rockchip/rk_spdif.c
@@ -187,6 +187,7 @@ static int spdif_set_syclk(struct snd_soc_dai *
        RK_SPDIF_DBG("Entered %s sysclk=%d\n", __func__, freq);
 
        spdif->clk_rate = freq;
+       clk_set_rate(spdif->clk, freq);
 
        return 0;
 }