ARM: dts: sun6i: Add security system crypto engine clock and device nodes

A31/A31s have the same "Security System" crypto engine as A10/A20,
but with a separate reset control.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 008047a018cf2b645cc85136c194be665376c5ef..e79c14d3db2b93ba061863cfbb502128349af71e 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -346,6 +346,14 @@
                                             "mmc3_sample";
                };
 
+               ss_clk: clk@01c2009c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
+                       reg = <0x01c2009c 0x4>;
+                       clocks = <&osc24M>, <&pll6 0>;
+                       clock-output-names = "ss";
+               };
+
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -870,6 +878,16 @@
                        #size-cells = <0>;
                };
 
+               crypto: crypto-engine@01c15000 {
+                       compatible = "allwinner,sun4i-a10-crypto";
+                       reg = <0x01c15000 0x1000>;
+                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ahb1_gates 5>, <&ss_clk>;
+                       clock-names = "ahb", "mod";
+                       resets = <&ahb1_rst 5>;
+                       reset-names = "ahb";
+               };
+
                timer@01c60000 {
                        compatible = "allwinner,sun6i-a31-hstimer",
                                     "allwinner,sun7i-a20-hstimer";