/*
- * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
- * 32-byte cachelines. The default configuration is not for SMP anyway,
- * so if you're building for SMP, you should select the appropriate
- * processor type. There is a potential livelock danger when running
- * a machine with this value set too small, but it's more probable you'll
- * just ruin performance.
+ * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
+ * have 32-byte cachelines. The L1 length appears to be 16 bytes but this
+ * is not clearly documented.
*/
-#ifdef CONFIG_PA20
-#define L1_CACHE_BYTES 64
-#define L1_CACHE_SHIFT 6
-#else
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-#endif
+#define L1_CACHE_BYTES 16
+#define L1_CACHE_SHIFT 4
#ifndef __ASSEMBLY__
#define __NR_memfd_create (__NR_Linux + 340)
#define __NR_bpf (__NR_Linux + 341)
#define __NR_execveat (__NR_Linux + 342)
+#define __NR_membarrier (__NR_Linux + 343)
+#define __NR_userfaultfd (__NR_Linux + 344)
-#define __NR_Linux_syscalls (__NR_execveat + 1)
+#define __NR_Linux_syscalls (__NR_userfaultfd + 1)
#define __IGNORE_select /* newselect */
ENTRY_SAME(memfd_create) /* 340 */
ENTRY_SAME(bpf)
ENTRY_COMP(execveat)
+ ENTRY_SAME(membarrier)
+ ENTRY_SAME(userfaultfd)
.ifne (. - 90b) - (__NR_Linux_syscalls * (91b - 90b))
{
struct resource *tmp;
+ /* exit if not a C8000 */
+ if (boot_cpu_data.cpu_type < mako)
+ return end;
+
pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n",
end - start, lba_len);
pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end);
- if (boot_cpu_data.cpu_type < mako) {
- pr_info("LBA: Not a C8000 system - not extending LMMIO range.\n");
- return end;
- }
end += lba_len;
if (end < start) /* fix overflow */
pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space,
lba_dev->hba.lmmio_space_offset);
if (lba_dev->hba.gmmio_space.flags) {
+ /* Not registering GMMIO space - according to docs it's not
+ * even used on HP-UX. */
/* pci_add_resource(&resources, &lba_dev->hba.gmmio_space); */
- pr_warn("LBA: Not registering GMMIO space %pR\n",
- &lba_dev->hba.gmmio_space);
}
pci_add_resource(&resources, &lba_dev->hba.bus_num);
return 0;
}
-struct tty_driver *mux_console_device(struct console *co, int *index)
-{
- *index = co->index;
- return mux_driver.tty_driver;
-}
-
static struct console mux_console = {
.name = "ttyB",
.write = mux_console_write,
- .device = mux_console_device,
+ .device = uart_console_device,
.setup = mux_console_setup,
.flags = CON_ENABLED | CON_PRINTBUFFER,
.index = 0,
+ .data = &mux_driver,
};
#define MUX_CONSOLE &mux_console
u16 queues[0];
};
#define XPS_MAP_SIZE(_num) (sizeof(struct xps_map) + ((_num) * sizeof(u16)))
-#define XPS_MIN_MAP_ALLOC ((L1_CACHE_BYTES - sizeof(struct xps_map)) \
- / sizeof(u16))
+#define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
+ - sizeof(struct xps_map)) / sizeof(u16))
/*
* This structure holds all XPS maps for device. Maps are indexed by CPU.